TW200818206A - High-performance flash memory data transfer - Google Patents

Abstract

A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a "legacy" mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, data is read at a higher frequency, for example at twice the frequency, of that available in the normal mode. In the advanced mode, the input data is presented by the controller at a higher frequency than is available in the normal mode. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Description

200818206 IX. DESCRIPTION OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to the field of flash memory devices, and in particular, the present invention is directed to interfacing between a flash memory device and a memory controller in an electronic system. Information communication. [Prior Art] As is well known in the art, a "flash" memory system electrically erasable semiconductor memory device can be erased and rewritten in units of cell blocks instead of being electrically erasable as before. The read-only memory (eepr〇m) device performs erasing and rewriting on a full-wafer or large-block basis. For its part, flash memory has become particularly popular in applications where the non-volatile nature of stored data (i.e., data retention after unpowered) is a fundamental point, but the rewriting frequency is relatively low. Examples of popular applications for flash memory include a portable audio player, a &quot;SIM&quot; card for storing phone numbers and voice records in a counter phone handset, &quot;thumbkey for computers and workstations, detachable Storage devices, storage devices for digital cameras, and the like. An important recent development in semiconductor non-volatile memory technology: configuring flash memory cells as "NAND" memory instead of configured as ' 'NOR' memory. As is known in the art, N0R flash memory means a conventional configuration in which a row of memory cells is connected in parallel between a bit line and a source line. Accessing a specific one in a NOR line The mode of the memory cell is to drive the word line (control gate) of the memory cell to be in an active state while maintaining other memory cells in the row, such that between the bit line and the source line The current is determined by the state of the accessed memory cell. 120269.doc 200818206 In another aspect, the memory cells in a row of NAND memory are connected in series to the bit line and the source line. Therefore, accessing a special A-body unit 70 in a NAND row requires: opening all memory cells in the row with the active word line level; and applying the _ intermediate word line level to be accessed. The memory unit such that the current between the bit line and the source line is again determined by the state of the accessed memory unit. As is well known in the art, each bit of the NAND flash memory The required area is significantly smaller than the area required for each bit of the flash memory. The main reason is that a row of NAND memory requires fewer conductors than the NOR memory (and therefore the car is: &gt; In addition, in the NAND configuration, a large number of memory cells share a common access transistor. In addition, conventional NAND flash memory can be easily accessed continuously, for example, by successive rows Access memory cells, rather than random access memory in the case of NOR memory. Therefore, 'NAND memory is especially suitable for music and video storage applications. Another important recent in the field of flash memory Progress in this technology Multilevel pr〇gram (MLC). According to this approach, each memory unit may have more than two states by simply controlling the stylization of memory cells. In the conventional binary data storage, each memory unit is programmed into a τ state. The way to read such a binary memory unit is to apply a single control voltage to the control gate of the address memory unit. Thus, if programmed to the "1&quot; state, the transistor is turned on, but if it is, the state, the state turns off the transistor; therefore, the sense of transmission through the address memory unit is returned to the memory. Stylized state. In contrast, according to the typical example of the practice of 120269.doc 200818206, four possible states are defined for each memory cell, typically corresponding to binary values 00, 〇!, 10, n. In effect, the two intermediate states correspond to two levels of localization of the memory cells between the fully erased state and the fully programmed state. It is known that one of the fast-track 3 recalls having up to eight states or three binary bits per memory cell is also implemented. Y-a — her plan. Two or three bits of data stored on the parent-memory unit directly double or triple the data capacity of the memory cell wafer. Examples of MLC flash memory cells and memories including such (4) memory are described in U.S. Patent No. 5,172,338 and U.S. Patent No. 6,747,892 B2. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The combination of MLC technology and the efficiency of the NAN_flash memory architecture has resulted in a significant reduction in the cost per bit for semiconductor non-volatile memories, and has led to improved system reliability, as well as higher data capacity for a given form factor. System functions. However, despite these important improvements, the data transfer rate to and from conventional flash memory devices has not yet progressed. A modernized flash memory application is particularly susceptible to data transfer rates: as data capacity increases. For example, the resolution of high-performance professional-grade i-bit still cameras can now exceed 1 megapixel. The progress of MLC NAND flash memory for this is welcome. However, the person = continues the "shutter lag between image capture," (-(10) depends on the data transfer rate of the image data from the second to the flash memory. The delay between the two is clearer than the shot. (4), the parameters between the extensions are not dependent on the image resolution, which is becoming a key factor in the camera 120269.doc 200818206. Especially as the image resolution continues to be large MS ^trr ^ ία U The "Beet" season is not enough to achieve the desired delay between images. The data transfer time of the flash memory is not compatible with the data transfer time of modern disk drives. Of course, this is another new application for flash memory. Accordingly, (10) 吏 flash memory meets the needs of modern high-performance digital still cameras, or flash memory as a modern high-performance electronic system, full-size solid storage, which will make flash memory a must Achieve higher data transfer rates to and from the flash memory device. ,. An example of a conventional data transfer practice for flash memory is described in the worksheet 2 GBIT (256 Mx8 BITS) CMOS NAND E2PR〇m, part number D58 HVGNVG1S3AFT05 (Toshiba, 2003). The conventional practice involves an octet data bus in which each cycle of the enable day sigmoid is enabled to synchronize the edge of the read enable clock to provide a data output on each data output. Bit. Furthermore, as described in the data sheet, this conventional practice involves a 3.3 volt logic standard such that the minimum high logic level output voltage (v〇h) is 24 volts and the maximum low logic The level output voltage (v〇l) is 〇·4 volts. The maximum data rate for this device is 20 MHz. It is believed that this data rate is not the data rate required for a large storage device in a personal computer system, making such conventional flash registers not suitable as a disk drive replacement. By means of some conventional dynamic random access memory (RAM), the so-called double data rate (DDR) data transfer technology is realized. As is known in the art, the material transfer involves synchronizing the rising edge and the falling edge of the corresponding data strobe or clock. 120269.doc 200818206 Transmitting one or more data bits (depending on the number of bus bars) . Thus, ddr data transfer conveys data at twice the data rate of conventional synchronous data transfer (which is synchronized to only one of the clock edges (rising edge or falling edge)). In addition, conventional DDR dynamic RAM utilizes source synchronous data strobe, wherein the RAM device itself generates data strobes for reading from memory (and external circuitry generates data strobes for writing to memory). However, this doubling of the input/output switching rate increases the power consumption of the data transfer, which is close to twice the power consumption of the single data rate communication. '

But 'in modern electronic systems, power consumption is a major concern' and significant power consumption in the overall system power consumption of the busbars and conductors in the process of transferring data between integrated circuit devices in the system. By. Based on the technology, the power consumption of the output driver used to drive the external conductor is directly (four) the switching rate of the digital signal to be driven. Therefore, as mentioned above, increasing the data transfer to the data of modern magnetic money requires a corresponding increase in the power consumed by such data transfer, and all other parameters remain equal. This increased power consumption requires greater heat dissipation and the like in both the driver and receiver devices & good system applications, which increases overall system cost. Even with these changes, the increased power consumption from high-speed data transfer for portable two-subsystems (such as digital cameras, laptops and workstations, wireless phone handsets, personal digital audio players, and similar battery-powered devices) is not required. Λ 进 背景 背景 背景 背景 DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA ^. Fig. 120269.doc -10 - 200818206 This kind of conventional flash memory card, constructed and operated according to the well-known standard CF+ and CompactFlash specification version 3.0 (2004 CompactFlash Association). As shown, the flash memory card 2 (in this example, the flash memory card is constructed as a COMPACT FLASH memory according to this standard) includes one or more flash memory modules 4 and a single chip memory controller 6. The flash memory module 4 transmits data to and from the memory controller 6 through the bus dataJ/O and transmits control numbers to and from the memory controller 6 through the bus Ctrl. In this example, the foregoing The data transfer method described in the cited T〇shiba data worksheet corresponds to communication between the flash memory module 4 and the memory controller 6 through the data-I/O bus and the Ctrl bus. The controller 6 communicates with a host device (such as a 'digital camera, a digital audio player, a personal computer, etc.) through the host interface HOST_IF. The CF+ and CompactFlash specifications cited above describe the communication through the host interface HOSTJF, including according to the ultra DMA Mode C. 'UDMA&quot;). As described in this specification, UDMA communication is carried out in a special mode of operation by means of a proxy (host or memory card 2) requiring such communication on a control line (UDMARQ). Drive a signal to start. As described in this specification, the UDMA data transfer source is synchronized because the agent (memory card 2 or host system) that is placing the data on the bus H〇ST jF is also Release the data selection communication number. In addition, as described in this specification, in the UDMA operation mode, the rising edge of the selected communication number is used in data transmission. Both edges are dropped. However, it has been observed that, in conjunction with the present invention, even if the UDMA mode is used for the host interface in the flash memory card of Figure 1, the memory module 4 and 120269.doc -11-200818206 memory control The Bellow transport rate between the devices 6 will still limit the overall performance of the memory card 2. However, the data transfer acceleration of the interface of Taizhi Yuxu &quot; Increase the number of ten 咅 I#? # μ丄+ Power consumption in the U body card 2. In addition, the technology is known to modify the input/output interface of § 体积 体积 雷 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 SUMMARY OF THE INVENTION The purpose of the present invention is to provide a method for transferring data to and from a memory controller in a flash memory module operating in a high-performance data transfer mode. The purpose of the sub-U's advancement is to provide a method for mass transfer in accordance with the high-efficiency mode: the rate of power consumption is substantially no greater than the rate at which the conventional data transfer consumes power. A further object of the present invention is to provide a method for the slab t &amp; a method in which the 'information communication' can also be implemented to provide backtracking compatibility with the conventional transmission standard of the prior art. The purpose is to eliminate the method of data distortion in the high-performance data transmission plate type of I, ... /曰. Other objects and advantages of the present invention will become apparent to those skilled in the art from this disclosure. Two: The first aspect of Ming 2 can be implemented in a multi-mode data library: body device. In an old mode, the data interface provides or receives data by means of an externally generated data strobe, wherein each of the strobes conveys a ', π V body. Bit. In an advanced mode 120269.doc •12· 200818206, the data interface is synchronized to two polarity options, mussel 兀 or word sync (rising down). The :: reduced electric house swing ' is used to reduce power consumption. In the 丄 丄 模式 mode, 'for the command and control communication, continue to use the automation control material, the material operation mode to raise the material timeout and other

= month - the first - the evil sample can be implemented in - with multi-mode data + flash: in the memory device. In an old mode, the data interface provides or receives data at 5 V in an externally generated data strobe, communicating each conductor-bit in each of the strobes. In the advanced mode, 'the data interface is source synchronized', one of the data bits or word sync = one of the selected communication numbers - the rising and falling edges - the frequency is the frequency of the sales mode of operation Times. A reduced voltage swing is provided for the advanced mode to reduce power consumption. In the advanced mode for stimulating data transfer, the old mode of operation is continued for command and control communication; data timeout and other automated control functions are provided for the advanced mode of operation. A third aspect of the present invention can be implemented in a flash memory device having a multi-mode data interface. In an old mode, the data interface provides or receives data in synchronization with externally generated data strobes, wherein one bit per conductor is communicated in each cycle of the strobe. In one of the old mode write operations, a write enable select communication number issued by a controller to the memory is clocked by the controller to each data word of the flash memory; In one of the read modes, the controller sends 120269.doc -13- 200818206 to the memory to enable a read enable communication number to time the flash memory to provide each data to the controller. word. In an advanced mode, the data interface is source synchronized, wherein a data bit or word is synchronized to the strobe edge of the read enable strobe and the write enable strobe. In one of the read modes, the flash memory device issues read strobes and write strobes that are different in phase from each other to time the alternate output data words. In one of the write operations of the advanced mode, the controller issues read strobe and write strobes that are different in phase from each other to time the alternate input material in the memory. A reduced voltage swing is provided for the advanced mode to reduce power consumption. In the advanced mode for priming data transfer, the old mode of operation is continued for command and control communications; data overtime and other automated control functions are provided for the advanced mode of operation. [Embodiment] The present invention will be described in connection with a preferred embodiment of the present invention, that is, implemented as a flash memory module, a subsystem including such a flash memory module, and a flash memory. The method of the module. Specifically, the exemplary flash memory module is described as a NAND type multi-level memory cell level cell; mlc) flash memory, because the present invention is expected to be particularly suitable for incorporating such flash memory. This results in the use of solid non-volatile memory in a large amount of lean storage in computer systems. However, it is contemplated that the present invention will be applicable to and beneficial to other applications involving various types of non-volatile solid state memories. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of the invention as claimed. 120269.doc • 14- 200818206 FIG. 2 illustrates an exemplary construction of a flash memory device (or module) 1〇 constructed in accordance with a preferred embodiment of the present invention. It is contemplated that the flash memory device 1G is typically constructed in a single product (four) way and that it can interface with a number of memory controllers or memory controller logic, as described in further detail below. The architecture of the flash (4) device shown in the pre-_2 is merely an example for understanding the purpose of the present invention, and those skilled in the art having reference to this specification can easily combine flashes different from those shown in FIG. The flash memory device architecture of the memory device architecture implements the present invention. The storage capacity of the Shaanxi flash device 10 resides in the flash memory array. The y-car array 12 includes electrically programmable and erasable memory cells arranged in columns and rows, as is well known in the art. Although a single array 12 is illustrated in FIG. 2, it is of course contemplated that the array 12 can be implemented as a plurality of sub-arrays, each having an individual instance of a peripheral integrated circuit (instanc, such as the example below with respect to FIG. 2). Part or all of the address, data or control circuitry is described in further detail. It is contemplated that those skilled in the art having reference to this specification will be able to readily implement the present invention in conjunction with such a multi-subarray architecture. The memory cell of array 12 is a floating gate metal oxide semiconductor (MOS) transistor that is constructed such that each such transistor (corresponding to a memory cell) can be electrically programmed and can also be powered Erase. According to a preferred embodiment of the present invention, the memory cells of array 12 are multi-level memory cells (MLCs) because their memory cells can be programmed to more than two data states (ie, Stylized to any of two or more threshold voltages such that each such memory cell stores a value of more than 120269.doc -15 - 200818206 bit digits. Further in accordance with the present invention The preferred embodiment of the present invention, as will be apparent from the following description, the memory cells are preferably arranged in % by the well-known NAND method, so that the memory is typically not accessed in a random manner. Accessing the 4th memory unit, the reason is that it helps a large number of applications, of course, it can also be combined with a binary memory unit (ie, only a single digital bit TL is stored), and combined with &gt; The present invention is applied to a memory unit. According to this preferred embodiment of the invention, the common input/output terminals 1/01 to I/On are provided and connected to the input/output control circuit 2A. It is known that the operation of the flash memory device is mostly controlled by the reception and execution of commands, and the commands are achieved by the input/output terminals 1/01 to Ι/On as digital words. Control logic 18 is executed. As such, input/output control circuit 2 receives control commands, address values, and input data, and drives and receives communications with input/output terminals 1/01 through Ι/On via them. Circuit to present Information and output data. It is expected that the number η of input/output terminals 1/〇1 to 1/〇11 is usually 8 or 16, however, any number of such terminals may of course be provided. Further, the input/output control circuit 20 receives power. Supplying voltage vec_R and driving input/output terminals 1/〇1 to 1/〇11 based on a logic level of the voltage. This preferred embodiment of the present invention will be described in detail below, this power supply voltage VCC_R The voltage used in the conventional flash memory device is such that the power consumption due to data transfer at the input/output terminals 1/〇1 to 1/〇11 is reduced, even at a higher switching rate. The logic i 8 also receives the power supply voltage Vec-R based on the voltage from the read enable terminal 120269.doc •16-200818206 RE, an output control signal that drives a lower voltage, and the like. The input/output control circuit 20 forwards the command information to the command register 24 for decoding and execution by the control logic 18 because the control logic 18 controls the operation of the flash memory device. In the conventional manner, status information is stored by the control logic 18 in the status register 23. In the conventional manner, the address values received by the input/output control circuit 20 at the input/output terminals 1/〇1 to 1/(11) are buffered in the address register 22; these addresses are buffered; The column portion is decoded by column decoder 11 and the row portion is decoded by row decoder 15 (each decoder typically includes a bit address buffer) to effect pair of one or more desired memory cells in array 12. Choice. The input/output control circuit 20 also performs two-way communication with the data buffer via the bus DATA_Bus to forward the data to be written to the data register 14 according to the data transmission direction to be executed, and The data is output from the data register 14. The control logic 18 also receives various direct control signals from the external to the flash memory device, including, for example, the following signal lines: the chip enables the CE one to enable the latch enable CLE, the address latch enable ALE, write Enable WE to enable RE and write protection line WP one. As is known in the art, the latch enable signal CLE and the address latch enable signal ALE indicate whether a command or address exists on the input/output terminals 1/01 to 1/11, and the enable signal WE is written. The read enable signal RE is used as a data strobe in the write operation and the read operation, respectively. In accordance with this embodiment of the invention, the input of the enable WE-signal to the flash memory device 10 is written. Accordingly, for transmitting data to the flash memory device 1 via the input/output terminals 1/01 to I/〇n, as writing 120269.doc • 17-200818206, the write data strobe for enabling the we-signal is enabled. It always originates from a device external to the flash memory device ίο, typically derived from the source of the transmitted data itself. However, also in accordance with this preferred embodiment of the present invention and as described in further detail below, the read enable RE signal is bidirectional. In the constant sad mode of operation, the external device (ie, the destination of the data from the flash memory array 12) is the source of the data strobe, and the input is the input to the 兄 兄 忆 忆 忆 装置 装置The read data strobe is carried to serve as a read enable RE signal. In an advanced mode of operation in accordance with a preferred embodiment of the present invention, control logic 18 issues a read data strobe as a read enable RE signal, which is synchronized to the self-flash memory, as described in further detail below. The volume array 12 reads the data and communicates the data via the data register 14, the 1/〇 control circuit 20, and the input/output terminals 1/〇1 to 1/〇11. 3 illustrates the implementation of a flash memory device (or module) 10 in a flash memory card in accordance with a preferred embodiment of the present invention. As shown in FIG. 3, the flash memory card 25 includes at least the flash memory device 1 itself and also includes the controller 30. The controller 30 provides and manages an external interface h〇st卩, interface h to the host system (such as a high-performance digital camera, a personal (four), or a portable device such as a digital audio player or a mobile phone handset or the like). 〇STjF# may correspond to a 'group external terminal' of the flash memory card 25 (which is constructed as a card for use in any of a wide variety of host systems), as is known in the art. . The interface H〇sT is expected to operate in accordance with conventional standard interfaces known in the art, or may be developed in conjunction with future flash memory interface standards or proprietary interface protocols. = As described above, the present invention is expected to be particularly advantageous for providing high speed data transfer, such as in data transfer rate critical applications for high performance digital still cameras. It is further contemplated that the high data transfer rates provided by the present invention may also enable the use of flash memory as a solid state mass storage device in a personal computer to replace the disk drive. It is expected that the interface H0STJF itself will optimally have high-speed data transfer capabilities, for example, the high-speed data transfer capabilities expected by the standards mentioned in the [Prior Art] above. As shown in FIG. 3, the flash memory device 10 is connected to the controller 30 in a manner similar to the terminal shown in FIG. In the case of ^4, an input/output bus is formed by the signal line I/0丨 to I/〇n (corresponding to the terminal of the same name of the flash memory device 10). A control bus CTRL couples the controller 30 to the flash memory device 1 and includes signal lines connected to the ale, CLE, WP, and CE-terminals shown in FIG. It is contemplated that other control lines and terminals may be provided for communication between the flash memory device 1 and the controller 3, and the control bus CTRL is depicted as a two-way bus' although it is shown in FIG. The ALE, CLE, wp, and CE-terminals serve as inputs to the flash memory device 10. In order to make this description clearer, FIG. 3 shows two control lines RE and WE_ separated from the control bus cTRL. According to this specific embodiment of the invention, the line WE carries a data strobe in a write operation (writing data from the controller 3 to the flash memory device 1G) and is itself connected to the flash Memory device! Terminal WE"_. According to a preferred embodiment of the present invention, in each-operation mode, the data warfare is derived from: the controller line RE - carried for reading operations (from the flash memory device 1 〇 The data strobe is read from the poor material and communicated to the controller 30), and its body is connected to the terminal RE of the flash memory device 10 (Fig. 2). As described above, [in accordance with the preferred embodiment of the present invention, the control line is a dual/direction: and the source of the read data strobe depends on the current operation pull of the flash memory device (4). In the normal mode of operation, the controller 30 issues the read data. • The meter (4) memory pack (4) responds to (4) the valid data present on the signal line - Ι/〇η. In a preferred embodiment of the present invention - an example: in an advanced mode of operation, the flash memory device 10 is an online RE-up (four) fetch (four) pass, and the secret is: #料自(四)Memory loading transport 0, as described in further detail below, the controller 30 transmits: the command transmitted by the fU tiger, line 1/〇1 to 1/〇11 is synchronized with the source of the beetle at the signal line. The flash memory device 10 is transmitting data to the mode of operation of the controller 30. Pre-J will construct the controller 3 according to the conventional flash memory control system known in the art, and modify it as needed to realize the combination according to the present invention. Flash memory of the preferred embodiment _ $ The operation described in the start, operation and termination of the read operation in the advanced mode of operation. It is also expected that the logical hardware, program instructions _ or its group ports that will be implemented in this advanced operating mode will be referred to in this specification. It is further contemplated that those skilled in the art will be able to readily add modifications to controller 30 to best suit a particular implementation without undue experimentation. And as also shown in Fig. 3, the power supply voltage VeeR is connected to and biased C to the flash, and each of the device 1〇 and the controller 3〇. This power supply voltage Vcc-r is lower than the voltage of 120269.doc -20-200818206 used in the conventional flash memory device and controller, so that the reduction is caused by the input/output terminals 1/01 to 1/〇11 and The power consumption of data transfer and transition at various control lines, even at higher switching rates, as described below. As described in detail below in conjunction with the specific examples, this power supply voltage may be at a nominal voltage of about U0 volts (ranging from about 1.60 volts to about 2. volts), which is substantially less than the conventional 3.3 volts. Nominal power supply voltage (ranging from approximately 2.70 volts to 3.60 volts). Referring now to Figures 4a through 4e, the operation of the flash memory device J 组合 combination controller 30 in the memory card 25 will now be described in a normal mode of operation and also in a known command communication mode. It is contemplated that their modes of operation will generally correspond to conventional flash memory interface protocols for modern flash memory devices, and that their operational modes will themselves be used as flash memory for use in accordance with preferred embodiments of the present invention. One of the "old" input/output protocols of the body device 10. Figure 4a illustrates the transmission of a command from the controller 30 to the flash memory device. As is known in the art, and as will be described in more detail below, modern flash memory devices operate in response to particular commands issued by the controller and specific commands communicated through the data input/output lines. In terms of its own, the actual implementation of the command CMD is implemented by the controller 30 driving the command latch enable signal CLE to a high active state, and the address latch enable signal ALE to a low The inactive state, which represents a command (not a single address) on the input/output lines 1/〇1 to 1/〇11. In a conventional manner, the wafer enable signal CE is enabled to be in an active low state to enable the flash memory device. As is known in the art, if a plurality of flash memory devices 10 are provided within the card 25, then when When the flash memory device for communication in the flash memory device 10 is selected, it can use the individual chip enable signal CE-120269.doc -21 - 200818206. The controller 3 发布 issues an active low pulse on the write enable line WE1 and strobes the input/output lines 1/〇1 to 1/〇^ on the digital word provided by the controller 30 (corresponding to the figure The command cmd); the rising edge of the pulse written to the enable line WE causes the i/o control circuit to be received and latched in the command CMD, and finally to the command register 24 (Fig. 2). The controller 30 can cause the command latch enable signal CLEs to return to an inactive low state to terminate the command operation. Of course, as is known in the art, multi-word commands or multiple single-word commands can be sequentially transmitted in this manner. The command communicated in the manner shown in Figure 4a is used to indicate that the controller % will communicate the memory address to the command of the flash memory device 1 (for example, the command for reading operations; for serial data input) Command to program or write operation 10H). The foregoing embodiment of the invention is reduced in the normal state and the command # mode in which the controller 3 communicates the address of the address to the flash memory device. For its part, the operation shown in Figure 4b conveys a command 00H along the sequence shown in Figure 2, which indicates that the memory address is about to be transferred in the next sequence of signals. In this normal mode of operation, 'control (4) can convey a relatively wide range of commands to the flash memory device H). An exemplary set of commands in this preferred embodiment of the invention is set forth in the following table.

120269.doc -22- 200818206

60, D〇 (two loop command) Read start Word buy row address change —----—__ Auto block erase ID read

Status Read 70 Reset FF Referring now to Figure 4b, a preferred embodiment of the present invention will be described in which the memory address is transferred from the control memory to the flash memory device. In this operation, the controller 30 drives the command latch enable signal CLE to the inactive low state and the address latch enable signal ALE to the high state, which indicates to the flash memory device 10 that it will be on the input/output line 1 The address value (not the command value) is conveyed on /〇1 to 1/11. The wafer enable signal CE- is also driven to function as a low-level erroneous indication that the controller 30 is selecting the flash memory device j 〇 as the recipient of the address information. In this operation, the controller 3 〇 issues the active low pulse of the write enable signal WE, and each pulse indicates the bit provided by the controller 30 on the input/output lines 1/〇1 to ι/〇η. One of the address values. In this embodiment of the invention, the address information is synchronized to the rising edge of the write enable signal WE (ie, the end of the active low pulse), so that the flash memory ίο can use the edge to input / The current state of output lines 1/01 through 1/11 is latched in address register 22 (Fig. 2) as part of the desired memory address. As shown in the example of Figure 4b, the memory address extends across multiple words (the width of which is defined by the number of input/output lines 1/〇1 to Ι/On η120269.doc • 23· 200818206 'defined) here In the month of the month, the '5' memory address includes four address words ADD〇 to ADD3, which are provided in synchronization with the low pulse of WE_. Following the transmission of the address value (as shown in Figure 4b), the control (4) can perform the writing of the information to the flash memory device 10 or the reading of the data from the flash memory device. Figure 4c illustrates the signal conveyed by the preferred embodiment of the present invention in a normal mode of operation (i.e., &quot;old type, mode) for effecting a write operation. According to the architecture of Figure 2, this data write operation writes data to the data register 14. As far as it is concerned, 'in accordance with a preferred embodiment of the present invention, the method shown in Figure 4a is used; see the write command (e.g., command value 80H) to the data register' followed by the controller 3 The destination memory address ' communicated within the flash memory device 10' is preceded by the write operation now described with reference to FIG. In order to implement the data write operation, the controller 3 drives the command latch enable signal CLE and the address latch enable signal pair to the inactive low state 'which indicates to the flash memory device 1 () that it will be The input data to be written transmitted on the input/output lines 1/01 to I/On (ie, not the command, nor the address value). Of course, for this operation, the wafer enable signal CE is also driven to the active low state. Next, the controller 3 〇 issues a low pulse of the write enable signal WE - together with the data of each byte or word provided on the input/output lines ι/〇ι to Ι/On. In this particular embodiment of the invention, as in the case of command and address transmission, valid input data is provided at the end of each pulse in synchronization with the rising edge of the write enable signal WE. In response to this edge, the flash memory device 1 latches the current state of the input/output line 1/01 to Ι/On (corresponding to one word or byte of the input data) to the 1/0 control circuit 2 The data buffer is latched into the data register 14 indirectly via the bus DATA-BUS (or last possible) through the 120269.doc -24-200818206 bus. FIG. 4c illustrates four words 〇4〇) to Din(3) transmitted through the input/output lines 1/01 to 1/11 in a manner of four pulses synchronized with the write enable signal we— FIG. 4d In a normal mode of operation (ie, "old" mode), the controller 30 and the flash memory device 1 are performing a lean reading operation (from the flash memory device 10 to the controller) 30) Operation in the middle. As in the case of a data write operation, a sequence of commands (i.e., as shown in Figure 4a) and an address sequence (i.e., as shown in Figure 4b) have been previously performed prior to this read operation. One or more write operations may have been previously performed prior to this read (ie, if the same is true for the address just written, the read will be used as the verification of the previous write) ), or a write operation (eg, as shown in ® 4e) may be performed after this read operation, in the form of a read_modify_write sequence to the same memory address. In response to the address being communicated, the contents of the memory unit corresponding to the address are sensed and forwarded to the data register 14. For its part, the graphical read operation reads the current annotation of the data register 14. And in order to implement this read operation, the controller 3 hereinafter refers to the party described in FIG. 4a to issue an appropriate command (for example, a command leg) in the command operation. In this case, as in the data write operation, the control The device 30 has driven the command latch enable signal CLE and the address latch enable signal ale to both: middle, !, 'f and the chip has been driven to enable the signal-to-active low: Make the write enable signal WE- become inactive high-order "" unwanted read operation. In this data reading operation, the flash device 120269.doc -25- 200818206 memory device 1 〇 responds to the falling edge of the enable signal RE of the controller 30 W, and outputs the data word D_, therefore, in this normal state Operating mode

In the following manner, the controller 30 can synchronize the self-flash memory device service data by the following means: • issue the read enable signal RE_ in the middle of the low pulse, and receive the wait-segment (four) access time (permitted fast) The flash memory device 10 implements some or all of the operations involved in sensing the state of its memory cells) and forwards the sensed state to its data register 14 and out to the input/output line! /01 to 1/〇11. Controller 3 can then latch the data status of input/output lines 1/01 through I/On into its input buffer to receive data from flash memory device 10. In the example of FIG. 4d, four data words D 〇 ut (0) to D 〇 ut (3) are sequentially read; the rising edge of the wafer enable signal ce_ ends the reading operation, and then the flash memory device 丨〇 The output driver in the I/O control circuit 20 is caused to place the input/output terminal to I/On in a high impedance ("high-z&quot;" state. According to this normal mode of operation (ie, &quot;old mode" mode) Other operations are also preferably available, and such operations are known in the art. For example, in this normal mode of operation, the controller 30 can read the contents of the state register 24 by issuing the specified state command (eg, command code 70H) along the timing of FIG. 4a, and In response to the release of the low pulse generated by the read enable signal rE_, the contents of the read status register 24 are received through the input/output lines 1/01 to I/〇n. As shown in Figures 4c and 4d, a data word or byte (referred to as "data word" in this specification) is transmitted for each cycle of the write enable signal WE or the read enable signal RE. In the normal operation mode, the controller 3G controls the write enable signal WE and the read enable signal RE_ as shown in the figure and in the foregoing description 120269.doc -26-200818206. Specifically, | According to the conventional fast-recovery timing requirement and performance, in the read operation, since only one data word is read for each complete cycle of the read enable signal RE, the controller 3 has sufficient fa1 to self-publish its Reading the transfer (write enable signal WE) and receiving and latching the read data. However, this performance level is not necessarily sufficient for high speed use of the flash memory device 1 such as when using the flash memory card 25 as A large number of storage devices in the personal computer system. In addition, it is also expected that the old "operating mode" cannot keep up with the high-speed external interface mode from the controller 3 to the host system, such as according to the above mentioned ΑInterface Protocol. In accordance with a preferred embodiment of the present invention, therefore, flash memory device 10 provides an advanced higher performance read and write mode of operation, and controller 30, 'two constructs to utilize the advanced Mode. The operation of the flash memory device (7) and the controller 30 to utilize this advanced mode will now be described in detail with reference to the flowchart of Figure 5 and the timing diagram of Figure 6a to the heart. Figure 5a and Figure 6c show fast The flash memory device operates in the process of performing a data reading operation (i.e., in the flash memory card 25 from the flash memory device to the controller 30). The processing procedure in Fig. 5a is performed. In the power supply, the device 10 and the controller 3 are brought into the normal L operation mode (processing program 42), as described above with respect to the description of the figure "to W". In this normal mode of operation (ie, &quot;old type, mode), the read and write operations (if any) in this normal mode are implemented. 120269.doc -27- 200818206 , The advanced read mode of operation begins with process 46, which The controller 3 outputs the memory address value 1〇 according to the normal operation mode, as described above with respect to FIG. 4b. The memory address issued in the process: ^: 30 will be from this advanced operation mode. Where: the starting memory address of the data is taken, and preferably after transmitting the corresponding entry address input command, as described above. In the processing program 48, the controller 30 issues "starting data transfer". "OR" ID T" command sequence to flash memory device 10. This operation is further illustrated in detail in Figure 6 &amp; In accordance with a preferred embodiment of the present invention, controller 30 issues &quot;IDT "Command to the flash memory device 1" to start the advanced data transfer mode. This command is issued in a manner similar to that described above with respect to the blunt description, in which the controller 3 drives the wafer enable signal CE to the active low state, the drive address latch enable signal ALE to the inactive low state, and the drive. The command latch enables the signal CLE to the active high state. The rising edge of the low-pulse pulse applied to the enable signal WE is used as the IDT command value IDT CMD for driving the controller 3 to the input/output lines 1/01 to I/On (the binary word) Data strobes with values different from other assigned command values.纟k write enable signal WE—after a certain time after being in the high state&apos; The controller 30 makes the input/output lines 1/01 to 1/〇11 high impedance. And after the other elapsed time trre after the rising edge of the write enable signal WE, when the IDT command is strobed, the controller 3 释放 also releases its control of the read enable signal RE, permitting the flash memory. The control logic 18 of the device drives the state corresponding to line RE (there is no risk of data competition with controller 30). 120269.doc -28- 200818206 Once the IDT command has been latched in the flash memory device 1 and executed by the flash 1 memory device, then the flash memory device Η starts to execute the π» speed Mode a takes the beetle transfer handler %. As shown in the figure, after the non-zero access time after the rising edge of the write enable message, the 5 buy data transfer processing program starts from the flash memory device 10 to issue the first valid output data word D〇ut (0). Once the flash memory device is supplied with the first output data word IWO), it then starts to issue the active pulse at the read enable signal in synchronization with the additional output data word Dout(1) and the like. In a preferred embodiment of the present invention, a data word D°Ut (k) is issued in synchronization with each edge (falling edge and rising edge) of the read enable signal re driven by the flash memory device 10 itself. ° In the example of Figure ^, each output data word D〇ut(k) is connected to its strobe edge after the non-zero access time; the alternative is that the corresponding valid data word D_(k Within the release (or delayed release) of each read enable signal RE along the controller 3. In accordance with a preferred embodiment of the present invention, therefore, for the flash memory device via the input (four) line to the heart Provide information to control Device rate: The rate in this advanced mode is substantially faster than the rate in the normal mode of operation (Figure 4d) is approximately twice the data rate in a typical implementation. To some extent, this higher data is achieved. The rate is obtained by permitting the flash memory device H) to issue the read data strobe edge of the read enable signal RE_, which excludes the propagation delay involved if the controller 30 issues the read data strobe edge. And the inevitable timing window. However, those skilled in the art should understand that the output data is provided on the input/output lines 1/〇1 to 1/〇11 in the case of all other factors equal to 120269.doc -29-200818206. The rate of increase substantially increases the power consumption within the flash memory card 25, where the power consumption is primarily derived from the output drive within the 1/〇 control circuit 20 of the flash memory device. The power consumption is degraded as the data word width (i.e., the number n of input/output lines 1/01 to Ι/On) increases (this is a modern trend). According to a preferred embodiment of the present invention, Will now be described by reducing the input / The voltage swing of the output signal on the output lines 1/〇1 to 1/〇11 causes this power consumption to be greatly reduced. Conventional flash memory devices utilize the well-known 3 · 3 volt bus bar standard, which makes the minimum high bit The quasi-output voltage (ν〇Η) is 2.4 volts and the maximum low level output voltage (v0LHf, (K4 volts, and its nominal voltage swing is about 3.3 volts. As is known in the art, according to this standard, they The voltage is based on a nominal supply voltage of 3.3 volts and is specified between 27 volts and 3.60 volts. According to the conventional normal operating mode of modern flash memory devices, the output data The rate is 25 ΜΗζ (ie, every 4 nanoseconds of data transition), and in the worst case where a given input/output line Ι/Ok performs a data transition in each cycle, a flash memory device will be required. The capacitor of the input/output line 1/〇]^ is charged at a frequency of 125 MHz. Assuming a typical line capacitance of the input/output line i/〇k is 65 pF, the current consumption of an input/output line I/Ok (in milliamps) can be calculated from the following equation.

Ik=f*C(V〇H-V〇L) For this example, the result is:

Ik = 12.5 * 〇. 〇 65 (3.3) = 2.681 mA The above formula uses a typical W volt 120269.doc 200818206 swing between the high data level and the low data (four). The current consumed in driving the read enable signal RE will be twice that of the motor Ik because it must charge its corresponding conductor at each transition. Suppose there are 8 input/output lines 1/〇1 to 1/〇8, so the total current consumed in the conventional normal mode of operation of this example would be: ^total = 8(2.681)+2 (2.681 = 26.81 milliamps, in accordance with a preferred embodiment of the present invention, the busbar voltage is substantially reduced from the conventional 3.3 volt busbar level, for example, to a busbar voltage of about 18 volts, which defines a nominal voltage swing of H8 volts. In this case, the example of the minimum output still level voltage V〇hr limit may be about 144 volts (80% of the nominal power supply voltage), and the example of the maximum low output level voltage v〇lr may be about 0.36 volts. (2% of the nominal power supply voltage). In this reduced voltage operation, the voltage is based on a nominal supply voltage of 18 volts and is permitted from about 16 volts to about 2 volts. Assuming a best case (for data transfer; worst case for current consumption), the data rate is 50 MHz, and the input/output line 1/〇1 to 1/〇11 will be charged at 25 MHz. Therefore, the current Ik consumed by a single input/output line i/〇k can be calculated by the following equation: Ιπ25*0·065(1·8)=2·925 milliamperes. The above formula uses high data level and low data. A typical 18 volt swing between levels. Therefore, for the advanced mode of operation, this difference in current consumption per input/output line is small, but provides twice the data rate. However, the read enable signal RE is operated at the same frequency as the (four) mode of operation (but with one edge per clock (rather than just rising edges)). However, of course, its voltage swing is also reduced, because it also operates at 18 volts bus voltage 120269.doc -31 - 200818206; as such, its current consumption is the same as in the input/output lines. The current consumed by one. Again assume that there are eight wheel input/output lines 1/01 to 1/08, so the total current consumed in the advanced mode of operation of this example would be:

Itotal = 8(2·925)+1(2·925)=26·33 mA The transfer rate (about twice the data rate of large bursts)

It is slightly less than the total current consumed by conventional flash memory cards operating at a 3.3 volt bus voltage. Moreover, since the low current consumption is achieved by a lower voltage swing (1.8 volts versus 3.3 volts) for the input/output signal, the power consumed in this advanced mode of operation is substantially less than The power consumed in conventional flash memory cards. According to their examples, the power consumed in the conventional 8 1/0 flash memory in the normal mode of operation will be approximately megawatts (3.3 volts by 26.81 milliamps), however the invention described above Preferably, the power consumed by the example of the embodiment will be about 47 milliwatts (18 volts multiplication: (3) home amps). This substantially reduced power consumption is combined with the improved data for the use of the lower bus voltage, and

In other words, the flash memory device 10 operates in the master 'advance mode' and the normal mode of operation, and also includes a lower bus voltage for command and use. The power consumed in the transmission of the data is less than 120269.doc -32- 200818206 conventional flash memory device. As described in the w text, the mode number is operated in the normal state. In order to facilitate the implementation of the Iw command signal and the address information, it is preferable to use the flow-discharge and communicate the signals of the signals at the lower bus voltage (the heart additionally reduces the flash memory card 25). Power Consumption..) In view of Figure 5a, in accordance with this embodiment of the present invention, flashing, setting 1 够# is sufficient to respond to a request from the controller 3 (4) to suspend. It is contemplated that the controller 30 recognizes that the read data transfer must be suspended for any of a number of reasons (e.g., within it). For its part, decision 51 of Figure 5a determines whether this suspension is required. If no, then in the manner described above with respect to Figure 6a, the high speed read data transfer continues in the handler %. If the controller 30 needs to suspend the read data transfer (decision 51 determines &quot;yes&quot;), it issues a suspend request in the handler 52. In this exemplary implementation, the controller 30 during the read transfer operation This request is made by asserting the address latch enable signal on the enable signal ALE. This pause operation is performed during the read data transfer in the advanced mode (ie, it has been called up). In the example of the figure, during the data transfer from the flash memory device 10 to the controller 3, the controller 30 requests the data by confirming the address latch enable signal ALE. The transfer is paused. In response, the flash memory device 1 pauses the read enable signal RE (when at the low level (as shown) or at the high level) and delays the release after the read enable signal RE is paused. A data word. It is assumed that in this advanced mode, the enable signal RE is read and the input/output lines 1/01 to 1/〇11 are 120269.doc -33- 200818206. The rate is quickly switched, and the enable signal is expected to be latched at the address. ALE After driving to the active high state to request a pause, the flash memory device 1 can drive one or two additional data words and read the corresponding edge of the enable signal RE. In this example, the output data word D〇ut (4) During the period of time, the controller 3 confirms that the address latch enable signal ale, and during the output of the data word 〇. (6), the flash memory device 10 maintains the read enable signal and the input. The output line I/O 1 to I/On responds with a further transition. This pause further data transfer continues until the controller 3 executes the processing program 54 to cancel the start address latch enable signal ALE, thus ending the pause. 6b, the pause state is terminated immediately after the controller 3 causes the address latch enable signal ale to become the inactive low state. According to this embodiment of the invention, the address latch enable signal ALE The transition is used as the f-buy data from the output data word (in this example, the data word D〇ut(7)) from the (4) memory device 10. After the data word after the start of the pause, it is fast. Flash memory device 1 () borrowed Confirming the change of the read enable signal RE- and generating the read select communication number again, as shown in the figure. In this example, the read signal RE is below - the transition is used for the output after the end of the pause period. The strobe of the material Dout (8). Continue to read the data transfer in the advanced mode in the processing program %, as shown in Figure 请. Please re-enter the phase to continue the advanced H read t material transfer until

120269.doc' is in the processing of programs 58, 59 to terminate the transfer. Typically, the termination is terminated immediately after the end of the control device 10 for other reasons (e.g., after receiving • 34 - 200818206 to all required materials for operation) to terminate the transfer. In accordance with this example, in order to terminate this data transfer, the controller 30 first issues a pause in the processing private sequence 58, for example, by verifying that the address latch enables the high level of the enable signal ALE, as described above. The figure & illustrates the termination process. The sequence of the sequence 8 59 is shown as an example. The figure shows the transition of the gate address enable signal ALE during the advanced read data transfer operation period. The control H3G executes the processing material 59 during the pause operation to cause the pause operation of the processing program 58 to shift to terminate the advanced read data transfer. Alternatively, the processing program 59 can be implemented after the flash memory device 10 itself determines that its output data has reached the end of the page, in which case the 'flash memory device 1G itself maintains the read (four) signal re- at its end Level 'and in the input / output line &quot; (1) to! The current (i.e., last) output data word is maintained on the heart; in this case, the address latch enable signal ALE remains in the inactive low state. In the example shown in the &&amp;&apos;&apos; controller 30 terminates the high level on the command latch enable signal CLE when the address latch enable signal ALE is at the active high level, and terminates the greedy transfer. In response to this command latch enable signal CLE2 transition, the flash memory device 10 controls its output driver to delete the input/output line to Ι/On in a high impedance state and also release its pair corresponding to the read enable signal. In the two cases, the controller 30 obtains control of its lines when appropriate, while avoiding data competition problems. As shown in the example of FIG. 6c, since the suspend operation and the termination operation occur at the read enable signal RE, which is at a low level, the controller 3 obtains control of the read enable signal RE, and then drives the corresponding The non-active high level on the line leads to the transition as shown; if the pause operation is with 120269.doc -35- 200818206, the S stop operation occurs when the read enable signal RE is already at a high level, then of course There is no change on the line. Next, the flash memory device 1 returns to the normal operation mode (, old type &quot; mode), and the control is passed back to the processing program 44 in the flowchart of Fig. 5a. In accordance with this preferred embodiment of the present invention, the new advanced mode read data transfer will require another execution entity of the initiating process 48. Further, in the alternative, an unconditional termination will occur if the controller 3 revokes the verification of the wafer initiation signal CE_'. However, it is expected that this unconditional termination may result in &quot;error&quot; and other false and unspecified events occurring inside and outside of flash memory device 10 and controller 30. In accordance with this preferred embodiment of the present invention, an advanced high performance mode is also provided for data transfer from the controller to the flash memory device 10 (in other words, for write data transfer operations). The flow chart of Figure 5b, together with the timing diagrams of Figures h and 6d through 6e, illustrates this operation and will now be described. Wood ^ implements advanced mode write data transfer, flash memory device _ • The operation mode starts, and the processing program 60 is entered. This normal mode operation (if any) is first performed in the processing program 62 as is the case with the read data transfer. In the processing program 64, in this normal mode of operation, the controller -30 issues the address value to the flash memory device 1(), as described above with respect to the figure. In the processing program 66, the controller 3G Similar to the above: Figure (4) describes the advanced read f-transfer mode of the implementation of the advanced mode. It is contemplated that the write data transfer performed in this advanced mode in processing 66 is substantially identical to the read data transfer. For its part, for example, the command value issued in the processing program 66 is expected to be 120269.doc -36·200818206 IDT-CMD for reading caution, fetching and writing data transfer operations The same alternative is to assign different command values to each other for the two operations. In the processing program 68, the control 11 3G and the flash memory device 10 perform the P white write bee feed. Figure 6 constructs this operation (including the processing of the signal called b-sequence in the shell example) where the controller 3 〇 issues the command value mT-CMD, the command latch enable signal CLE, the high level and write

The combination of the medium and low pulses of the signal WE is applied to the flash memory device 10, thus the advanced mode data transfer is initiated. As in the previous example, the address latch enable signal AL_ is held at the (4) low level and the wafer enable signal CE is maintained at the low level. And because this operation will be a poor material write operation, the controller 3 causes the read enable signal re_ (not shown in the figure 6d) to remain in the non-discrete state. In this embodiment of the present invention, since the write data transfer processing program 68 is still under the full control of the controller 30, the delay between the issue command [靡 and the start of the write data transfer can be read. The delay before the first output data word (Fig. 6a) in the data transfer is much shorter. Preferably, the rising edge of the write enable signal corresponding to the start command IDT_CMD and the write enable signal WE corresponding to the first input data word Din(〇) The falling edge of the first pulse lasts for a specified time, as shown in the preferred embodiment of the present invention. Once the write data transfer begins, the rising edge and the falling edge of the enable signal WE are written. Both are used as write data strobes, which are confirmed by the controller 30. As shown in Fig. 6d, the standard 120269.doc -37-200818206 allows the controller 30 to issue a new valid write, in the same manner as the + input of the enable signal WE- Dice (in) to the input/output line I/O 1 to Ι/〇η. As a result, for the frequency of the write enable signal WE such as π # , the write data value, the main *, the du, and the (4) in the advanced mode can be the rate of the normal operation mode of the write operation. About twice.

According to the present invention, Ι_μ % θ A ^ , term /, embodiment, please refer back to Figure 5b, and the pause mode decision 69 is also implemented in the advanced mode write data transfer. Typically, only the controller 3 determines the need for a write pause, which expects the flash memory device to &quot; receive input data at this rate without buffering H overflow and so on. For example, --: to suspend # (decision 69 decides &quot;no&quot;), then continue to feed the bedding in the processing program. If the controller 30 requests a pause (decision 69 decides to be &quot;), a pause in the write transfer is implemented in the handler 7G. In this example, the controller 30 extends the write enable signal as needed - and simply Implementing a suspend processing private sequence 70. This pause can be implemented in either state (the write enable signal we remain high (four) or remain low); ® 6d is depicted as a pause during the duration of the write data word Din(2) Program 7(), in which the write enable signal WE is kept low_. Of course, the &amp; controller 30 does not issue an extra write data word ~(8) between the pause handlers 7. The controller only drives the write enable. Signal WE-transformation along with the next valid write data word

Din (3) (in the example shown in Figure 6d) implements the end of the pause period to continue the write data transfer (process 72). Moreover, as in the case of reading data transmission, the voltage level of the data signal and the control signal (input/output lines I/Oi to I/〇n, and the line for writing the enable signal WE1) are preferably lower than A known level of voltage level, for example, 120 269.doc -38- 200818206, with an 18 volt &quot;swing&quot; between a high logic level and a low logic level. As discussed in detail above, at a data rate of one-half, this lower voltage f bus will maintain the power consumed by this advanced write data transfer mode equal to or less than the normal operation in the normal mode of operation. Flash memory system • Power consumed in the system. Referring back to Figure 5bJ* in conjunction with Figure 6e, the termination of the write data transfer is accomplished in exactly the same manner as terminating the read data transfer. In the processing program 74, the (4) device 3() confirms the address latch enable signal ALE to the middle high (four) to suspend the transfer in the processing program 74 and then confirms the command latch enable signal CLE in the processing program 76 to the active state. The high level (while the address latch enable signal ALE remains high), which in turn terminates the write data transfer. The figure shows the timing of the various signals during the termination of the write data transfer. The write enable signal WE remains at a high level (as shown in Figure 6e) or transitions from a low level to a high level after the last data word Din(5) has been latched. After the termination of the advanced mode, the data is transmitted by the wire latching signal A l E and the life of the 7 latch enable signal CLE* to keep the high level up to the specified pulse width) and then enter the flash memory again. The normal operation mode of the body device 1() and the controller 3. - In this case, the temple considers that it needs to execute the command to call the advanced mode, and = it is considered that when the data transfer is terminated (4) the operation of the memory device ig returns to the U mode (ie, 'no need to execute the command), the normal state The operation mode is actually a "preset" operating mode. Alternatively, the flash memory device 10 can be configured so that a command needs to be executed to enter both the advanced data transfer mode and the normal operation mode, so that once the flash memory is restored The body device 10 is in the advanced 120269.doc -39-200818206 data transfer mode, a normal operation 丄;::;::: formula: 'until the controller - command. 妒 f, flashing body device 10 Execution of this use. (4) (4) and the additional consumption of the command sequence in essence, the r is in the θ generation, the flash memory device, the preset, the drop == material transmission! mode, resulting in At the first and second 10, the command is issued to the flash module 30 to apply the flash memory device to the flash memory device. In accordance with the present invention, the replacement of the specific secondary memory device 10 is in the normal mode of operation. Finishing The device 10 returns to the advanced data transfer mode. FIG. 7 shows the operation of the memory device according to the present invention, and the flash memory machine constructed by the soil case is constructed. The #, , /, medium and advanced lean material transfer mode is actually , pre-2 pull. In the processing program 80, power is supplied to the flash memory device ^ and = or otherwise reset, and the processing program enters the advanced operation mode (actually as a preset condition) without the need to send = 2 lines command. In the processing program 84, only the read operation and the write operation are performed in the advanced data transfer operation, as described above with reference to Fig. 4 (4). For example, 'in this advanced mode' is expected to perform a suspend operation and the like as described in the above description of (4) 6e; it is further expected that other operations (such as address, command and status communication operations) can still follow the normal operation mode practice. (if hope). In the processing program 86, the flash memory card 25 in accordance with the preferred embodiment of the present invention prepares a normal (or &quot;old type&quot;) mode mode: the address value is issued by the controller 120269.doc 200818206% To the flash memory device 1 (), the address value indicates the start memory address transmitted in the normal operation mode. In the processing program, the controller 30 issues a command sequence to start the normal mode of operation; it is expected that the command sequence substantially corresponds to the description above with respect to Figure 6a, and the command sequence - Green is operating according to the normal state Mode operation (expected command code value is a single bit 'read value'). In response to the command 88, the flash memory device performs the f 11 mode of operation reading or the person data transfer operation in the direction of the data transmission, @如' as described above, and the description of the ★. In the implementation of the present invention, the controller 3G issues both the read data strobe control signal and the write data strobe control signal, as described above. Moreover, in accordance with this alternative embodiment of the present invention, the normal mode of operation is exited upon completion of the data transfer. In the example of Figure 7, it is similar to that described above with respect to Figures 5a and 5b. In the handler %, the controller 30 issues a pause signal (eg, an active level on the address latch enable signal) to terminate the data transfer, and then in the processing routine (4), the control device, 30 terminates the transmission (eg, , by issuing a command to latch the enable signal level. According to the preferred embodiment of the present invention, after the termination of the normal operation mode data transmission, the control returns to the processing program, wherein the advanced data transfer operation mode is entered again, and in the processing program 8/ as needed The read and write data transfer operations are performed. Those skilled in the art having access to this specification will appreciate that in addition to the preferred embodiment of the present invention, it is contemplated that there are alternatives to the various modes of operation of the flash memory device 10. It is also to be understood that these and other alternative embodiments are within the scope of the invention as set forth in the application of the patent application No. 120269.doc-41.200818206. Referring now to Figures 8a through 8e, the signal between the flash memory device 10 and the controller 30 in the context of the flash memory card 25 in accordance with the second preferred embodiment of the present invention will now be described in detail. Timing. During the advanced mode in accordance with the second preferred embodiment of the present invention, the overall processing of the entry and exit operations preferably follows the processing described above with respect to the read operation of FIG. 5a and with respect to FIG. 5 &amp; Write the handler described in the operation. As such, the detailed description of the processing procedures will not be repeated herein in connection with the description of Figures 8a through 8e. As described above with respect to the first preferred embodiment of the present invention, the flash memory device 10 and the controller 30 are both in the normal mode of operation (or the old mode) after being powered. For its part, the user performs the read and write operations (if any) in this normal mode as needed. Then 'the memory address value is issued by the controller 30 in the normal mode of operation (which corresponds to the starting memory address from which the data is to be read in this advanced mode of operation) to the flash memory device. To perform the read operation

Enter the operation mode. As described above, this memory address is placed on the input/output lines 1/01 to Ι/On in conjunction with the active bit on the address latch enable signal ALE. After the memory address is transmitted, the controller 3 becomes the active low state by making the wafer enable signal CE-, the address latch enable signal ALE becomes the inactive low state, and the command latch enable signal CLe becomes the active high. "Sorrowful" and issue a "start data transfer" (or "IDT") command sequence to the flash C memory device, as described above. Figure 8a illustrates this operation. Write 120269.doc • 42- 200818206 The enable edge of the enable signal WE is used as the rising edge of the low pulse for use as the IDT command value for driving by the controller 30 to the input/output lines 1/〇1 to I/〇n. Data strobe for IDT-CMD (which is a binary word with a different value than other assigned command values). The controller 30 causes the input/output lines 1/〇1 to ^ to be added to the high impedance state after a certain time after the write enable signal WE_ is in the high state. In accordance with this second preferred embodiment of the present invention, the flash memory device 10 will take control of the read enable signal RE and drive the read enable signal RE. Accordingly, as shown in Fig. 8a, after strobing the rising edge of the signal 唬WE_, the controller 3 释放 then releases its control of the item enable signal RE. Next, the control logic 18 of the flash memory device j 驱动 drives the state of the corresponding line RE one without competing with the controller 30. Next, the flash memory device 1 starts the high-speed advanced mode read data transfer. According to the second preferred embodiment of the present invention, as shown in FIG. 8a, the flash memory device 1 is combined with the higher frequency read enable signal RE (higher than the frequency available in the old mode). Data from the address memory unit is provided at a higher data rate (higher than the data rate in the old mode). For example, in this advanced mode, the flash memory device 1 is coupled with the frequency of reading the enable signal RE twice at the frequency of reading the enable signal in the old type, and is provided in the old mode. The frequency of twice the frequency of the data is provided at the input/output lines 1/01 to Ι/On. For the example of the maximum available data rate and the read strobe frequency of 25 MHz in the old mode, the advanced mode data rate and the read enable signal RE can be as high as 120269.doc -43 - 200818206 up to 5〇 MHz. Since the flash memory device 1 itself is issuing the read enable signal RE and also issuing the data word, the frequency at which the flash memory device 1 generates the four signals is not under the direct control of the controller 3. Figure 8a illustrates this advanced mode capture operation. After the non-zero access time has elapsed after the rising edge of the write enable signal we_, the read data transfer process begins with the flash memory device 10 issuing the first valid output data word D〇ut(〇). A first output material word D is provided at the flash memory device 10. After 〇), it then starts issuing the active pulse RE-reading pulse in the same manner as the additional output data word DqJ) and the following. In accordance with this preferred embodiment of the present invention, a data word is issued in a manner that is synchronized to the read enable signal RE. In the example of the figure, the edge of the signal of the data edge synchronized with the falling edge of the enable signal RE is read; of course, the rising edge of the read enable signal RE (ie, the read enable signal "RE") can be used as a rising edge. Alternatively, as an operational edge, as shown in Figure 8a, each output data word D() ut(k) is connected to a falling edge of its corresponding read enable signal RE by a non-zero access time. , can be issued (or delayed release) within the corresponding valid data word Dcut (k) "Bei take enable signal RE one each falling edge to controller 3 〇. According to this second preferred embodiment of the present invention, therefore, for the flash memory device, the rate at which data is supplied to the controller 30 via the input/output lines 1/〇1 to I/〇n: here The rate in the order mode is substantially faster than the rate in the normal mode of operation (Fig. 4d), which is approximately twice the data rate in a typical implementation. To some extent, the way to achieve this higher data rate is to allow the flash memory device 1 to issue the read enable signal RE - read the data selection I20269.doc • 44 · 200818206 pass edge, which excludes The controller 30 issues the propagation delays and inevitable timing windows involved in reading the data strobe edge. Moreover, as described above with respect to a preferred embodiment of the present invention, the voltage swing is reduced by using the data signal (and the voltage swing is read by the read enable signal RE, if needed), The increased data rate at the input/output lines 1/〇1 to I/〇n is achieved without rushing to increase the power consumption of the flash memory device and controller 30. As noted above, the nominal busbar voltages of their lines are substantially reduced, for example, to a busbar voltage of about i.8 volts from the conventional 3&lt;3 volt busbar level. For an example of a 16-bit input/output bus interface (ie, 16 input/output lines 1/〇1 to 1/〇11) between the flash memory device 10 and the controller 3〇, The power consumption of the second preferred embodiment of the present invention is only slightly more than the power consumption involved in the first preferred embodiment of the present invention. As described above, in accordance with this preferred embodiment of the present invention, at a data rate of 50 MHz, the charging frequency for the input/output lines 1/〇1 to 1/(^ will be 25 MHz. Calculate the current consumed by a single input/output line Ι/Ok using the following formula: 1^~~25*0.065(1.8)=2.925 ιηΑ The above equation is typically between a high data level and a low data level. 18 volt swing. However, because the read enable signal RE is operating in the normal mode of operation and at twice the frequency of the frequency in the first preferred embodiment of the invention 'and its current consumption itself will be a single input / twice the current consumption of the output line:

Ire—50*0.065( 1 ·8)=2*2·925 mA = 5.850 mA 120269.doc -45- 200818206 According to this, for the case of 16 input/output lines I/Oi to 1/016, Therefore, the total current consumed in the advanced mode of operation for this example will be

Itotai-16 (2.925) + 5·850 = 52·65 Home Anesthesia It is slightly more than the current consumed according to the first preferred embodiment of the present invention (i.e., 49.73 milliamperes). Following the above, for a 16-bit j/〇 bus, the total current consumed by the conventional data transfer will be:

It 〇 tai = 16 (2.6 81) + 2 (2.6 81) = 48.62 mA It is slightly lower than the current consumed by the second preferred embodiment according to the present invention, which is 52.65 mA. However, even though the current consumed in accordance with this preferred embodiment of the present invention is slightly higher than conventional embodiments, this current level is oscillated at a lower voltage for the input/output signal (1.8 volts versus 3.3 volts). ) to be reached. As a result, the power consumed in this advanced mode of operation is substantially less than the power consumed in conventional flash memory cards. According to their examples, the power consumed in one of the normal operating modes of the conventional 16 I/O flash memory will be approximately 16 〇 milliwatts (3 3 volts = • 62 mA). The power consumed by the examples of the preferred embodiment of the invention will be about 95 milliwatts (1.8 volts by 52 65 milliamperes). This substantial reduction in power consumption is achieved by combining substantial improvements in the transmission rate (close to twice the data rate of the large burst). As described above, for example, if (from the flash memory device 10) is filled, the 5 memory device 1 is 〇. The operation of the quick release is illustrated in Figure 8b. The controller 30 is in the town, if the input buffer of the controller 30

120269.doc During the period of guaranty, the period was confirmed by the high level of confirmation. In response to this request, the flash memory device ι pauses the read enable message (when at the high level (as shown) or at the low level), and = late, the enable signal RE - the next cycle. Because of the high data rate transfer, one or two additional data words (and the read enable signal RE) should be already in the output of the flash memory device, pipeline, and The second correspondence, the data word, can be output before the flash memory device 10 reacts to the pause report. In this example, during the output data word DQut(4), the controller 30 has confirmed that the address latch enable signal ale, and during the output data word D〇ut(6), the flash memory device 1 borrows The response is made by the further loop of the read enable signal RE and the transition of the input/output lines 1/01 to I/On. Figure 8c illustrates the termination of the advanced mode rate reading data transfer in accordance with this preferred embodiment of the present invention. As described above, the controller 3 first issues a pause report by asserting the ancestor address latch enable signal ALE to a high level, thereby enabling final high speed data transfer. During the pause request, the controller 3 终止 when the address latch enable signal ALE is at the active high level, by confirming the command to latch the high level on the enable signal CLE, and terminating the data transfer operation as a response, flashing $ The memory device 1 causes its output driver to place the input/output lines 1/01 to I/On in a high impedance state and also release its control of the conductor corresponding to the read enable signal RE. Now, if suitable for the next operation, controller 30 can take control of their lines. The write operation in the advanced mode of this second preferred embodiment of the present invention will now be described with reference to Figs. 8d and 8e. As in the case of reading the data transfer, after the flash memory device 1 and the controller 3 have been operated in the normal state of the old mode &amp; The implementation of the advanced two-pass communication mode of the human-writer operation is similar to the implementation described above with respect to the description of the advanced mouth-to-mouth transfer. The command-lock enable signal CLE is shown in Figure 8d. The upper level of the upper level and the write enable; : ^ - the role of the low pulse and the release of the advanced mode command value IDT_CMD. As described above, the address latch enable signal ALE is maintained at the inactive low level, and The wafer enable signal CE is maintained at an active low level. The controller 30 maintains the read enable signal RE (Fig. 8d+, depicted) in an inactive high state during the entire data write operation to indicate that the data is written. The operation enters the advanced mode. Then, the rising edge of the pulse enabling signal we_ between the corresponding start command and the write corresponding to the first input data word Din(〇) is enabled. The signal 戦—the falling edge of the first pulse lasts for a specified time. According to the second preferred embodiment of the present invention, the write enable signal WE is written during the advanced mode write to the bead transport. One cycle frequency The _ is added to twice the frequency of the loop of the writer enable signal used when writing in the normal mode. In this example, the falling edge of the writer enable signal WE is used as the write data strobe. Moreover, in this advanced mode and in the W-plate type, the controller 3 确 combines the data values driven by the controller 3 on the input/output lines 1/01 to I/On to confirm the write enable signal WE. 8d, the controller 3 发布 issues a new valid write data word Din(k) to the input/output lines 1/01 to I/On in synchronization with each falling edge of the write enable signal. In this example, because the write enable signal is doubled, the write data transfer rate in this advanced mode can be approximately twice the data rate of the 120269.doc -48-200818206 mode of operation. For example, if the maximum write data transfer rate and the write enable signal frequency are μ mhz, the data transfer rate and write can be made in the advanced mode according to the second preferred embodiment of the present invention. The enable signal frequency is increased by up to 50 MHz. According to the invention This embodiment constructs the flash memory device 10 such that it can receive and process data at the higher rate. Of course, the controller 30 can use less than the maximum frequency depending on the system application and the rate at which the controller 30 itself processes the data. The actual write enable signal frequency and data rate frequency (e.g., 5 〇 MHz). Further, in accordance with this embodiment of the invention, the pause can be inserted into the advanced mode write data transfer. In this example, the controller 30 simply suspends the write data transfer by extending the write enable signal we as needed. As shown in Figure 8d, it can be in either state (the write enable signal remains high or remains). This pause is implemented in the low state). Of course, during this timeout period, the new material word Din(k) is not released. The controller 30 drives the write enable signal WE-lower cycle along with the next valid write data word Din(3) (in the example shown in Figure 8d) to end the pause period to continue the write data transfer. Moreover, as in the case of reading data transmission, the voltage level of the data signal and the control signal (input/output line 1/01 to Ι/On, and the line for writing the enable signal WE) are preferably lower than the Xi The known voltage level, for example, has a 1.8 volt &quot;swing, between the high logic level and the low logic level. As discussed in detail above, at a data rate of one-half, this lower voltage bus will cause the power dimension consumed by this advanced write data transfer mode to be equal to or less than 120269.doc -49 - 200818206 Often digging away from the power consumed by you in the operation of the system. For the sake of loss, please refer to the figure Se, enter n, and write the data transfer in the same way as the second material transfer according to the invention. The controller 30 drives the address lock (four) order reading capital movement The address latch enable signal ALE to the active high ο^ stop write transfer and terminate the advanced mode. During this period, the controller locks the latch enable signal CLE to the active high level (while the address = number is maintained at a high level) ) to terminate the transfer of the writer's data. The enable signal WE is guaranteed to be high, y, y, y, y, or after the last data word has been latched. After terminating the advanced mode write port transfer (by enabling the address latch enable signal ale and the command latch enable signal CLE knife to keep the clamp to the specified pulse width), the potato is reintroduced (4) Memory (4) Set_Controls the normal operation mode of H30. Therefore, in accordance with this second, more specific embodiment of the present invention, the data rate can be increased by permitting the use of the selected communication number of the local frequency to perform the high speed data transfer mode of operation instead of the party j. It is contemplated that this second operation in accordance with the present invention may be more compatible with the desired operation in some flash memory applications. Referring again to Figures 2, 1 and in accordance with a third preferred embodiment of the present invention, the continuation enable signal RE - and the write enable signal WE are both bidirectional. For the read operation in the normal operation mode, the external device (ie, the destination that is reading data from the flash memory array 12) is the source of the read data strobe, and the work is one to the flash memory device. Input to carry the read data strobe as a read enable RE-signal. In this normal operation, the write operation in the mode 120269.doc 200818206, the external device that is providing input data is issued to write the poor in synchronization with placing the input data on the input/output lines 1/〇1 to 1/〇11. The material strobe is used as a write enable WE signal. In a read operation in an advanced mode of operation in accordance with a preferred embodiment of the present invention, control logic 18 issues two read data strobes (phase shifts from each other) as described in the following detailed description. One of the read data strobes reads the enable RE signal, and the other writes the enable WE signal. The edges or transitions of each of the signals will be synchronized to the read data from the flash memory array 12 and via the lean register 14, the I/O control circuit 2, and the input/output terminal 1/〇1 to Ι/On conveys the information. Similarly, writing is performed in the advanced mode of operation by using both the read enable re_signal and the write enable WE-signal as write data strobes (published to the flash memory device 10 by the data source). operating. In the third preferred embodiment of the present invention, referring to FIG. 3, the line RE_ is carried for the old mode read operation (reading data from the flash memory device (7) and transmitting the data to the control The data strobe of the device 3) is itself connected to the terminal of the flash memory device i] 1 £ (Fig. 2). As described above, in accordance with this third preferred embodiment of the present invention, the control line RE is bidirectional, and the source of the read data strobe depends on the current mode of operation of the flash memory device. In the normal mode of operation, the controller 3g issues a read data strobe, which is maintained as valid data present on the signal lines 1/01 to Ι/On. In an advanced mode of operation in accordance with a preferred embodiment of the present invention, the flash memory device 1 sigma issues a read data strobe on the line RE for use in the data from the flash memory device 10 120269.doc - 51 - 200818206 Two: 30. And also as described in detail below, as follows: 'In the advanced pull write operation, the controller 3. Will also be strobed line -. Therefore, 'similar to the line', in the advanced data transfer mode according to the preferred embodiment of the present invention, the cloud control line RE is uniformly applied to the basket and the write operation It must be twisted—the discretion of the phase-shift communication number, which is used to read the word in both the read operation and the write operation. shell

As described in the detailed description below, the command transmitted by the controller 3 through the signal lines I/O 1 to Ι/Οη is synchronized with the source of the read data strobe on the signal line I, and the concern (4) the memory device It is difficult to transfer the data to the operation mode of the controller 30. Thus, in accordance with a preferred embodiment of the present invention, flash memory device 10 provides an advanced higher performance read and write mode of operation, and controller 30 is configured to utilize the advanced mode. The item according to the present invention will now be described in detail with reference to the flow chart of Fig. 4 (d) and the timing chart of Figs. 9a to 9e.

The third preferred embodiment flash memory device 1 and controller 3 utilize the operation of this advanced mode. 5a and 9a to 9c illustrate the flash memory device 1 in performing a data reading operation (i.e., in the flash memory card 25, from the flash memory device 1 to the controller 30). operating. In the processing routine 4 of Figure 5a, power is supplied to the flash memory device 1 and the controller 3 to bring the two devices into the normal mode of operation (process 42), as described above with respect to Figure 乜Said. In the processing program 44, the read operation and the write operation in this normal mode are performed in this normal operation mode (ie, the old type, the mode) (if there is 120269.doc • 52·200818206) . The entry into the white entry operation mode begins in process 46 where controller 30 issues the memory address value to the flash memory device 10 as described above with respect to Figure 4b. The memory address issued by the controller 30 in the processing program 46 is the starting memory address from which the data will be read in this advanced mode of operation, and preferably the corresponding read address is transmitted. After entering the command, as described above. In the processing program 48, the controller 30 issues a &quot;start data transfer&quot; or &quot;mT&quot; command sequence to the flash memory device 10. This operation is illustrated in further detail in Figure 9a. In accordance with a preferred embodiment of the present invention, in process 48, controller 30 issues an &quot;IDT read,&quot; command to flash memory device 1 to initiate an advanced lean mode. This command is issued in a manner similar to that described above with respect to the diagram, wherein the controller 30 drives the wafer enable signal CE- to the active low state, the drive address latch enable signal ALE to the inactive low state, and the drive. The command latch enables the signal 0:1^£ to the active high state. The rising edge of the low-pulse pulse applied to the enable signal WE is used as the IDT command value IDT_RD_CMD for driving to the input/output lines 1/〇1 to 1/〇11 by the controller 30 (its A data strobe that is a binary word with a different value than the other assigned command values. After a certain time after the write enable signal WE is in the high state, the controller 30 causes the input/output lines 1/〇1 to 1/〇11 to become a high impedance state. Moreover, after the other duration trel after the rising edge of the enable signal WE_ is written, when the strobe IDT read command is followed, the controller 30 also releases its control of the read enable signal RE_, permitting the flash memory. The control logic 18 of the body device 10 drives the state corresponding to the line RE_ (there is no risk of data competition with the controller 30 at 120269.doc -53-200818206). According to the present invention

Good concrete (4) After the advanced data transmission mode, the money transfer mode is used to establish the direction of the advanced mode data transmission (ie, writing or reading), and the use of the bedding material to convey the towel itself. Read enable signal rainbow - one or two with write enable signal WE, as described below. Alternatively, the advanced transfer mode, and the indication of the read or write operation to be performed in this mode, can be communicated from the controller 3 to the flash memory device 1 in other ways; for example a specific control signal transfer sequence (eg, control λ number on one or more lines of the control bus CTRL includes one or more of the signal lines connected to the ALE, CLE, wp- and ce-line' together with Read the enable signal RE_ and the writer enable signal WE". (4) Those who are familiar with this specification who have read this manual will understand the advanced steps for implementing the read operation and the write operation. These and other alternatives of the data transfer mode. Once the IDT read command has been latched in the flash memory device 1 and executed by the Shan-Zero Z 1:3⁄4 device 1G, then the flash memory device i 〇 Start executing the high-speed mode read data transfer processing program 5〇. As shown in the figure, after the non-zero access time after the rising edge of the write enable signal WE, the capture data transfer processing program starts in the flash memory. Device 1 〇 released A valid output data word D〇ut(0). Once the flash memory device 1 provides the first output data sub-D〇iit(〇), it is synchronized with the extra output data word Dout(l) and the following, etc. The alternate mode begins to issue a pulse in the action of both the read enable signal RE and the write enable signal WE. According to the preferred embodiment of the present invention, the read enable signal RE and the write enable 120269 are read. .doc -54- 200818206 The signals WE are out of phase with each other, with the same edge of each (for example, in this example, the falling edge, but of course the rising edge is used instead) to time a corresponding data word. 9a shows that in the advanced mode read operation, the write enable signal WE and the read enable signal RE are 180° out of phase with respect to each other. This complementary phase relationship is not specifically preferred according to the present invention. The necessity of the operation of the embodiment, because the strobe of the output data word will occur immediately after the next alternate falling edge (when it occurs); however, in order to maximize the data transfer rate with the fastest degree of designation, mutual The phase relationship is as desired. As shown in Fig. 9a, a data word is issued in synchronization with the read enable signal RE and the write enable signal WE driven by the flash memory device 1 itself. D(mt(k). In the example of Figure %, each output data word Dout(k) is connected to its corresponding gating edge and differs by a non-zero access time; alternatively, it can be corresponding The valid data word D_(k) is issued (or delayed) for each read enable signal re and the write enable signal WE to a falling edge to the controller 3. In accordance with a preferred embodiment of the present invention, therefore, The flash memory device 10 provides a data rate via input/output lines I/O 丨 to I/〇n: the rate in this sequence is substantially faster than the rate in the normal state (Fig. 4d), which is approximately in a typical implementation. Double the data rate. To some extent, the way to achieve this higher data rate is to allow the flash memory device 10 to issue the read enable signal RE_ and the write enable signal to read the data strobe edge 'its excluded if the controller 3 〇 Release the propagation delays and inevitable timing windows involved in the case of their read data strobe edges. In addition, the frequency of the falling gate edges of the two signals can be close to the single signal 120269.doc -55-200818206 Two pieces of the frequency of the falling gate edge can be used in this master operation. WE, this is because of the ancestor capture 1 &gt; First, the direction of the mouth of the mouth is set by the IDT read command value.

The master, however, should understand that the technology in the case of all other factors being equal 'in the input/transmission line plus the increase rate of the output provided is substantially larger than the flash memory card 2 5 Power consumption, in this read operation, 'power consumption is mainly derived from the output drive circuit in the 1/〇 control circuit 20 of the flash memory device 1G. As the data word width (i.e., the number η of input/output lines 1/01 to Ι/On) increases (this is a modern trend), this power consumption is deteriorated. In accordance with a preferred embodiment of the present invention, it will now be described that this power consumption is substantially reduced by reducing the voltage swing of the output signals on the input/output lines 1/01 to 1/11. The known flash memory device utilizes the well-known 3 · 3 volt bus bar standard, in which the minimum high level output voltage (V 〇 H) is 2·4 volts and the maximum low level output voltage (V0L) is 0·4 volts. And its nominal voltage swing is about 3.3 volts. As is known in the art, according to this standard, their voltages are based on a nominal supply voltage of 3.30 volts and are specified between 2 volts and 3.60 volts. In accordance with a preferred embodiment of the present invention, the busbar voltage is substantially reduced from the conventional 3.3 volt busbar level, e.g., to a busbar voltage of about 18 volts, which defines a nominal voltage swing of 1.8 volts. In this case, the example of the minimum output south level voltage V0H-R limit may be about ι 44 volts (80% of the nominal power supply voltage), and the maximum low output level voltage v 〇 L_Ri instance may be about 0.36 Volt (2% of the nominal power supply voltage). In this reduced voltage operation, the voltage is based on a nominal supply voltage of 180 volts and the permitted range is from about 1.60 volts to about 2.0 volts. . It can be easily calculated that even if the data rate is high, the current consumed in this advanced mode of operation will not be substantially higher (and possibly slightly lower) than the higher voltage swing; the current consumed in the normal mode of operation. The reason is that the voltage at which the parasitic capacitance must be charged at each output is lower than the voltage in the normal operating mode of the voltage swing. However, the lower voltage swing of the input/output signals causes the power consumption in this advanced mode of operation to be substantially lower than the power consumed in conventional flash memory cards. This substantially reduced power consumption is achieved in conjunction with a substantially improved data transfer rate (about twice the data rate of a large burst). Therefore, in accordance with a preferred embodiment of the present invention, the current consumed by the advanced read data transfer at a lower bus voltage (relative to a conventional flash memory device) in the advanced mode is not It is known that the flash memory device consumes more current in the normal mode of operation. Moreover, in a preferred embodiment of the iceberg according to the present invention, wherein the flash memory device 10 also has the ability to operate in a normal mode of operation, the lower mode is used in both the advanced mode and the normal mode of operation. The voltage is discharged, and the lower bus voltage is also used for other operations including the command disk, (iv) value transmission. As far as it is concerned, the flash memory device 1G consumes less power in transmitting data than conventional flash memory devices. As described above, the command signal and the address signal are transmitted in the normal operation mode. For ease of implementation, it is preferred that the bus voltage for communicating their signals is also maintained at a lower bus voltage (eg, 18 volts), which provides 120269.doc • 57· 200818206 additional reduction of flash memory The power consumption of the card 25. Please refer back to FIG. 5a again, according to the present invention.

^ /, the body knows * the example of his BA memory device 10 can respond to the suspension request from the controller 30, the invention, the controller 3G is expected to be based on a number of reasons (for example, within: receiving data buffer The device is full and it is considered that the data transfer must be suspended. For its part, decision 51 of Figure 5a determines if this pause is required. If no, then in the manner described above with respect to Figure 9a, the high speed read data transfer continues in the handler %. If the controller 30 needs to suspend the read data transfer (decision 51 determines &quot;yes&quot;), it issues a pause request in the handler 52. In this exemplary &amp; implementation, the controller 30 makes this request during the read transfer operation by verifying that the address latch enables the mid-high level on the enable signal ALE. Figure % shows this pause operation, which occurs during the read data transfer in advanced mode (ie, advanced mode has been called and data transfer has started). In the example of Fig. 9b, during data transfer from the flash memory device 10 to the controller 3, the controller 30 requests the data transfer pause by confirming the address latch enable signal ale. In response, the flash memory device 1 suspends the read enable signal RE and the write enable signal WE—(when at a low level or at a high level, as shown), and thus suspends the read enable signal RE_ Delay the release of the next data word after writing the enable signal WE. Assuming that the fast switching rate of the enable signal RE_, the write enable signal WE_, and the input/output lines 1/01 to I/On is read in this advanced mode, it is expected that the address latch enable signal ALE is driven to function. After the medium high state is requested to be paused, the flash memory device 10 can drive one or two additional data words and the corresponding edge of the read enable signal RE_ and the write 120269.doc -58-200818206 into the start signal WE. In this example, during output of the data word D〇ut(4), the controller 30 has confirmed the address latch enable signal ALE, and during the output of the material word Dout(6), the flash memory device 1 A further transition of the read enable signal RE—, the write enable signal WE-, and the input/output lines 1/01 to I/On is maintained in response. This pause further data transfer continues until the controller 3 executes the processing routine 54 to revoke the start address latch enable signal ale, thus ending the pause. As shown in Figure 9b, the pause state is terminated immediately after the controller 30 causes the address latch enable signal ale to become inactive low. According to this embodiment of the invention, the transition of the address latch enable signal ALE is used as an output data word from the underlying flash memory device 10 (in this example, the data word 〇_(7)) Read data strobe. After the start of the data word after the pause, the flash memory device 1 generates the read selection communication number again by confirming the change of the read enable signal RE and the write enable signal WE, as shown in the figure. The write enable signal WE is used to switch the second output data word D〇ut(8) after the end of the pause period, and the read enable signal RE is used. The strobe of the third output material word Dout(9) after the pause period. Advanced mode read data transfer continues in process 56, as shown in Figure 9b. Referring again to Figure 5a, the advanced mode read data transfer continues until the controller 30 wants to terminate the transfer, which in the processing programs 58, 59 indicates to the flash memory device 10 that it wants to terminate the transfer. Typically, the transfer is terminated immediately after the controller 30 determines that it is reaching the end of the flash memory device 1'. However, the controller 30 may also be used for other reasons (eg, receiving 120269.doc -59-200818206) The transfer is terminated after all the required information of the operation. = According to this example '4', the data transfer is terminated, and the controller pays a pause in the processing program 58 first, for example, when the ALE is high, the address is latched and enabled. Figure 9c illustrates an example of terminating the process, which is (4) latching the enable signal-like transition during the advanced read transfer operations. The controller 3G shifts the pause operation of the processing program 58 to the termination advanced item fetch data transfer during the pause operation period, the second processing, and the sequence 59'. Alternatively, the processing procedure (4) may be performed after the flash memory device 10 itself determines that its output data has reached the end of the page. In this case, the flash memory (4) (4) itself causes the read enable signal re- and the write enable signal WE. _maintained at its last level and maintains the current (ie, last) output data word on input/output lines 1/〇1 to I/On; in this case, the address latch enable signal ALE is still maintained Non-active low state. In the example shown in Figure 9c, the controller 3 terminates the data transfer when the address latch enable signal ALE is asserted at the active high level to assert the high level on the command latch enable signal cLE. In response to this command latching the enable of the signal CLE, the flash memory device controls its output driver to place the input/output lines 1/01 to I/On in a high impedance state, and also releases its pair corresponding to Reading the control of the enable signal RE - and the conductor of the write enable signal WE_, in both cases, allows the controller 3 to obtain control of their lines when appropriate, while avoiding data contention issues. As shown in the example of FIG. 9c, since the suspend operation and the termination operation occur at the read enable signal RE- and the write enable signal WE__ are at a low level, once the controller 30 obtains the read enable signal 11£__ and Write enable signal WE_ control 120269.doc -60- 200818206 system, then drive the corresponding non-active high level on the line = no change; if the pause operation and the termination operation occur in any of their signals Of course, the two or the two are already at a high level. Then, the flash memory device 10 returns to the normal operation mode (&quot;old type&quot; mode), and the control is returned to the processing program in the flowchart of Fig. 5a. According to this preferred embodiment of Shuming, the new advanced mode read data transfer will require another execution individual of the start handler 48. • Go-step' in an alternative practice' if controller 3. If the verification chip enable signal % is revoked, an unconditional termination will occur. However, it is expected that termination of this benefit condition will result in &quot;error&quot; and other false and unspecified events occurring inside and outside of the flash memory device 1 and controller (9). In accordance with this preferred embodiment of the present invention, an advanced high performance mode is also provided for data transfer from the controller (10) to the flash memory device 10 (in other words, for write data transfer operations). The flow chart of Figure 连同 together with the diagram of the diagram of the % Lushaw 9d to 9e (4), this operation is now described. In order to realize the advanced mode writer data transmission, the flash memory device _ normal operation mode starts, and enters the processing program 6〇. As with the read data transfer - H, this normal mode operation is first performed in the processing program 62 (if there is (4)). In the processing program 64, the controller 3 〇 issues the address value to the flash memory device 1 in this normal mode of operation, as described above with respect to the servant description. And in the processing program 66, the controller 66 initiates the advanced mode in a manner similar to the advanced read data transfer described above with respect to Figure 9 &amp; It is expected that in the processing program 66, the write data transfer of the line 120269.doc -61 - 200818206 in this advanced mode is exactly the same as the read f transfer, except that a different command value IDT_WR_CMD is used, the command value The advanced mode data transfer operation is indicated (controller 30 to flash memory device 1) instead of reading. This different value permits the use of both the write enable signal WE and the read enable signal RE in the write transfer, as described below. In the processing program 68, the controller 30 and the flash memory device 1 perform advanced write data transfer. Figure 9d shows the signal timing in the example of this operation (including the processing program 66), wherein the controller 3 〇 issues the command value IDT - WR - CMD, the command latch enable signal CLE, the high level and the write enable The combination of the signal WE and the low pulse is applied to the flash memory device 1〇, so the advanced mode data transmission is started. As in the previous example, the address latch enable signal ALE is maintained at the inactive low level and the wafer enable signal CE is maintained at the active low level. And because this operation will be a data write operation, the controller 3 causes the read enable signal re_ (not shown in Fig. 9d) to remain in the inactive high state at all times. In this embodiment of the invention, since the write data transfer handler 68 is still under full control of the controller 30, there is a delay between issuing the command IDT_WR_CMD and starting the write data transfer. The delay before reading the first output data word (Fig. 9a) in the batting transmission is much shorter. Preferably, the rising edge of the pulse corresponding to the write enable signal WE corresponding to the start command IDT-WR-CMD and the write enable signal WE corresponding to the first input data sub-Din(〇) are (Or reading between the falling edges of the first pulse of the enable signal scale for a specified time, as shown. In this preferred embodiment of the invention, once the data transfer 120269.doc-62 is written - Beginning with 200818206, the falling edge of the write enable signal WE and the read enable signal RE is used as the write data strobe, which is confirmed by the controller 30. Of course, the rising edges of their signals can be used instead. As with the October issue of reading data transmission, the write enable signal WE and the read enable signal RE are provided by mutually different phase relationships (in order to maximize the data transfer speed; rate, preferably 180. phase relationship). To increase the data transfer rate in this write operation. As shown in Figure #, this allows the controller 3 to synchronize with each of the falling edge of the write enable signal and the read signal RE. Way to post a new valid write The poor word Din(k) is input to the input/output line 1/〇1 to 1/〇11. As a result, the frequency of the write enable signal WE and the read enable signal RE is the same as the normal (old type) operation mode. The frequency of the write data in this advanced mode may be about twice the data rate of the normal operation mode write operation. According to this embodiment of the present invention, please refer back to the figure, advanced mode. A pause decision 69 can also be implemented in the write data transfer. Typically, only the controller 30 determines the need for a write pause, which expects the flash memory device to receive input data at this data rate without buffering. Overflow, etc. If no pause is required (decision 69 decides no), then data transfer continues in process 72. If controller 30 requests a pause (decision 69 decides • "is"), then processing The suspension of the write data transfer is implemented in the program 70. In this example, the controller 30 simply extends the write enable signal WE as needed to read the enable signal RE, and simply implements the pause processing routine. (This write is performed in the write enable signal WE and the read enable signal RE remains high or low), and FIG. 9d illustrates the pause processing routine 70 during the duration of the write data word 2). Wherein the write age # τ 乂咼 eight enable signal WE_保120269.doc • 63· 200818206 hold the low state and keep the read enable signal RE_ high. Of course, during the pause handler 7G, the controller 3G does not The additional write data word Dln(k) is issued. The controller 3() only drives the write enable signal or the read enable edge of the S number E_ along with the next valid write data word Din(3) (in Figure d The only example shown is the end of the pause period to continue the write data transfer (process 72).

And as if the tributary is being transmitted, the voltage level of the data signal and the control signal (input/output line to, and the line for writing the enable signal WE_ and the read enable signal RE_) are better. A voltage level lower than a conventional level, for example, having a U volt "swing" between a high logic level and a low logic level. As discussed in detail above, in one-half of the data At the rate, this lower voltage bus will cause the power consumed by this advanced write data transfer mode to be equal to or less than the power consumed in the conventional flash memory system operating in the normal mode of operation. Figure 5b, in conjunction with _, terminates the write data transfer in exactly the same way as terminating the read data transfer. In the handler %, the control, 30 in the handler 确 confirms that the address latch enable signal appears to the middle bit The transfer is suspended, and then the command latch enable signal CLE is asserted in the handler % to the active high level (while the address latch enable signal remains high), which then terminates the write data transfer. Figure (4) will = stop! Enter the timing of various signals during the data transmission. Write enable (4) take the enable signal RE_ remain at the high level (as shown in Figure %), = the last data word Din (5) is latched ( In this example) drive to Micro Motion. Following the termination of the advanced mode write data transfer (by making the address latch open 120269.doc -64 * 200818206 with 5 ALE and command lock in the Kaitian Zhuoda After the device p 7 钡孖 enable signal CLE respectively maintains the high fixed pulse width and then the real jg_ 现, then enters the normal operation mode of the flash memory 10 and the controller 30 again. In the 匕 example, it is considered that the command needs to be executed to call in. The mode, and considering that the operation of the flash memory device U) returns to the core mode when the data transfer is terminated (ie, 'no need to execute the command'), the normal operation mode is actually the "preset" operating mode. The practice is that configurable flash memory ^

Set 10' so that f wants to execute the command to enter both the advanced data transfer mode and the normal operation mode, so that the flash memory device 1G is in the advanced data transfer mode, then it is still in the mode, Until the controller 30 issues a command to return to the operating mode and the flash memory device i executes the command. Of course, this approach involves the extra cost of the command sequence. Further, in an alternative, the &quot;preset, operation mode of the flash memory device 10 can be an advanced data transfer mode, so that all data transfer is implemented in the advanced mode until the controller 30 issues a command to make it faster. The flash memory cluster 10 enters the sad operation mode. In this case, it is contemplated that the controller 3 can indicate whether to read or write an advanced mode operation to permit both the read enable signal and the write enable signal to be gated, as described above. In accordance with this alternative embodiment of the present invention, once the flash memory device 10 is in the #怨操作 mode, completing the data transfer will cause the flash memory device 10 to return to the advanced data transfer mode. Those skilled in the art who have referred to this specification should understand that it is expected that there will be alternatives to the various modes of operation for entering and exiting the flash memory device 10, and that the method of 120269.doc-65-200818206 should be understood and that they should Such other alternative embodiments are within the scope of the invention as set forth in the claims. Thus, flash memory device 10, controller 30 and flash memory card 25 in accordance with a preferred embodiment of the present invention provide significant advantages over conventional devices and systems. The present invention achieves a high data transfer rate (close to twice the size of conventional devices and systems) while still providing command and signal compatibility with legacy, non-advanced devices. In addition, in the advanced data transfer mode

The lower bus voltage signals involved maintain the overall device and system current and power consumption close to (or even below) the current and power consumption of conventional flash memory devices and systems. As a result, the present invention can be used in digital system applications where the transfer rate of f material is particularly critical. As mentioned above, this application is based on a high-performance digital still camera. In this type of camera, the image resolution (and therefore the data per image capture) is now over 10 megapixels, and now there are commercially available cameras above 12.4 megapixels. However, because the data transfer rate from the image sensor to the fast memory is a direct factor of the rate at which images can be taken (the shutter user is usually perceived by the camera, the shutter lag is lag), this data transfer rate is critical. . Moreover, the camera user's primary (4) absolute delay (i.e., irrespective of the amount of data acquired in each image) increases the load on the data transfer rate as the resolution of the image increases. Another potential application for this high data transfer rate is the use of solid state flash memory as a mass storage medium in a computer system that substantially replaces some or all of the disk drive's mass storage. It is expected that the use of solid-state memory (without the use of a magnetic disk drive) will enable further miniaturization of the computer system and the adoption of the band, and also greatly increase the modern portable and handheld systems. Features. Although the present invention has been described in terms of the preferred embodiments of the present invention, it will be understood that modifications and alternatives to the specific embodiments thereof Advantages and benefits of the present invention. It is intended that such modifications and alternatives are within the scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows an electrical block diagram on a conventional memory. 2 is an electrical block diagram of a memory module constructed in accordance with a preferred embodiment of the present invention. 3 is a block diagram showing the operation of the memory module of FIG. 2 in conjunction with a single-chip memory controller as a system or subsystem in accordance with a preferred embodiment of the present invention. 4a-4d are timing diagrams showing the operation of the flash memory module of FIGS. 2 and 3 in a normal mode of operation and in a communication command in accordance with a preferred embodiment of the present invention. 5a and 5b are respectively a flow chart showing an operation of reading data transfer rate and writing data transfer in an advanced mode according to a preferred embodiment of the present invention. Figures 6a through 6e are timing diagrams of signals involved in the operation of the first preferred embodiment of the present invention and the operation of Figure 5b. Figure 7 is a flow chart showing the operation of the advanced mode data transfer in accordance with the second preferred embodiment of the present invention. 8a-8e are diagrams showing a second preferred embodiment of the present invention. A timing diagram of the signals involved in the operation of Figure 5b. 120269.doc -67- 200818206 5a Figures 9a through 9e are timing diagrams of signals involved in the operation of the third preferred embodiment of the present invention and the operation of Figure 5b. [Main component symbol description]

2 Flash Memory Card 4 Flash Memory Device (Module) 6 Memory Controller 10 Flash Memory Device (Module) 11 Column Decoder 12 Flash Memory Array 13 Sense Amplifier 14 Data Scratchpad 15 row decoder 18 control logic 20 input/output control circuit 22 address register 23 status register 24 command register (status register) 25 flash memory card 30 controller ADD0 to ADD3 address word ALE Address Latch Enable (Signal) CE_ Chip Enable (Signal) CLE Command Latch Enable (Signal) CMD Command 120269.doc -68 - 200818206

CTRL Control Bus DATA_BUS Bus Din Data Word D〇Ut Data Word HOST_IF Host Interface (External Interface) Ik Current consumed by a single input/output line Ire Read current consumed by enable signal RE_11 〇ta 1 Total consumed Current I/Ol to I/On Common input/output (signal line) IDT Start data transfer IDT-CMD, IDT command value IDT_RD_CMD, IDT_WR_CMD RE_ Read enable (terminal, control line, signal) vcc_R Power supply voltage V〇h Minimum high (logic) level output voltage V OH-R minimum output high level voltage V〇L maximum low (logic) level output voltage V 〇lr maximum low output level voltage WE_ write enable (terminal, control line, signal WP_ write protection line data_I/0 bus Ctrl bus trel duration 120269.doc -69-

Claims (1)

200818206 X. Patent application scope: ▲ Operation &amp; flash memory device to communicate with a flash memory controller's method includes the following steps: Broken in the "normal operation mode, in response to receiving from the controller – ❹ data selection communication number - the first polarity transition, providing the information word to the controller on the input/round line; performing a command from the controller to initiate an advanced transfer mode; Driving the read data selection communication number to the controller; and synchronizing with the transition of the first and second polarity of one of the read data selection communication numbers and corresponding to the advanced data transfer mode The data stored in the flash memory device provides a data word to the controller on the input/output line. The method of claim 1 wherein the normal mode of operation corresponds to a standardized specification for (4) communication between the flash device and the controller, and the standardized specification includes a H-voltage specification, the first-voltage specification is defined for The read data selects a communication number and a high and a low logic level of the data words on the input/output lines; and wherein the providing step, the driving step, and the providing step use a second specified voltage specification Executing, the second specified voltage specification is defined for the read data selection communication number and the high and low logic levels of the data words on the input/output lines, the south of the second specified voltage specifications A voltage swing defined with a low logic level is substantially less than a voltage swing defined by the high and low logic levels in the first specified voltage specification = 120269.doc 200818206. The method of [j2] wherein the voltage swing defined by the first specified voltage specification and the low logic level is nominally about 3 3 volts, by means of the mth voltage specification The voltage swing defined by the material high and low logic is nominally about 1.8 volts. 4. The method of claim ’ further includes: After performing the step, receiving a write data selection from the controller; responding to receiving the transition of the first and second poles of one of the write data selection signals, latching in the input/output a data word on the line for storage in the flash memory device; and in a normal mode of operation 'responding to receiving a change in the first polarity of one of the second and second selection communication numbers from the controller, the lock There are bedding words on the input 1 line for storage in the flash memory. The method of claim 1, wherein the executing the step is in response to receiving a start command value on the j input/output line, which is combined with one of the data from the work order. One of a polarity transitions, the combination of receiving a command latch enable signal from the controller; and further comprising: providing a data word to the controller during the second data transfer mode, and responding to the receiving Suspending the request from one of the controllers, maintaining one of the data words on one of the input/output lines, and 120269.doc 200818206 maintaining the current state of one of the read enable signals; and responding to receipt from the control One of the pause requests of the device ends 're-continues the step of providing the data word to the controller in the advanced data transfer mode towel and the step of driving the read data selection communication number. 6. The method of claim 5, wherein the pause request corresponds to receiving a transition from one of the control signals of the controller; and further comprising: providing the data word to the controller in the advanced data transfer mode towel The step and the step of driving the read data selection communication number are combined with one of the first polarity from one of the controllers to write the data selection communication number and combined with receiving the address lock from the controller Storing an enable signal, receiving a memory address from the controller on the input/output line; wherein the pause request corresponds to the address during the step of providing the material to the controller in the advanced data transfer mode One of the latch enable signals transitions; and wherein the end of the pause request corresponds to a second transition of the one of the address latch enable signals. 7. A method of operating a flash memory device to communicate with a flash memory controller, the method comprising the steps of: in an advanced data transfer mode of operation: the read data selection communication number Go to the controller and synchronize with the transition of the first and second polarity of one of the read data selection communication numbers; and 120269.doc 200818206 corresponds to the data stored in the flash memory device, at the input Providing a data word to the controller on the output line; executing a command from the controller to initiate a normal mode of operation; and then responding to receiving a read data from the controller The change in polarity provides a data word to the controller on the input/output line. The method of claim 7, wherein the normal mode of operation corresponds to a normalization specification for communication between a plurality of flash memory devices and a plurality of controllers, the standardized specifications including a first voltage a specification, the first voltage specification defining a high and low logic level for the read data selection communication number and the data words on the input/output lines; J and wherein the driving step and the providing step are used a second specified voltage specification is defined, the second specified voltage specification defining the read selection communication number and the high and low logic: levels of the data words on the input/output lines, the second specified voltage specification The voltage swing of the contour and the low logic level is substantially smaller than the voltage swing defined by the 压 压 〜 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 。 。 。 。 。. The method of 々月士项8, wherein the voltage swing defined by the A and the low logic levels in the first specified voltage specification is nominally about 3 3 volts, _ and wherein the second is hunted by the second The voltage swing defined by the contour and level in the specified voltage specification is nominally about 1.8 volts. A10. The method of claim 7, further comprising: 120269.doc 200818206 in the advanced data transfer mode, receiving a write data selection communication number from the controller; 'responsive to receiving the write data selection communication One of the first one, the second, the second, and the second, the data word latched on the input/output is line is stored in the flash memory device; and 'I the normal state In the operation mode, in response to receiving a transition from the controller to the first data polarity of the write data selection number, latching the corrupted words on the output output lines for storage in the flash memory device in. ▲ a method of operating a flash memory device to communicate with a flash memory controller, comprising the steps of: in a normal mode of operation, in response to receiving a read from the controller (four) selected communication number - a transition of the selected polarity, providing a material to the controller on the input/output line, in which the read data selection communication number has a maximum available frequency; # &amp; line - receiving from the (four) H The command is to start-advance data transfer mode; then drive the read data to select the communication number to the controller; and synchronize with the selected polarity of the selected data to select the polarity change and enter the P white In the shell material transfer right, the data word is provided on the input/output line to the controller corresponding to the data stored in the flash memory device; wherein the read data is selected in the advanced data transfer mode The frequency of the communication number is higher than the maximum available frequency of the read data selection communication number in the normal operation mode. 120269.doc 200818206 12. The method of the second item 11 wherein the normal mode of operation corresponds to a standardized specification for mediating communication between the flash memory device and the controller, = standardized specifications including 1-voltage specifications The first voltage test is used for the read data selection communication number and the high and low logic levels of the special beet word on the input/output lines; j and wherein the providing step, the driving step and the Providing a step-by-step; the second finger, the voltage specification is implemented, and the second specified voltage specification is used for the read data selection communication number and the high and low logic levels of the inputs at the input, the first The voltage swing of the equal-back and low logic levels is substantially less than the voltage swing defined by the high and low logic levels in the first &amp; fixed voltage specification. 13. The method of claim 12, wherein the voltage swing defined by the first and the low logic levels in the first-specified voltage specification is nominally about 3 3 volts; wherein the second specified voltage is The voltage swing defined by the contour and the low logic level in the specification is nominally about 1.8 volts. 14. The method of claim U, further comprising: receiving, after the performing step, a write data selection communication number from the controller; responding to receiving a change in polarity selected by one of the write data selection communication numbers A data word latched on the input/output lines for storage in the flash CMOS device; and in the normal mode of operation, in response to receiving the 120269.doc 200818206 write data from the controller Selecting one of the communication numbers, the first &lt;11&gt;, and the data words latched on the wheeled/output lines are stored in the flash memory device, wherein in the normal mode of operation, the maximum available frequency The μ human shell material selection communication number has and the frequency of the writing of the poor material selection communication number is in the advanced data transmission mode, and the writing data is in the normal operation mode. Select the maximum available frequency for the communication number. The step of executing the execution is in response to receiving a start command value on the input/output lines, which is combined with one of the first polarities of one of the write data selection communication numbers from the controller, and is combined with the reception. a command latch enable message from the controller and further comprising: during the step of providing the data word to the controller in the advanced data transfer mode, and shouting (4) from one of the control pause requests 'keep One of the data words on the input/output lines, and maintaining one of the current status of the read enable signal; and in response to receiving the end of the pause request from the controller, resuming the advanced data The step of providing the data word to the control mode in the transfer mode to the control ι§ and the step of driving the read enemy and the selection of the becket selection communication number. 16. The method of claim 15, wherein the suspend request corresponds to receiving a transition from one of the control signals of the controller; and further comprising: providing a data word to the controller in the advanced data transfer mode 120269 .doc 200818206 In violation of the step and the step of driving the read data selection communication number, combined with one of the first polarities from one of the controllers to write the data selection communication number, and combined with receiving from the controller a bit latch enable message #ϋ 'receives a memory address from the controller on the input/output lines; wherein the pause request corresponds to being provided in the advanced data transfer mode, the bucket to the controller The one bit of the address latch enable signal transition during the step; And wherein the method of ending the pause request to the second conversion operation &amp; Ρα] δ 忆 体 device to communicate with the fast pj memory controller comprises the following steps: in an advanced data transfer operation In the mode: ^ drive to read the data selection communication number to the controller, and synchronize with the selected polarity of the selected one of the selected communication numbers; and the data corresponding to the flash memory device Providing a data word to the controller on the input/output line; performing a command to receive the command from the controller in a mode; and 1%^ then responding to receiving a readout from the controller The selected polarity is changed, and the secondary JU controller is provided on the input/output line; ^, scalar, and to the maximum available frequency in the normal operation mode; the read data selection communication number has 120269.doc 200818206 The read data selects the read data selection communication and wherein the frequency of the advanced data transmission mode number is higher than the maximum available frequency in the normal operation mode18. The method of claim 17, wherein the normal mode of operation is a beam of communication between the flash memory device and the controller: the standard specification for including the first voltage specification, the first The value of the data is selected and the high and low logic levels in the input/round line == data; And wherein the driving step and the providing step are performed using a one-to-one electrical specification, the second voltage regulation defining a material selection communication number and the information words on the input/output lines High and low logic levels 'the second specified voltage specification of the high disk low logic level defines a voltage swing 'which is substantially smaller than the first _ finger: electricity 19. The high and low logic in the voltage specification The voltage swing defined by the level. The method of claim 18, wherein the voltage swing defined by the contour and the low logic level in the first specified voltage specification is nominally about 3 3 volts; And wherein the voltage swing defined by the contour and low logic levels in the second specified voltage specification is nominally about 1.8 volts. 20. A method of operating a flash memory device to communicate with a flash memory controller, the method comprising the steps of: in the 〒I mode of operation, in response to receiving a data selection communication number from the controller Providing a data word to the controller on the input/output line; '120269.doc 200818206 In the normal mode of operation mode #φ, π^, in response to receiving a message from the controller, the data is stored in A and stored in The input/output lines receive the data word of the self-talking controller; ^ in response to receiving an advanced mode signal from the controller, starting an advanced read data transfer mode; Q then driving the read data selection communication No. and the written data selection communication number to the control, the reading data selection communication... The numbers are out of phase with respect to each other; and the 4 input selection communication is synchronized with the reading data selection 4 s, the communication number and the writing Into the data selection communication 諕 檐 ' ' 在 该 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' provide Data word to the controller. The method of claim 20, wherein the spoofing mode corresponds to a standardized specification for communication between the flash memory device and the control $, ^^, e % y J15, Specialized specifications include g ~ plug voltage specifications, the first voltage class sister in the dry ... 1 The data is written to select the communication number and your side of the temple input / output line of the dragons Gan / A / Temple Bell鬲 and low logic level; and wherein the step of providing, the fourth driving step and the providing step are so that the definition is green and the second is the first step, the younger one is determined by the voltage specification. No., etc. Involvement/transmission ~ "Bei material selection communication number and the second specified electric product specification of the data words on the output line are the same as the current KW standard. The logic level definition - the electric current is only less than the voltage swing defined by the first and lower logic levels. The specification is such that the height is 120269.doc 200818206 22 · as in the method of claim 21, , ^ Bajia hunting by the brother of a specified voltage gauge With the low logic level defined by the lean, we fall the voltage swing nominally on the volt; J:: 2: Hunting the voltage swing of the high and low logic levels in the second specified voltage gauge The method of claim 20, wherein the initial step comprises: combining one of the write data selection signals from the controller, and receiving the _ from the controller The command latches the enable signal, receives a start read command value on the input/output lines, and then executes, Ρ, to initiate the advanced read data transfer mode. 24. The method of claim 23 And further comprising: during the step of providing the data word to the controller in the advanced data transfer mode and responding to receiving a pause request from the controller, maintaining one of the input/output lines a value of one of the words, and maintaining the current state of the read enable signal and the write enable signal; and in response to receiving the end of the pause request from the controller, resuming at the advanced data transfer The step of providing a data word to the controller in the mode and the step of driving the read data selection communication number and the write data selection communication number. 25. The method of claim 23, wherein the suspension request corresponds to receiving One of the control signals from the controller transitions; and further comprising: the step of providing the data word to the controller in the advanced data transfer mode and driving the read data selection communication number and the write data strobe 120269.doc -11 - 200818206 Before this step of the signal, combined with the one of the write data selection communication numbers from the controller, and in combination with receiving an address from the controller, the latch enable signal is at the input Receiving, on the output line, a brother memory address from the controller; wherein the pause request corresponds to one of the address latch enable signals during the step of providing the data word to the controller in the advanced data transfer mode ; And wherein the end of the pause request corresponds to a second transition of the address latch enable signal. The method of claim 20, wherein the poor material word is provided in the advanced data transfer mode in synchronization with the first polarity of the read data selection communication number - the first polarity and the write data selection communication number. 27. The method of claim 20, further comprising: initiating an advanced write data transfer mode in response to receiving an advanced mode signal from the controller; receiving the read data from the controller Selecting the communication number and the writing data selection communication number 'the reading data selection communication number and the writing data selection communication number are out of phase with each other; and synchronizing with the reading data selection communication number and the writing data selection communication In the advanced write data transfer mode, the data word received from the controller on the input/output line is stored in the flash memory device. Operation - a method in which a flash memory device is coupled to a flash memory controller, which includes the following steps: in an advanced read data transfer mode of operation: 120269.doc • 12- 200818206 Driver's first reading Selecting the data selection communication number and a writing data selection communication number to the controller, the reading data selection communication number is out of phase with respect to the writing data selection communication number; and synchronizing with the reading data selection communication number and writing One of the selected polarities of each of the data selection communication numbers is changed, corresponding to the data stored in the flash memory device, and the data word is provided on the input/output line to the controller; a command from the controller to initiate a normal operation mode; then responding to receiving a change in polarity selected from one of the read data selection communication numbers from the controller, providing a data word on the input/output line to the a controller; and, after the performing step, responding to receiving a change in polarity selected by one of the write data selection communication numbers from the controller, stored on the input/output lines The information word of the controller. The method of claim 28, wherein the normal mode of operation corresponds to a standardized specification for communication between the flash memory device and the controller, the standardized specifications including - a first-voltage specification, the first-voltage specification, defined for the read data selection communication number, the writer data selection communication number, and the high and low logic levels of the data words on the input/output lines And wherein the driving step is performed with the voltage step of the providing step, and (4) the second voltage reducing specification defines a bus selection communication number, the written data selection communication number, and the high of the data words on the input/output lines. With the low logic level, the second designated power 120269.doc • 13- 200818206 in the repeated specifications of the contour and the low logic level is smaller than by the first-specified thunder heart... swinging substantially ^ Μ ^ ^ ^, straw The voltage swing of the contour and the low logic level is the same as the low logic level. The method of claim 29 is as long as the method of claim 29, and the hope of one of the voltages is determined by the younger one. Logical bit ^ volt; The voltage swing of the derogatory is nominally about 3.3. 31. And wherein the electrical activity defined by the equal level of the second specified voltage specification is approximately 1.8 volts. A flash memory device comprising: a high and a low logic system consisting of a non-volatile memory array arranged in columns and rows, and a H memory unit, a H temporary storage H, poetry storage phase Corresponding to at least the stored state of the memory cells in the memory array; and a control circuit that is connected to the data register, is connected to the input/output terminal, and is connected to the (four) to the complex (four) terminal, and the poem responds to the control signal received at the input/output terminals in a normal operation mode. And in an advanced mode, receiving data from the input/output terminals and providing data to the input/output terminals, and controlling operation of the device; wherein, in the normal operation mode, the control circuit is responsive to a first polarity transition of a read data selection communication number received at a first one of the plurality of control terminals, providing a data word at the input/output terminals; and wherein, in the advanced operation In the mode, the control circuit responds to the 120269.doc -14-200818206 transition of the first polarity and the second polarity of the data selection communication number, and provides reading at the one of the plurality of control terminals Take the data selection communication number ' and provide the data word at the input/output terminals. 32. The device of claim 31, further comprising: a command register coupled to the control circuit; wherein the control circuit is responsive to a write received at a second one of the plurality of control terminals Entering one of the data selection communication numbers, and storing a command value received at the input/output terminals into the temporary storage number of the command; And wherein the control circuit enters the advanced operation mode from the normal operation mode in response to the command value corresponding to the start of the advanced mode. 33. The apparatus of claim 31, further comprising: a command register coupled to the control circuit; wherein the control circuit is responsive to receiving a write at a second one of the plurality of control terminals Transmitting, by one of the data exchange numbers, a command value received at the input/rounding terminal is stored in the command register; and wherein the control circuit is responsive to the command corresponding to the initiation of the normal mode The value enters the normal mode of operation from the advanced mode of operation. 34. The device of claim 31, wherein the normal mode of operation corresponds to a standardized specification for communication between the device and the controller, the first specification comprising a first voltage a specification, the first voltage specification is used for the data selection communication number and the high and low logic levels of the data words at the input/output terminals; and wherein the control circuit follows a second designation The voltage specification is to provide information to the data selection communication number, and the second specified voltage specification is 120269.doc -15-200818206 2 a substantially lower voltage, so that the voltage swing is substantially smaller than the specified by the brother The voltage swing defined by the contour and the low logic level in the voltage specification: the voltage swing defined by the apparatus of the long term 34 藉 by the high and low logic levels in the first specified voltage specification The nominal value is about 3.3. And, the voltage swing defined by the high and low logic levels in the second specified voltage specification is nominally about 1.8 volts. 36. Device in which the advanced In the mode, the control circuit responds to the transition between the first polarity and the second polarity of one of the write-selected communication signals received at the second of the plurality of control terminals. The data word received at the input/output terminal is latched in the data register; and wherein, in the normal mode of operation, the control circuit is responsive to the second one received at the second of the plurality of control terminals Writing a change in the first polarity of the data selection communication number, the data word received at the input/output terminal is latched in the data register. 37. The apparatus of claim 31, further comprising: a command register coupled to the control circuit; wherein the control circuit is responsive to one of the plurality of control terminals to receive a write data selection message number change, combined in the plurality of Controlling, by a third party at the terminal, a command latch enable signal, storing a command value received at the input/output terminals into the command register; 120269.doc -16- 200818206 wherein The control circuit enters the advanced operation mode from the normal operation mode in response to the command value corresponding to the start of the advanced mode; wherein in the a-hi-order operation mode, the control circuit responds to the plurality of controls Receiving a pause request signal in the terminal, at the input/output terminal, returning the - (four) word - the current value and maintaining the read enable signal at the first of the plurality of control terminals a 'state'; wherein the control circuit responds to the receipt of the pause request from the controller, and resumes providing the data to the controller and driving the read in the advanced data transfer mode Data selection communication number; wherein the control circuit combines a data strobe from one of the controllers: a one of the first polarity transitions, and in combination with receiving an address from the control port, the latch enable signal is in the Waiting for the input/output line to receive the memory address from the controller; β and wherein the pause request corresponds to in the advanced data transfer mode • during the provision of the data word to the controller One of the address latch enable signals changes. 38. The device of claim 31, wherein the flash memory device is implemented in a 'ten flash memory subsystem, the flash memory subsystem further comprising a *flash memory controller, The device has a host interface for interfacing with a host system; a data bus that is coupled to the flash memory controller; and a plurality of control lines coupled to the flash memory controller 120269.doc -17- 200818206 wherein the control circuit of the flash memory device is coupled to the data bus and the plurality of control lines, and the control circuit is responsive to receiving from the control lines The control signal, in a normal mode of operation and an advanced mode, receives data from the data bus and provides data to the data bus and controls operation of the device. 39. A flash memory device, comprising: at least one memory array consisting of non-volatile memory cells arranged in columns and rows; a lean register for storing corresponding Data of the stored state of the memory cells in the at least one memory array; and a control circuit that is coupled to the data register, coupled to the input/output, and is coupled to the plurality Control terminals for responding to control signals received at the input/output terminals, receiving data from the input/output terminals and providing data to the in-operation mode and an advanced mode Input/output terminal, and controlling operation of the device; wherein, in the normal operation mode, the control circuit responds to the data access in the plurality of control terminals (four) - a transition of the selected polarity at which the feedstock is provided. In the Weishou mode of operation, the read data selection communication number has a maximum available frequency; ^ wherein, in the advanced mode of operation The control circuit is responsive to the transition of the selected polarity of the read data selection communication number, providing a read f-selection communication number at the one of the plurality of control terminals, and providing at the input/output terminals The data word 120260.doc -18- 200818206 and wherein the frequency of reading the data selection communication number in the advanced data transmission mode is higher than the maximum available frequency of the reading data selection communication number in the normal operation mode. 40. The apparatus of claim 39, further comprising: a command register coupled to the control circuit; wherein the control circuit is responsive to receiving a write at a second one of the plurality of control terminals Transmitting, by one of the data exchange numbers, a command value received at the wheel input/output terminals is stored in the command register; and wherein the control circuit is responsive to the corresponding start mode The command value enters the advanced operation mode from the normal operation mode. 41. The device of claim 39, further comprising: a command register coupled to the control circuit; wherein the control circuit is responsive to a write received at a first one of the plurality of control terminals Transmitting, by one of the data selection communication numbers, a command value received at the input/output terminals is stored in the command register; and wherein the control circuit is responsive to the command corresponding to the initiation of the normal mode The value enters the normal mode of operation from the advanced mode of operation. 42. The device of claim 39, wherein the normal mode of operation corresponds to a standardized specification for communication between the flash memory device and the controller, the standardized specification comprising a first voltage specification, the first The voltage specification defines a high and low logic level for the read data selection communication number and the data words at the input/output terminals; and wherein the control circuit provides 120269 according to a second specified voltage specification. Doc • 19- 200818206 selects a communication number, the second specified voltage specification such that the voltage swing is substantially less than the voltage defined by the high and low logic levels. 43. The electrical swing defined by the first and lower logic levels in the first specified voltage specification is nominally about 33 volts; The voltage swing defined by the high and low logic levels in the mth gauge is nominally w 8 volts. 44. The apparatus of claim 39, wherein, in the advanced mode of operation, the control circuit is responsive to a selected one of the plurality of control terminals - a second person receiving the strobe (4) a change in polarity, latching a f-type word received at the input/output terminals in the f-memory register. wherein, in the normal mode of operation, the write data selection communication number has a maximum available frequency ; The data sub-and the read data are substantially lower than the voltage in the first specified voltage specification. The frequency of the write data selection communication number in the advanced data transmission mode is the maximum available frequency of the communication data selection communication number in the normal operation mode; and in the normal operation mode, The control circuit is responsive to a transition of the write data selection communication number received at the (4): the plurality of control final funds, and the data received at the input/output terminal is latched in the In the data register. 45. The apparatus of claim 39, further comprising: a command register coupled to the control circuit; 120269.doc 200818206 wherein the 4 control circuit is responsive to one of the plurality of control terminals One of the data selection communication numbers is converted, and the command latch enable signal received at one of the plurality of control terminals stores a command value received at the wheel input/output terminals to the command temporary In the memory, wherein the control circuit enters the advanced operation mode from the normal operation mode in response to the command value corresponding to the start of the advanced mode; wherein in the advanced operation mode, the control circuit responds to And a pause request signal received by the one of the plurality of control terminals maintains an active value of one of the data words at the input/output terminal and the first one of the plurality of control terminals Maintaining an active state of one of the read enable signals; wherein the control circuit resumes the transfer of the advanced data in response to receiving one of the pause requests from the controller Providing two materials to the controller and driving the read data selection communication number; wherein the control circuit is combined with one of the first polarities from one of the controllers to write the data selection communication number, and combined with receiving An address from the control state latching enable signal, receiving a memory address from the controller on the input/output lines; and wherein the pause request corresponds to providing a data word in the advanced data transfer mode to The address latches one of the enable signals during the controller. 46. The device of claim 39, wherein the flash memory device is implemented in a flash memory subsystem, the flash memory subsystem further comprising 120269.doc -21 - 200818206 comprising: a flash memory a body controller having a host interface for interfacing with a host system; a data bus coupled to the flash memory controller; and a plurality of control lines coupled to the flash memory a controller; wherein the control circuit of the flash memory device is coupled to the data bus and the plurality of control lines, and the control circuit is configured to respond to control signals received from the control lines, In a normal mode of operation, in an advanced mode, receiving data from the data bus and providing data to the data bus, and controlling the operation of the device. 47. A flash memory device, comprising: at least one memory array consisting of non-volatile memory cells arranged in columns and rows; a nurturing register for storing corresponding The storage state of the memory cells in the at least one memory array; and a control circuit coupled to the data register, coupled to the input/output n-side and coupled to the plurality of controls The terminal is configured to receive the control signals received at the control terminals, and receive information from the input/output terminals and provide data to the inputs in a normal operation mode and an input mode. / outputting a terminal and controlling the operation of the device; wherein, in the normal mode of operation, the control circuit is responsive to a read data selection message received at a plurality of control terminals The data word is provided at the input/output terminals; in the normal operation mode, the control circuit is latched in the complex in response to a data word of the write data strobe at the 120269.doc-22.200818206 Control terminal of the second signal are received at the receive data register in such an input / output terminal; In the advanced operation mode, for a read transfer, the control circuit responds to the read data selection communication number and the write data strobe: one of each of the selected transitions, in the plural The corresponding person of the control terminal provides the reading data selection communication number and the writing person (four) selection communication number, and: providing information words at the input/output terminals, and the writing data selection communication numbers are relative to the reading The data selection communication number is out of phase. 48. The device of claim 47, further comprising: a buffer register coupled to the control circuit; wherein the control circuit is responsive to a write received at a corresponding one of the plurality of control terminals Entering one of the data selection communication numbers, and storing a command value received at the input/output terminals into the command temporary device; And wherein the control circuit responds to the command value corresponding to the start of the advanced mode, and enters the advanced operation mode from the normal operation mode, the command value also indicating whether an advanced mode read transfer is to be implemented. Or a 'implemented advanced mode write transfer. The device of claim 47, further comprising: a command register coupled to the control circuit; wherein the control circuit is responsive to a write received at a corresponding one of the plurality of control terminals Entering one of the data selection communication numbers, storing a command value received at the input/output terminals into the command register 120269.doc • 23 - 200818206; wherein the control circuit responds to the phase Corresponding to the initial normal mode 50 ^ value 'from the money level operation mode into the normal mode of operation. ^ wherein the normal mode of operation corresponds to a standardized specification for communication between the flash memory device fish &amp; ~ controller, the 4 standard specification includes a - one voltage specification, the first voltage specification is The high and low logic levels of the information items in the item selection, the communication number of the writer and the input/output terminal of the item; the second and the second of which the control circuit follows the second Specify the voltage specification to provide the following::, the master data selection communication number and the write data selection communication number, the first-&amp;疋 voltage specification ^ meaning substantially lower voltage, so that the voltage swing is substantially less than the borrowing The voltage swing defined by the high and low logic levels in the first specified voltage specification. The apparatus of claim 50, wherein the voltage swing defined by the height and low logic levels in the first specified voltage gauge is nominally about 3 3 volts; and wherein The voltage swing defined by the contour and low logic levels in the two specified voltage specifications is nominally about 1.8 volts. 52. The device of claim 47, further comprising: a mediator register flanked by the control circuit; wherein the control circuit is responsive to a write received at the second of the plurality of control terminals Incoming one of the data selection communication numbers, combined with a command latch received at one of the plurality of control terminals to enable 120269.doc -24-200818206 a command value stored to the signal, will be in the input / The command register is received by the output terminal; wherein the control circuit is responsive to the phase command value, and the value is also indicated from the normal operation mode to indicate whether a mode write transfer is to be performed; corresponding to starting the advanced mode Entering the advanced mode of operation, the progressive mode read transfer or an advanced In the advanced mode of operation, the control circuit receives a pause request signal in response to the plurality of control terminals, and maintains at the input/output terminals - the current value of the data word and the The plurality of controls, the first one of the terminals maintains an active state of the read data selection communication number and the write data selection communication number; wherein the control circuit is responsive to receiving the suspension request from the controller One of the ends, resumes providing the material in the advanced data transfer mode to the controller and drives the read data selection communication number and the write data selection communication number; ^ ^ where the control circuit is combined with the controller One of the selected data selects one of the selected polarity of the communication number transition, and in combination with receiving an address latch enable signal from the controller, receiving a memory address from the controller on the input/output line; And wherein the pause request corresponds to one of the address latch enable signals transitions during the provision of the lean word to the controller in the advanced data transfer mode. 53. The device of claim 47, wherein the flash memory device is implemented in a flash memory subsystem, the flash memory subsystem further comprising 120269.doc -25-200818206: - flash memory a body controller, configured to interface with a host interface of a host system; a data bus, coupled to the flash memory controller; and a plurality of control lines coupled to the flash memory control The control circuit of the flash memory device is spliced to the data bus and the plurality of control lines, and the control circuit is configured to respond to the control signals received from the control lines in a normal state. In the operating mode ® and an advanced mode, receiving data from the data bus and providing data to the data bus and controlling the operation of the device. 120269.doc 26·