KR101458381B1 - 고성능 플래시 메모리 데이터 전송 - Google Patents

고성능 플래시 메모리 데이터 전송 Download PDF

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Publication number
KR101458381B1
KR101458381B1 KR1020087028524A KR20087028524A KR101458381B1 KR 101458381 B1 KR101458381 B1 KR 101458381B1 KR 1020087028524 A KR1020087028524 A KR 1020087028524A KR 20087028524 A KR20087028524 A KR 20087028524A KR 101458381 B1 KR101458381 B1 KR 101458381B1
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KR
South Korea
Prior art keywords
data
controller
flash memory
mode
strobe signal
Prior art date
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Expired - Fee Related
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KR1020087028524A
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English (en)
Korean (ko)
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KR20090026267A (ko
Inventor
이샤이 카간
리즈완 아흐메드
파루크흐 무가트
제이슨 린
Original Assignee
샌디스크 테크놀로지스, 인코포레이티드
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Publication date
Priority claimed from US11/379,910 external-priority patent/US7345926B2/en
Priority claimed from US11/379,895 external-priority patent/US7366028B2/en
Priority claimed from US11/424,581 external-priority patent/US7366029B2/en
Priority claimed from US11/424,573 external-priority patent/US7525855B2/en
Priority claimed from US11/458,431 external-priority patent/US7499339B2/en
Priority claimed from US11/458,422 external-priority patent/US7499369B2/en
Application filed by 샌디스크 테크놀로지스, 인코포레이티드 filed Critical 샌디스크 테크놀로지스, 인코포레이티드
Publication of KR20090026267A publication Critical patent/KR20090026267A/ko
Application granted granted Critical
Publication of KR101458381B1 publication Critical patent/KR101458381B1/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Read Only Memory (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
KR1020087028524A 2006-04-24 2007-04-20 고성능 플래시 메모리 데이터 전송 Expired - Fee Related KR101458381B1 (ko)

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
US11/379,895 2006-04-24
US11/379,910 US7345926B2 (en) 2006-04-24 2006-04-24 High-performance flash memory data transfer
US11/379,895 US7366028B2 (en) 2006-04-24 2006-04-24 Method of high-performance flash memory data transfer
US11/379,910 2006-04-24
US11/424,573 2006-06-16
US11/424,581 US7366029B2 (en) 2006-04-24 2006-06-16 High-performance flash memory data transfer
US11/424,573 US7525855B2 (en) 2006-04-24 2006-06-16 Method of high-performance flash memory data transfer
US11/424,581 2006-06-16
US11/458,431 US7499339B2 (en) 2006-07-19 2006-07-19 High-performance flash memory data transfer
US11/458,422 2006-07-19
US11/458,431 2006-07-19
US11/458,422 US7499369B2 (en) 2006-07-19 2006-07-19 Method of high-performance flash memory data transfer
PCT/US2007/067090 WO2007127678A2 (en) 2006-04-24 2007-04-20 High-performance flash memory data transfer

Publications (2)

Publication Number Publication Date
KR20090026267A KR20090026267A (ko) 2009-03-12
KR101458381B1 true KR101458381B1 (ko) 2014-11-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020087028524A Expired - Fee Related KR101458381B1 (ko) 2006-04-24 2007-04-20 고성능 플래시 메모리 데이터 전송

Country Status (6)

Country Link
EP (1) EP2011122A2 (enExample)
JP (1) JP5226669B2 (enExample)
KR (1) KR101458381B1 (enExample)
CN (1) CN101479804B (enExample)
TW (1) TWI486964B (enExample)
WO (1) WO2007127678A2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5106219B2 (ja) 2008-03-19 2012-12-26 株式会社東芝 メモリデバイス、ホストデバイス、メモリシステム、メモリデバイスの制御方法、ホストデバイスの制御方法、およびメモリシステムの制御方法
KR101087195B1 (ko) * 2008-05-26 2011-11-29 주식회사 하이닉스반도체 불휘발성 메모리 장치
US8677056B2 (en) 2008-07-01 2014-03-18 Lsi Corporation Methods and apparatus for interfacing between a flash memory controller and a flash memory array
JP5266589B2 (ja) * 2009-05-14 2013-08-21 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
JP5449032B2 (ja) * 2009-05-28 2014-03-19 パナソニック株式会社 メモリシステム
JP2011058847A (ja) * 2009-09-07 2011-03-24 Renesas Electronics Corp 半導体集積回路装置
EP3703055B1 (en) * 2010-02-23 2022-03-16 Rambus Inc. Methods and circuits for dynamically scaling dram power and performance
US8422315B2 (en) * 2010-07-06 2013-04-16 Winbond Electronics Corp. Memory chips and memory devices using the same
JP2012198965A (ja) * 2011-03-22 2012-10-18 Toshiba Corp 不揮発性半導体記憶装置
US9053066B2 (en) 2012-03-30 2015-06-09 Sandisk Technologies Inc. NAND flash memory interface
KR102130171B1 (ko) * 2014-01-13 2020-07-03 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US9385721B1 (en) 2015-01-14 2016-07-05 Sandisk Technologies Llc Bulk driven low swing driver
US9792994B1 (en) 2016-09-28 2017-10-17 Sandisk Technologies Llc Bulk modulation scheme to reduce I/O pin capacitance
JP6894459B2 (ja) * 2019-02-25 2021-06-30 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 疑似スタティックランダムアクセスメモリとその動作方法
JP7714432B2 (ja) * 2021-07-21 2025-07-29 キオクシア株式会社 半導体記憶装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010113496A (ko) * 2000-06-16 2001-12-28 가네꼬 히사시 메모리 제어 기술

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US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
KR100252057B1 (ko) * 1997-12-30 2000-05-01 윤종용 단일 및 이중 데이터 율 겸용 반도체 메모리 장치
JP2000067577A (ja) * 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
JP3416083B2 (ja) * 1999-08-31 2003-06-16 株式会社日立製作所 半導体装置
US6466491B2 (en) * 2000-05-19 2002-10-15 Fujitsu Limited Memory system and memory controller with reliable data latch operation
TWI228259B (en) * 2000-05-22 2005-02-21 Samsung Electronics Co Ltd Method and circuit for inputting and outputting data, and system using semiconductor memory device including the same
US7370168B2 (en) * 2003-04-25 2008-05-06 Renesas Technology Corp. Memory card conforming to a multiple operation standards
US6961269B2 (en) * 2003-06-24 2005-11-01 Micron Technology, Inc. Memory device having data paths with multiple speeds
KR100521049B1 (ko) * 2003-12-30 2005-10-11 주식회사 하이닉스반도체 더블 데이터 레이트 싱크로너스 디램의 쓰기 회로
DE102004026808B4 (de) * 2004-06-02 2007-06-06 Infineon Technologies Ag Abwärtskompatibler Speicherbaustein
KR100546418B1 (ko) * 2004-07-27 2006-01-26 삼성전자주식회사 데이터 출력시 ｄｄｒ 동작을 수행하는 비휘발성 메모리장치 및 데이터 출력 방법

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KR20010113496A (ko) * 2000-06-16 2001-12-28 가네꼬 히사시 메모리 제어 기술

Also Published As

Publication number Publication date
EP2011122A2 (en) 2009-01-07
CN101479804B (zh) 2013-05-01
KR20090026267A (ko) 2009-03-12
TW200818206A (en) 2008-04-16
JP5226669B2 (ja) 2013-07-03
CN101479804A (zh) 2009-07-08
TWI486964B (zh) 2015-06-01
WO2007127678A2 (en) 2007-11-08
JP2009534785A (ja) 2009-09-24
WO2007127678A3 (en) 2008-02-07

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