TWI469309B - 積體電路封裝系統 - Google Patents

積體電路封裝系統 Download PDF

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Publication number
TWI469309B
TWI469309B TW96101208A TW96101208A TWI469309B TW I469309 B TWI469309 B TW I469309B TW 96101208 A TW96101208 A TW 96101208A TW 96101208 A TW96101208 A TW 96101208A TW I469309 B TWI469309 B TW I469309B
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TW
Taiwan
Prior art keywords
integrated circuit
substrate
termination pad
hole
pad
Prior art date
Application number
TW96101208A
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English (en)
Chinese (zh)
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TW200739874A (en
Inventor
林充彬
權奕燦
河宗佑
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星科金朋有限公司
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Application filed by 星科金朋有限公司 filed Critical 星科金朋有限公司
Publication of TW200739874A publication Critical patent/TW200739874A/zh
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Publication of TWI469309B publication Critical patent/TWI469309B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW96101208A 2006-03-17 2007-01-12 積體電路封裝系統 TWI469309B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/276,946 US7501697B2 (en) 2006-03-17 2006-03-17 Integrated circuit package system

Publications (2)

Publication Number Publication Date
TW200739874A TW200739874A (en) 2007-10-16
TWI469309B true TWI469309B (zh) 2015-01-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW96101208A TWI469309B (zh) 2006-03-17 2007-01-12 積體電路封裝系統

Country Status (4)

Country Link
US (2) US7501697B2 (enExample)
JP (1) JP4943898B2 (enExample)
KR (1) KR101424777B1 (enExample)
TW (1) TWI469309B (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US8198735B2 (en) 2006-12-31 2012-06-12 Stats Chippac Ltd. Integrated circuit package with molded cavity
US9466545B1 (en) * 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US7982297B1 (en) * 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US20080315406A1 (en) * 2007-06-25 2008-12-25 Jae Han Chung Integrated circuit package system with cavity substrate
US8258614B2 (en) * 2007-11-12 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with package integration
US20090127715A1 (en) * 2007-11-15 2009-05-21 Shin Hangil Mountable integrated circuit package system with protrusion
US7985628B2 (en) * 2007-12-12 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with interconnect lock
US7781261B2 (en) * 2007-12-12 2010-08-24 Stats Chippac Ltd. Integrated circuit package system with offset stacking and anti-flash structure
US8536692B2 (en) * 2007-12-12 2013-09-17 Stats Chippac Ltd. Mountable integrated circuit package system with mountable integrated circuit die
US8084849B2 (en) * 2007-12-12 2011-12-27 Stats Chippac Ltd. Integrated circuit package system with offset stacking
US8247893B2 (en) * 2007-12-27 2012-08-21 Stats Chippac Ltd. Mountable integrated circuit package system with intra-stack encapsulation
US7800212B2 (en) * 2007-12-27 2010-09-21 Stats Chippac Ltd. Mountable integrated circuit package system with stacking interposer
US8258015B2 (en) * 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US7919871B2 (en) * 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
US9293385B2 (en) * 2008-07-30 2016-03-22 Stats Chippac Ltd. RDL patterning with package on package system
US8304869B2 (en) * 2008-08-01 2012-11-06 Stats Chippac Ltd. Fan-in interposer on lead frame for an integrated circuit package on package system
US7750455B2 (en) * 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
US8513801B2 (en) * 2008-08-18 2013-08-20 Stats Chippac Ltd. Integrated circuit package system
US8406004B2 (en) 2008-12-09 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
US7923290B2 (en) * 2009-03-27 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system having dual sided connection and method of manufacture thereof
US8004073B2 (en) * 2009-06-17 2011-08-23 Stats Chippac Ltd. Integrated circuit packaging system with interposer and method of manufacture thereof
TWI411051B (zh) 2009-12-02 2013-10-01 晨星半導體股份有限公司 封裝層疊方法與結構及其電路板系統
CN102087983A (zh) * 2009-12-07 2011-06-08 晨星软件研发(深圳)有限公司 封装层叠方法与结构及其电路板系统
KR101695352B1 (ko) * 2010-08-12 2017-01-12 삼성전자 주식회사 리드 프레임 및 이를 갖는 반도체 패키지
CN102569247A (zh) * 2012-01-17 2012-07-11 华为终端有限公司 集成模块、集成系统板和电子设备
JP2014150213A (ja) * 2013-02-04 2014-08-21 Fujitsu Semiconductor Ltd 半導体装置及び半導体装置の製造方法
US9312198B2 (en) 2013-03-15 2016-04-12 Intel Deutschland Gmbh Chip package-in-package and method thereof
KR102729072B1 (ko) 2019-08-28 2024-11-13 삼성전자주식회사 반도체 패키지
KR20240023263A (ko) * 2022-08-11 2024-02-21 삼성전자주식회사 반도체 패키지

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200416787A (en) * 2002-10-08 2004-09-01 Chippac Inc Semiconductor stacked multi-package module having inverted second package

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
US5656550A (en) * 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US5663593A (en) * 1995-10-17 1997-09-02 National Semiconductor Corporation Ball grid array package with lead frame
JP3297387B2 (ja) * 1998-11-20 2002-07-02 沖電気工業株式会社 半導体装置の製造方法
JP3722209B2 (ja) * 2000-09-05 2005-11-30 セイコーエプソン株式会社 半導体装置
US6967395B1 (en) * 2001-03-20 2005-11-22 Amkor Technology, Inc. Mounting for a package containing a chip
US6946323B1 (en) * 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US7109574B2 (en) * 2002-07-26 2006-09-19 Stmicroelectronics, Inc. Integrated circuit package with exposed die surfaces and auxiliary attachment
US6965160B2 (en) * 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
US6972481B2 (en) * 2002-09-17 2005-12-06 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US6861288B2 (en) * 2003-01-23 2005-03-01 St Assembly Test Services, Ltd. Stacked semiconductor packages and method for the fabrication thereof
US6936922B1 (en) * 2003-09-26 2005-08-30 Amkor Technology, Inc. Semiconductor package structure reducing warpage and manufacturing method thereof
JP4580671B2 (ja) * 2004-03-29 2010-11-17 ルネサスエレクトロニクス株式会社 半導体装置
US7205656B2 (en) * 2005-02-22 2007-04-17 Micron Technology, Inc. Stacked device package for peripheral and center device pad layout device
US7372141B2 (en) * 2005-03-31 2008-05-13 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US7535086B2 (en) * 2006-08-03 2009-05-19 Stats Chippac Ltd. Integrated circuit package-on-package stacking system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200416787A (en) * 2002-10-08 2004-09-01 Chippac Inc Semiconductor stacked multi-package module having inverted second package

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