CN102087983A - 封装层叠方法与结构及其电路板系统 - Google Patents
封装层叠方法与结构及其电路板系统 Download PDFInfo
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Abstract
本发明是一种封装层叠方法与结构及其电路板系统。封装层叠方法包括:接合导线架与基板;将集成电路与基板接合,并电连接集成电路与导线架;以及将集成电路、基板的一部分及导线架的一部分进行封装并暴露一表面贴装接合区以形成凹型封装结构。
Description
技术领域
本发明有关一种集成电路封装方法、结构及其电路板系统,特别是有关于一种封装层叠方法与结构及其电路板系统。
背景技术
集成电路封装属于半导体产业的后段加工工序,主要是将晶片上的集成电路予以分割、黏晶,并加上外接引脚及包覆。而其成品(封装体)主要是提供一个引接的接口,内部电性信号可通过封装材料,例如引脚,将其连接到系统,并提供硅芯片免于受外力与水、湿气、化学物的破坏与腐蚀等。常见的集成电路封装方式包含有双列直插式封装(Dual In-line Package,DIP)、塑料方型扁平式封装(PlasticQuad Flat Package,PQFP)、塑料扁平封装(Plastic Flat Package,PFP)、针栅阵列封装(Pin Grid Array Package,PGA)、球栅阵列封装(Ball Grid Array Package,BGA)等。
集成电路封装由集成电路、导线架(lead frame)及壳体所组成。请参考图1,图1显示现有集成电路封装10的剖示图,包含集成电路102、集成电路托盘(diepaddle)104、引脚(finger)106、金线108及壳体100。集成电路102为集成电路封装10的核心单元,用来进行模拟或数字信号处理。集成电路托盘104与引脚106形成导线架,承载集成电路102及焊接金线108,使信号得以顺利传递。壳体100用来填充模穴(cavity),以保护集成电路封装10,其材质可为陶瓷或塑料,如热固性环氧树脂(Epoxy Molding Compound,EMC)。一般而言,金线108与引脚106的电感值约为每毫米1纳亨(nH/mm)及0.8nH/mm,例如在256引脚的薄型方型扁平式封装(Low Profile Quad Flat Package)中,金线108与引脚106的长度为3mm与8~10mm,所形成的等效电感值约为10.2nH。
一般而言,将集成电路组装到系统级封装(System-In-Package,简称SIP)有多种方法:堆叠组装、相邻组装(side-by-side)、封装层叠(Package on Package,简称PoP)以及四方扁平封装(Quad Flat Package,简称QFP)型。每一种方法都有其独特之处,堆叠技术在缩小封装尺寸方面特别有效,是要求小外形尺寸的系统级封装的最佳选择,而相邻组装通常用于功耗很大的集成电路。
相较于在电路板(printed circuit board,简称PCB)上采用多个集成电路的系统设计,使用系统级封装实现的方案可以更小、更轻、更薄,另一个好处是这样可以减少或消除系统厂商对高速电路设计的需求。另一项与此相关的优势是系统级封装产生的电磁干扰(electromagnetic interference,简称EMI)噪讯更小。
通常一个构建在电路板上的嵌入式系统,其噪讯程度大约为90dB。而用系统级封装技术则能大幅度地将噪讯程度降低到60dB左右。这种改善主要是由于系统级封装基板上的连接线很短,以及其适当的电源设计。另一个优点是系统级封装将峰值电压降低许多,如此将简化系统厂商终端产品设计。
由于系统级封装节省了电路板空间,因此也附带降低了电路板成本。同样地,由于系统级封装元件可以得到充分的测试,因而可以节省系统厂商的测试时间,还能降低测试设备的投资,并减少元件的采购流程以及元件库存。与系统单芯片(system on chip,简称SoC)相比,系统级封装的开发周期更短而开发成本更低。因此,本发明提出一种系统级封装,特别是有关于一种封装层叠的方法与结构及其电路板系统。
发明内容
本发明提出一种封装层叠方法,包括:接合导线架与基板;将集成电路与基板接合,并电连接集成电路与导线架;以及将集成电路、基板的一部分及导线架的一部分进行封装并暴露一表面贴装接合区以形成凹型封装结构。
本发明还提出一种封装层叠结构,包括:基板;导线架,电连接至该基板;集成电路,接合至基板以及电连接导线架;以及凹型包覆,其中,凹型包覆是凹型包覆基板的一部分、导线架的一部分与集成电路,使得基板曝露一表面贴装接合区。
本发明更提出一种电路板系统,包括:基板;导线架,电连接至基板;双层电路板,电连接至导线架;集成电路,接合基板以及电连接导线架;以及凹型包覆,其中,凹型包覆是凹型包覆基板的一部分、导线架的一部分与集成电路,使得基板曝露一表面贴装接合区。
附图说明
为了使能更进一步了解本发明特征及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明,并非用来对本发明加以限制,其中:
图1为现有集成电路封装的剖示图。
图2显示根据本发明实施例的基板与导线架接合的架构图。
图3显示根据本发明实施例的置入集成电路后的结构图。
图4显示根据本发明实施例的凹型封装结构图。
图5显示根据本发明实施例的电路板系统结构图。
图6显示根据本发明实施例的封装层叠方法流程图。
具体实施方式
随着多媒体产品的普及以及对更高数字信号处理、具有更高储存容量和灵活性的新型储存架构的迫切需求,堆叠式封装层叠(stacked package on package,简称PoP)应用正快速成长。在整合复杂逻辑和存储器方面,封装层叠是一种新兴的、成本低的三维(3D)封装解决方案。系统设计师可以利用封装层叠开发新的元件外形、整合更多的半导体,并可通过由堆叠带来的封装体积优势减少电路板(printedcircuit board,简称PCB)的尺寸。
封装层叠可以在原始设备制造(Original Equipment Manufacturer,简称OEM)厂商、逻辑和存储器供应厂商的合作下开发完成,封装层叠解决了影响高密度逻辑与存储器整合的问题。由于原始设备制造厂商的终端产品元件中的封装堆叠技术解决了高密度整合问题,因此封装层叠可提供最佳的成本,并消除堆叠集成电路装配和测试元件流程中固有的良率下降、测试复杂性和冗余堆叠问题。由于原始设备制造厂商拥有封装堆叠工序,而封装层叠又允许逻辑和元件供货商使用其现有的装配及测试基础架构和流程,因此原始设备制造厂商可最佳化制造成本,保证来源的灵活。
系统级封装可以说组合了板上系统(system on board)以及将系统变成一个集成电路(die),构成具系统单芯片(system on chip,简称SoC)长处的构装技术。系统级封装的特性除了可将两个以上的集成电路组合之外,系统级封装还能将机能完成的系统或次系统整合在一个封装当中。系统级封装可以包含一个或多个打线、集成电路(integrated circuit,简称IC)之外,还可将分离式的被动元件埋在封装基板当中,或将以材料形成方式(forming)的被动元件、表面声波滤波器(SurfaceAcoustic Wave filter,简称SAW filter)、电磁干扰屏蔽、电容、未封装集成电路(prepackaged IC)、机械(mechanical)元件等,以及组装到系统基板中的其它标准元件中也内埋在封装基板中。因此可以将多层电路板降低为两层电路板或更少,以降低系统厂商的制造成本。
图2至图5显示根据本发明实施例的所产生的封装结构图。图2显示基板与导线架接合的架构图,接合架构20包括基板22与导线架24,首先接合导线架24与基板22,接合方式可为压印或黏贴。导线架24可为金属导线架。
图3显示根据本发明实施例的置入集成电路34后的结构图。结构30包括基板22、导线架24、连接线32与集成电路34。将集成电路34与基板22接合,并用连接线32电连接集成电路34与导线架24,亦可将集成电路34直接接合导线架24,接合方式非用以限定本发明。举例而言,集成电路34可为特定应用集成电路(application-specific integrated circuit,简称ASIC)或数字信号处理器(digital signalprocessor,简称DSP);连接线32可为金线、铜线或其它金属导线。集成电路34可以是任何型式的电路,并不受限于互补式金属氧化物半导体(complementarymetal-oxide-semiconductor,简称CMOS)或双载子接面晶体管(bipolar junctiontransistor,简称BJT)。
图4显示根据本发明实施例的凹型封装结构图,凹型封装结构40包括基板22、导线架24、连接线32、集成电路34与凹型包覆42。图4显示将图3中结构30进行凹型封装,也就是说,封装基板22的一部分、导线架24的一部分、集成电路34以及连接线32,以暴露一表面贴装接合区(surface mount joint,简称SMT joint)而将其余部分封装。由于表面贴装接合区并未封装,因此可以叠加额外的集成电路或其它元件,较佳地为具有高速传输接口的元件,例如第三代双倍数据率同步动态随机存取存储器(double-data-rate three synchronous dynamic random access memory,简称DDR3存储器)或串行式先进附加技术(serial advanced technology attachment,简称SATA)接口。也由于表面贴装接合区是暴露在外面,可便利对凹型封装结构40做一些进行测试,例如:电源测试、接地测试或功能测试,将不合格(fail)的凹型封装结构40剔除,以避免后续叠加额外的集成电路或其它元件时连带影响叠加的集成电路,使得制造成本增加。此凹型封装结构40可以是由多个凹型封装结构通过切割分离而得到一个凹型封装结构40。
图5显示根据本发明实施例的电路板系统50,包括基板22、导线架24、连接线32、集成电路34、凹型包覆42、元件52与电路板54。首先测试元件52,将不合格的元件52剔除,以避免接合至凹型封装结构40时影响凹型封装结构40,造成凹型封装结构40损坏丢弃,使得制造成本增加。接着将测试好的元件52接合至凹型封装结构40的表面贴装接合区成为一层叠结构,之后可以将此层叠结构再做封装以成为一系统级封装结构,然后,再对系统级封装结构进行测试。此系统级封装结构可电连接于一电路板54,较佳地可为一双层电路板,以供系统厂商做进一步的利用。较佳地,元件52为具有高速传输接口的元件,例如DDR3存储器,应注意到,原本应该位于电路板的DDR3存储器,根据本实施例的揭露,可直接接合于凹型封装结构40的表面贴装接合区,可以具有低电感、低干扰的信号传输品质,如此一来,可以降低对电路板品质等级的要求,而可以使用低成本的双层电路板。另一方面,在系统生产流程方面也深具优点,本实施例解决了影响高密度逻辑与存储器整合的问题,并消除堆叠集成电路装配和测试元件流程中良率下降、测试复杂性和冗余堆叠的问题。本实施例还允许目前的逻辑和元件供货商使用其现有的装配及测试基础架构和流程,因此系统制造厂商可最佳化制造成本,保证料件来源的灵活,选用符合自己需求的元件而不受限于个别厂商。
举例而言,元件52可以是被动元件、存储器、具有高速传输接口的元件。其封装方式可为四方扁平封装、球格阵列封装(Ball Grid Array,简称BGA)、陶瓷针栅阵列封装(Ceramic Pin Grid Array,简称CPGA)、双列直插式封装(Dual InlinePackage,简称DIP)、覆晶针脚栅格阵列封装(Flip-chip Pin Grid Array,简称FCPGA)、有机针脚网格阵列封装(Organic Pin Grid Array,简称OPGA)、薄型小尺寸封装(Thin Small Outline Package,简称TSOP)、小尺寸J形针脚封装(SmallOutline J-Lead,简称SOJ)、小尺寸集成电路封装(Small Outline Integrated Circuit,简称SOIC)、收缩小型封装(Shrink Small-Outline Package,简称SSOP)、薄型四方扁平封装(Thin Quad Flat Pack,简称TQFP)、塑料晶粒承载封装(Plastic LeadedChip Carrier,简称PLCC)、塑料四方扁平封装(Plastic Quad Flat Pack,简称PQFP)、晶片级芯片尺寸封装(Wafer Level Chip Scale Package,简称WLCSP)、铸造阵列处理球栅阵列封装(Mold Array Process-Ball Grid Array,简称MAPBGA)、无引线四方扁平封装(Quad Flat No-Lead,简称QFN)、地栅阵列封装(Land Grid Array,简称LGA)或针栅阵列封装(Pin Grid Array,简称PGA)。
图6为根据本发明实施例的封装层叠方法流程图。步骤620为接合导线架与基板,接合方式可为压印或黏贴;步骤640为将集成电路与基板接合,并电连接集成电路与导线架;步骤660为将集成电路做凹型封装并暴露表面贴装接合区,也就是说,封装基板的一部分、导线架的一部分、集成电路以及连接线,暴露表面贴装接合区而将其余部分封装;步骤680为将一元件接合至表面贴装接合区。
综上所述,虽然本发明已以较佳实施例揭露如上,然而其并非用以限定本发明。任何熟悉此技术者,在不脱离本发明的精神和范围内,当可作各种更动与润饰,本发明的保护范围当视后附的本申请权利要求范围所界定的为准。
Claims (20)
1.一种封装层叠方法,包括:
接合一导线架与一基板;
将一集成电路与该基板接合,并电连接该集成电路与该导线架;以及
将该集成电路、该基板的一部分及该导线架的一部分进行封装并暴露一表面贴装接合区以形成一凹型封装结构。
2.根据权利要求1所述的封装层叠方法,其特征在于,还包括在该表面贴装接合区接合一元件以形成一层叠结构。
3.根据权利要求2所述的封装层叠方法,其特征在于,该元件是为一具有高速传输接口的元件。
4.根据权利要求2所述的封装层叠方法,其特征在于,该元件是一被动元件或一存储器。
5.根据权利要求2所述的封装层叠方法,其特征在于,该元件的封装方式为一四方扁平封装、一球格阵列封装、一陶瓷针栅阵列封装、一双列直插式封装、一覆晶针脚栅格阵列封装、一有机针脚网格阵列封装、一薄型小尺寸封装、一小尺寸J形针脚封装、一小尺寸集成电路封装、一收缩小型封装、一薄型四方扁平封装、一塑料晶粒承载封装、一塑料四方扁平封装、一晶片级芯片尺寸封装、一铸造阵列处理球栅阵列封装、一无引线四方扁平封装、一地栅阵列封装或一针栅阵列封装。
6.根据权利要求2所述的封装层叠方法,其特征在于,还包括封装该层叠结构以形成一系统级封装结构。
7.根据权利要求6所述的封装层叠方法,其特征在于,还包括测试该系统级封装结构。
8.根据权利要求2所述的封装层叠方法,其特征在于,还包括测试该元件。
9.根据权利要求1所述的封装层叠方法,其特征在于,还包括测试该凹型封装结构。
10.根据权利要求1所述的封装层叠方法,其特征在于,还包括将该凹型封装结构电连接于一电路板。
11.根据权利要求10所述的封装层叠方法,其特征在于,该电路板是一双层电路板。
12.一种封装层叠结构,包括:
一基板;
一导线架,电连接至该基板;
一集成电路,接合至该基板以及电连接该导线架;以及
一凹型包覆;
其中,该凹型包覆是凹型包覆该基板的一部分、该导线架的一部分与该集成电路,使得该基板曝露一表面贴装接合区。
13.根据权利要求12所述的封装层叠结构,其特征在于,还包括一元件,接合至该凹型包覆。
14.根据权利要求13所述的封装层叠结构,其特征在于,该元件是一具有高速传输接口的元件。
15.根据权利要求13所述的封装层叠结构,其特征在于,该元件是一被动元件或一存储器。
16.根据权利要求13所述的封装层叠结构,其特征在于,该元件的封装方式为一四方扁平封装、一球格阵列封装、一陶瓷针栅阵列封装、一双列直插式封装、一倒装芯片针脚栅格阵列封装、一有机针脚网格阵列封装、一薄型小尺寸封装、一小尺寸J形针脚封装、一小尺寸集成电路封装、一收缩小型封装、一薄型四方扁平封装、一塑料晶粒承载封装、一塑料四方扁平封装、一晶片级芯片尺寸封装、一铸造阵列处理球栅阵列封装、一无引线四方扁平封装、一地栅阵列封装或一针栅阵列封装。
17.根据权利要求12所述的封装层叠结构,其特征在于,该集成电路是通过多个连接线电连接该导线架。
18.一种电路板系统,包括:
一基板;
一导线架,电连接至该基板;
一双层电路板,电连接至该导线架;
一集成电路,接合该基板以及电连接该导线架;以及
一凹型包覆;
其中,该凹型包覆是凹型包覆该基板的一部分、该导线架的一部分与该集成电路,使得该基板曝露一表面贴装接合区。
19.根据权利要求18所述的电路板系统,其特征在于,还包括一元件,接合至该表面贴装接合区。
20.根据权利要求19所述的电路板系统,其特征在于,该元件是一具有高速传输接口的元件。
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