TWI456665B - 半導體積體結構的製造方法 - Google Patents

半導體積體結構的製造方法 Download PDF

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TWI456665B
TWI456665B TW100138539A TW100138539A TWI456665B TW I456665 B TWI456665 B TW I456665B TW 100138539 A TW100138539 A TW 100138539A TW 100138539 A TW100138539 A TW 100138539A TW I456665 B TWI456665 B TW I456665B
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dielectric layer
layer
forming
substrate
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TW201250858A (en
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Chunhung Huang
Yuhsien Lin
Mingyi Lin
Jyhhuei Chen
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Taiwan Semiconductor Mfg
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Claims (10)

  1. 一種半導體積體結構的製造方法，包含：提供具有一第一區及一第二區的一基材；形成具有一第一材料之一第一介電層於該第一區之該基材上；形成具有一第二材料之一第二介電層於該第二區之該基材上，其中該第二材料不同於該第一材料；形成一犧牲閘極層於該第一介電層和該第二介電層上；圖案化該犧牲閘極層、該第一介電層和該第二介電層，以形成複數個閘極堆疊於該第一區和該第二區中；形成一層間介電(Interlayer Dielectric；ILD)層於該第一區和該第二區的該些閘極堆疊中；去除該第一區及第二區中之該犧牲閘極層；以及去除至少一部分之該第二介電層。
  2. 如請求項1所述之半導體積體結構的製造方法，其中在該至少一部分之該第二介電層的去除期間，該第一介電層並未被實質地去除。
  3. 如請求項1所述之半導體積體結構的製造方法，其中該第一材料係氧化矽，和該第二材料係氮化矽。
  4. 如請求項1所述之半導體積體結構的製造方法，其中形成該第二介電層於該第二區中的該步驟係透過一選擇性製程(Selective Process)來進行，藉以使該第二介電層不形成於該第一區中。
  5. 如請求項4所述之半導體積體結構的製造方法，其中該選擇性製程係使用一含氮氣體進行之一熱處理製程，其中該熱處理製程，包含：該熱處理製程為一爐熱製程、一快速退火(Rapid Thermal Annealing；RTA)製程、或一臨場蒸氣產生(In-Situ Steam Generation；ISSG)製程；以及該熱處理製程係在實質介於300℃至700℃間之一範圍，和實質介於0.1毫托爾(mTorr)至10毫托爾(mTorr)間之一壓力下來進行。
  6. 如請求項1所述之半導體積體結構的製造方法，更包含：在形成該第二介電層後進行一退火製程，且該退火製程係使用氧氣來進行。
  7. 一種半導體積體結構的製造方法，包含：提供具有一元件區及一輸入/輸出(Input/Output；I/O)區的一基材；形成一第一介電層於該基材上；去除於該元件區中之該第一介電層的一部分選擇性形成一第二介電層於該元件區之該基材上，其中該第一介電層和該第二介電層間有一蝕刻選擇率；形成一犧牲閘極層於該第一介電層和該第二介電層上；圖案化該犧牲閘極層、該第一介電層和該第二介電層，以形成複數個閘極堆疊於該元件區和該I/O區中；形成一ILD層於該元件區和該I/O區的該些閘極堆疊中；去除該元件區和該I/O區中之該犧牲閘極層；以及去除該元件區中之該第二介電層，其中在該第二介電層的去除期間，於該I/O區中該第一介電層並未被實質地去除。
  8. 如請求項7所述之半導體積體結構的製造方法，其中該第一介電層比該第二介電層薄。
  9. 如請求項7所述之半導體積體結構的製造方法，其中該去除該第二介電層的步驟係由使用一磷酸溶液之濕式蝕刻製程來進行，且該第二介電層和該第一介電層間之蝕刻選擇率係實質介於80至100之間。
  10. 一種半導體積體結構的製造方法，包含：提供具有一元件區及一I/O區的一基材；形成一氧化層於該基材上；去除部分之該氧化層，以暴露出該元件區中之該基材；選擇性地形成一氮化層於該元件區之該基材上；形成一多晶矽層於該氧化層和該氮化層上；圖案化該多晶矽層、該氧化層和該氮化層，以形成複數個閘極堆疊於該元件區和該I/O區中；形成一ILD層於該元件區和該I/O區的該些閘極堆疊中；去除該多晶矽層以形成複數個開口於該元件區和該I/O區中；去除位於該元件區之該些開口中之該氮化層，而不實質地去除位於該I/O區之該些開口中之該氧化層；形成一高K值閘極介電層於該元件區和該I/O區之該些開口中；以及形成一金屬閘極電極於該高K值閘極介電層上。
TW100138539A 2011-05-13 2011-10-24 半導體積體結構的製造方法 TWI456665B (zh)

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US9129856B2 (en) * 2011-07-08 2015-09-08 Broadcom Corporation Method for efficiently fabricating memory cells with logic FETs and related structure
US20130049134A1 (en) * 2011-08-30 2013-02-28 Renesas Electronics Corporation Semiconductor device and method of making same
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