TWI456656B - 介電蝕刻中的輪廓控制 - Google Patents
介電蝕刻中的輪廓控制 Download PDFInfo
- Publication number
- TWI456656B TWI456656B TW097136482A TW97136482A TWI456656B TW I456656 B TWI456656 B TW I456656B TW 097136482 A TW097136482 A TW 097136482A TW 97136482 A TW97136482 A TW 97136482A TW I456656 B TWI456656 B TW I456656B
- Authority
- TW
- Taiwan
- Prior art keywords
- gas
- cos
- etchant
- computer readable
- etchant gas
- Prior art date
Links
- 239000007789 gas Substances 0.000 claims 51
- 238000000034 method Methods 0.000 claims 12
- 238000005530 etching Methods 0.000 claims 6
- 239000000758 substrate Substances 0.000 claims 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 5
- 239000001301 oxygen Substances 0.000 claims 5
- 229910052760 oxygen Inorganic materials 0.000 claims 5
- 239000011295 pitch Substances 0.000 claims 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 4
- 239000012159 carrier gas Substances 0.000 claims 2
- 229910052681 coesite Inorganic materials 0.000 claims 2
- 229910052906 cristobalite Inorganic materials 0.000 claims 2
- 239000000203 mixture Substances 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- 235000012239 silicon dioxide Nutrition 0.000 claims 2
- 229910052682 stishovite Inorganic materials 0.000 claims 2
- 229910052905 tridymite Inorganic materials 0.000 claims 2
- 238000007599 discharging Methods 0.000 claims 1
- 239000000376 reactant Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Claims (16)
- 一種用於蝕刻一介電層之方法,該介電層設置在一基材的上方並在具有一列間距圖案之一已圖案化遮罩的下方,該方法包含:提供包含CF4 、COS、及一含氧氣體之一蝕刻劑氣體;從該蝕刻劑氣體形成一電漿;以及藉由該遮罩及來自該蝕刻劑氣體之該電漿,將該介電層蝕刻為該列間距圖案,其中CF4 之一氣流率具有大於所有反應氣體成分的總氣流率之50%的比率,以及其中COS的一氣流率在CF4 之該氣流率的1%及50%之間。
- 如申請專利範圍第1項之方法,其中COS的該氣流率在CF4 之該氣流率的2%及20%之間。
- 如申請專利範圍第2項之方法,其中COS的該氣流率在CF4 之該氣流率的3%及15%之間。
- 如申請專利範圍第1項之方法,其中該蝕刻劑氣體另外包含Ar、He、或Xe之一者,或彼等之混合物,以作為一載體氣體。
- 如申請專利範圍第1項之方法,其中該蝕刻劑氣體另外包含一氫氟碳化合物氣體。
- 如申請專利範圍第1項之方法,其中該介電層係SiN、SiO2 、或正矽酸四乙酯(TEOS)之其中一者。
- 一種用於在蝕刻一介電層時減少弓形之方法,該介電層設置在一基材的上方並在具有一列間距圖案之一已圖 案化遮罩的下方,該方法包含:提供包含CF4 、COS、及一含氧氣體之一蝕刻劑氣體,CF4 之一氣流率具有大於所有反應氣體成分的總氣流率之50%的比率,且COS的一氣流率具有在CF4 之該氣流率的3%及15%之間的比率;從該蝕刻劑氣體形成一電漿;以及藉由該遮罩及來自該蝕刻劑氣體之該電漿,將該介電層蝕刻為該列間距圖案。
- 如申請專利範圍第7項之方法,其中該蝕刻劑氣體另外包含Ar、He、或Xe之一者,或彼等之混合物,以作為一載體氣體。
- 如申請專利範圍第7項之方法,其中該蝕刻劑氣體另外包含一氫氟碳化合物氣體。
- 如申請專利範圍第7項之方法,其中該介電層係SiN、SiO2 、或正矽酸四乙酯(TEOS)之其中一者。
- 一種用於蝕刻一介電層之設備,該介電層設置在一基材的上方並在具有一列間距之一已圖案化遮罩的下方,該設備包含:一電漿處理室,包含:一室壁,其形成一電漿處理室封閉體;一基材支撐,其用於在該電漿處理室封閉體內支撐一基材;一壓力調整器,其用於調整該電漿處理室封閉體內的壓力; 至少一電極,其用於提供電力至該電漿處理室封閉體以保持電漿;一氣體進氣口,其用於提供氣體進入該電漿處理室封閉體;以及一氣體出氣口,其用於從該電漿處理室封閉體排出氣體;一蝕刻劑氣體源,其與該氣體進氣口流體連接,包含:一CF4 源;一COS源;以及一含氧氣體源;一控制器,其可控制地連接至該氣體源及該至少一個電極,包含:至少一個處理器;以及電腦可讀媒體,其包含:用於藉由該遮罩將該介電層蝕刻為該列間距圖案的電腦可讀編碼,其中電腦可讀編碼包含:用於從該蝕刻劑氣體源提供包含CF4 、COS、及一含氧氣體之一蝕刻劑氣體的電腦可讀編碼,包括用於控制CF4 之一氣流率,以具有大於所有反應氣體成分的總氣流率之50%的比率的電腦可讀編碼,以及用於控制COS的一氣流率在CF4 之該氣流率的1%及50%之間的電腦可讀編碼;用於從該蝕刻劑氣體產生一蝕刻電漿的電腦可讀編碼;以及用於從該蝕刻劑氣體源停止該蝕刻劑氣體的電腦 可讀編碼;以及用於移除該遮罩的電腦可讀編碼。
- 如申請專利範圍第11項之設備,其中用於提供該蝕刻劑氣體之該電腦可讀編碼包含:用於控制COS的該氣流率在CF4 之該氣流率的2%及20%之間的電腦可讀編碼。
- 如申請專利範圍第12項之設備,其中用於提供該蝕刻劑氣體之該電腦可讀編碼包含:用於控制COS的該氣流率在CF4 之該氣流率的3%及15%之間的電腦可讀編碼。
- 一種用於蝕刻一介電層之設備,該介電層設置在一基材的上方並在具有一列間距圖案之一已圖案化遮罩的下方,該設備包含:用於提供包含CF4 、COS、及一含氧氣體之一蝕刻劑氣體的機構,包括;用於控制CF4 之一氣流率,以具有大於所有反應氣體成分的總氣流率之50%的比率的機構;以及用於控制COS的一氣流率以在CF4 之該氣流率的1%及50%之間的機構;用於從該蝕刻劑氣體形成一電漿的機構;以及用於藉由該遮罩及來自該蝕刻劑氣體之該電漿,將該介電層蝕刻為該列間距圖案的機構。
- 如申請專利範圍第14項之設備,其中用於提供蝕刻劑氣體之該機構另外包含: 用於控制COS的該氣流率以在CF4 之該氣流率的2%及20%之間的機構。
- 如申請專利範圍第15項之設備,其中用於提供蝕刻劑氣體之該機構另外包含:用於控制COS的該氣流率以在CF4 之該氣流率的3%及15%之間的機構。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US97575207P | 2007-09-27 | 2007-09-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200933734A TW200933734A (en) | 2009-08-01 |
TWI456656B true TWI456656B (zh) | 2014-10-11 |
Family
ID=40512082
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097136482A TWI456656B (zh) | 2007-09-27 | 2008-09-23 | 介電蝕刻中的輪廓控制 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8501627B2 (zh) |
KR (1) | KR101528947B1 (zh) |
CN (1) | CN101809721B (zh) |
TW (1) | TWI456656B (zh) |
WO (1) | WO2009042453A2 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009200080A (ja) * | 2008-02-19 | 2009-09-03 | Tokyo Electron Ltd | プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体 |
US8394722B2 (en) * | 2008-11-03 | 2013-03-12 | Lam Research Corporation | Bi-layer, tri-layer mask CD control |
KR102333443B1 (ko) | 2014-10-24 | 2021-12-02 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
KR20160119329A (ko) | 2015-04-02 | 2016-10-13 | 삼성전자주식회사 | 반도체 소자의 미세패턴 형성방법 |
US9673058B1 (en) * | 2016-03-14 | 2017-06-06 | Lam Research Corporation | Method for etching features in dielectric layers |
CN109997212B (zh) | 2016-11-29 | 2023-06-13 | 朗姆研究公司 | 在有机层蚀刻中生成竖直轮廓的方法 |
US9941123B1 (en) * | 2017-04-10 | 2018-04-10 | Lam Research Corporation | Post etch treatment to prevent pattern collapse |
US10600648B2 (en) * | 2017-04-20 | 2020-03-24 | Lam Research Corporation | Silicon-based deposition for semiconductor processing |
CN112368805A (zh) | 2018-12-18 | 2021-02-12 | 玛特森技术公司 | 使用含硫工艺气体的含碳硬掩模去除工艺 |
KR20220010648A (ko) | 2020-07-16 | 2022-01-26 | 삼성전자주식회사 | 플라즈마 식각 장치, 플라즈마 식각 방법 및 그를 포함하는 반도체 소자의 제조 방법 |
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TW200614369A (en) * | 2004-06-30 | 2006-05-01 | Lam Res Corp | Methods and apparatus for the optimization of etch resistance in a plasma processing system |
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2008
- 2008-09-16 CN CN2008801094475A patent/CN101809721B/zh not_active Expired - Fee Related
- 2008-09-16 KR KR1020107009127A patent/KR101528947B1/ko active IP Right Grant
- 2008-09-16 US US12/679,008 patent/US8501627B2/en not_active Expired - Fee Related
- 2008-09-16 WO PCT/US2008/076542 patent/WO2009042453A2/en active Application Filing
- 2008-09-23 TW TW097136482A patent/TWI456656B/zh not_active IP Right Cessation
Patent Citations (3)
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US5376228A (en) * | 1992-06-29 | 1994-12-27 | Sony Corporation | Dry etching method |
TW200614369A (en) * | 2004-06-30 | 2006-05-01 | Lam Res Corp | Methods and apparatus for the optimization of etch resistance in a plasma processing system |
US20060226120A1 (en) * | 2005-03-30 | 2006-10-12 | Lam Research Corporation | Etch profile control |
Also Published As
Publication number | Publication date |
---|---|
WO2009042453A3 (en) | 2009-06-11 |
WO2009042453A2 (en) | 2009-04-02 |
TW200933734A (en) | 2009-08-01 |
US8501627B2 (en) | 2013-08-06 |
CN101809721A (zh) | 2010-08-18 |
KR20100088128A (ko) | 2010-08-06 |
US20110053379A1 (en) | 2011-03-03 |
KR101528947B1 (ko) | 2015-06-15 |
CN101809721B (zh) | 2013-03-06 |
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