TWI455273B - 晶片封裝結構 - Google Patents

晶片封裝結構 Download PDF

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TWI455273B
TWI455273B TW100127738A TW100127738A TWI455273B TW I455273 B TWI455273 B TW I455273B TW 100127738 A TW100127738 A TW 100127738A TW 100127738 A TW100127738 A TW 100127738A TW I455273 B TWI455273 B TW I455273B
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wafer
chip package
package structure
insulating layer
flexible substrate
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TW100127738A
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TW201308562A (zh
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Davide Chen
Chi Chia Huang
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Chipmos Technologies Inc
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Priority to TW100127738A priority Critical patent/TWI455273B/zh
Priority to CN201110308024.XA priority patent/CN102915990B/zh
Priority to US13/481,881 priority patent/US8723316B2/en
Publication of TW201308562A publication Critical patent/TW201308562A/zh
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Description

晶片封裝結構
本發明是有關於一種晶片封裝結構，且特別是有關於一種使用可撓性基板的晶片封裝結構。
隨著半導體技術的改良，使得液晶顯示器具有低的消耗電功率、薄型量輕、解析度高、色彩飽和度高、壽命長等優點，因而廣泛地應用在筆記型電腦或桌上型電腦的液晶螢幕及液晶電視等與生活息息相關之電子產品。其中，顯示器之驅動晶片(integrated circuit,IC)更是液晶顯示器不可或缺的重要元件。
因應液晶顯示裝置驅動晶片各種應用之需求，一般是採用捲帶自動接合(tape automatic bonding，TAB)封裝技術進行晶片封裝，其中又分成薄膜覆晶(Chip On Film,COF)封裝及捲帶承載封裝(Tape Carrier Package,TCP)。
請參考圖1，詳細而言，以捲帶自動接合方式進行晶片封裝的製程，係在完成可撓性基板50上的線路及晶片60上的凸塊62製程之後，將晶片60置於平台10上，且將可撓性基板50置於晶片60上方，並利用熱壓頭20進行加熱及加壓，以進行內引腳52接合(inner lead bonding，ILB)，使晶片60上的凸塊62與可撓性基板50上的內引腳52產生共晶接合而電性連接。在此壓合過程中，可能因可撓性基板50的翹曲彎折而產生邊緣接觸(edge touch)的問題。也就是說，位於晶片60邊緣的靜電防護環(seal ring/guard ring)80接觸到內引腳52，造成漏電或橋接短路等電性失效問題。此外，設置於切割道上的測試墊(test key)可能於晶圓切割完後未被完全移除，而有部分殘留於晶片60邊緣，若測試墊殘餘物翻起形成突刺(burr)30，在可撓性基板50翹曲彎折時殘留於晶片60邊緣的測試墊凸刺30也可能接觸到內引腳52而造成電性短路。
另外，內引腳接合(ILB)製程亦可如圖2所示將可撓性基板50置於平台10上，且利用熱壓頭20將晶片60置於可撓性基板50上方，並進行加熱及加壓，使內引腳52與凸塊62產生共晶接合而電性連接。在此種接合方式之下，若平台10上存在異物12，會造成可撓性基板50翹曲彎折而使內引腳52接觸到靜電防護環80或殘留於晶片60邊緣的測試墊突刺(圖未顯示)，同樣可能產生邊緣接觸(edge touch)的問題，導致漏電或橋接短路等電性失效。
本發明提供一種晶片封裝結構，可避免其晶片與其引腳發生非預期的電性接觸。
本發明提出一種晶片封裝結構，包括可撓性基板、多個引腳、絕緣層及晶片。可撓性基板具有晶片接合區。引腳配置於可撓性基板上。各引腳包括相連的主體部及內接部。內接部延伸至晶片接合區內。主體部位於晶片接合區之外且主體部的厚度大於內接部的厚度。絕緣層配置於引腳之內接部上。晶片具有主動面。主動面上設置有多個凸塊與靜電防護環。靜電防護環鄰近晶片之邊緣。晶片設置於晶片接合區內並透過凸塊對應連接引腳之內接部而與可撓性基板電性連接。晶片與可撓性基板電性連接後，絕緣層適對應靜電防護環。
在本發明之一實施例中，上述之凸塊沿晶片之至少二相對邊緣排列且鄰近至少二相對邊緣，靜電防護環位於凸塊與晶片之至少二相對邊緣之間。
在本發明之一實施例中，上述之絕緣層包含至少二絕緣條，至少二絕緣條分別配置於沿晶片之至少二相對邊緣相鄰排列的引腳之內接部上。
在本發明之一實施例中，上述之晶片封裝結構更包括封裝膠體，設置於晶片與可撓性基板之間，以包覆凸塊與靜電防護環。
在本發明之一實施例中，上述之晶片封裝結構更包括防銲層，防銲層位於晶片接合區之外並局部覆蓋引腳之主體部。
在本發明之一實施例中，上述之主體部與內接部的連接處具有側壁面，絕緣層延伸至並配置於側壁面上。
在本發明之一實施例中，上述之主體部的厚度係內接部的厚度的1.2至2倍。
在本發明之一實施例中，上述之凸塊的厚度大於靜電防護環的厚度與絕緣層的厚度的和。
在本發明之一實施例中，上述之可撓性基板係適用於薄膜覆晶封裝(chip on film package，COF package)或捲帶承載封裝(tape carrier package，TCP package)。
基於上述，本發明的引腳之主體部具有較大的厚度且絕緣層配置於引腳之內接部上，藉以提升引腳的結構強度，降低引腳受力彎折的機率。此外，絕緣層對應於晶片上的靜電防護環而位於引腳與靜電防護環之間，可避免引腳與靜電防護環因可撓性基板的撓曲及引腳的彎折而產生非預期的電性接觸，以降低晶片封裝結構發生短路的機率。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖3為本發明一實施例之晶片封裝結構的局部剖面圖。請參考圖3，本實施例的晶片封裝結構100包括可撓性基板110、多個引腳120(圖3繪示出一個)及晶片140。引腳120配置於可撓性基板110上，且晶片140透過引腳120與可撓性基板110電性連接。本實施例的晶片封裝結構100例如為薄膜覆晶封裝，然本發明不以此為限，可撓性基板110除了適用於薄膜覆晶封裝，亦適用於捲帶承載封裝。
詳細而言，可撓性基板110具有晶片接合區110a，引腳120包括相連的主體部122及內接部124，內接部124即一般所稱之內引腳。引腳120的內接部124延伸至晶片接合區110a內，引腳120的主體部122位於晶片接合區110a之外，且主體部122的厚度大於內接部124的厚度。晶片140具有主動面140a，主動面140a上設置有多個凸塊142(圖3繪示出一個)與靜電防護環144。晶片140設置於晶片接合區110a內並透過凸塊142對應連接引腳120之內接部124而與可撓性基板110電性連接。靜電防護環144鄰近晶片140之邊緣以作為晶片140預防電磁干擾(例如：靜電)之防護措施。晶片封裝結構100更包括絕緣層130，絕緣層130配置於引腳120之內接部124上，當晶片140與可撓性基板110電性連接，絕緣層130適對應於靜電防護環144。
在上述配置方式之下，由於引腳120之主體部122具有較大的厚度，因此可提升引腳120的結構強度，降低引腳120受力彎折的機率。此外，藉由配置絕緣層130於引腳120之內接部124上，使絕緣層130對應於晶片140上的靜電防護環144，晶片140接合至可撓性基板110後，絕緣層130適位於引腳120與靜電防護環144之間，可避免引腳120與靜電防護環144因可撓性基板110的撓曲及引腳120的彎折而產生非預期的電性接觸，以降低晶片封裝結構100發生電性短路的機率。
更詳細而言，在本實施例中，主體部122與內接部124的連接處具有側壁面122a，絕緣層130延伸至並配置於側壁面122a上。圖4為圖3之晶片的仰視示意圖。請參考圖3及圖4，於本實施例中，凸塊142沿晶片140的二相對邊緣140b、140c排列並且鄰近邊緣140b、140c。靜電防護環144位於凸塊142與晶片140之邊緣140b、140c之間，以作為晶片140預防電磁干擾(例如：靜電)之防護措施。於本實施例中，靜電防護環144環繞於晶片140之四邊緣，然而靜電防護環144的範圍和形狀並不以此為限。
在本實施例中，主體部122的厚度例如為內接部124的厚度的1.2至2倍，以有效提升引腳120的結構強度。此外，引腳120之主體部122與晶片140不重疊，且凸塊142的厚度大於靜電防護環144的厚度與絕緣層130的厚度的和，以避免凸塊142與引腳120之內接部124接合不良。
請參考圖3，本實施例的晶片封裝結構100更包括封裝膠體150，封裝膠體150設置於晶片140與可撓性基板110之間，以包覆凸塊142與靜電防護環144。此外，晶片封裝結構100更包括防銲層160，防銲層160位於晶片接合區110a之外並局部覆蓋引腳120之主體部122，以防止引腳120之間不當接觸而造成電性短路。於本實施例中，晶片接合區110a是由防銲層160的開口所定義。
圖5為圖3之可撓性基板的俯視圖。請參考圖5，本實施例的絕緣層130包含至少二絕緣條132，二絕緣條132分別配置於沿晶片140之二相對邊緣140b、140c相鄰排列的這些引腳120之內接部124上，也就是說，絕緣條132是整條連續地覆蓋位於一邊緣140b或140c的引腳120之內接部124上。圖6為本發明另一實施例之可撓性基板的俯視圖。請參考圖6，在本實施例中，絕緣層130’亦可由多個絕緣塊134組成，各絕緣塊134分別配置於各引腳120之內接部124上。
本發明不限制絕緣層130的延伸範圍，以下藉由圖示加以舉例說明。圖7為本發明另一實施例引腳及絕緣層的局部剖面圖。請參考圖7，相較於圖3之絕緣層130從內接部124往主體部122延伸並往上延伸而覆蓋引腳120的側壁面122a，本實施例的絕緣層230從內接部224往主體部222延伸，但並未覆蓋引腳220的側壁面222a。圖8為本發明另一實施例引腳及絕緣層的局部剖面圖。請參考圖8，相較於圖3之絕緣層130從內接部124往主體部122延伸並往上延伸而覆蓋引腳120的側壁面122a，本實施例的絕緣層330從內接部324往主體部322延伸並往上延伸而覆蓋引腳320的側壁面322a，且進一步延伸至主體部322的上表面而覆蓋於防銲層160上。
綜上所述，本發明的引腳之主體部具有較大的厚度，因此可提升引腳的結構強度，降低引腳受力彎折的機率。此外，藉由配置絕緣層於引腳之內接部上，使絕緣層對應於晶片上的靜電防護環，晶片接合至可撓性基板後，絕緣層適位於引腳與靜電防護環之間，可避免引腳與靜電防護環因可撓性基板的撓曲及引腳的彎折而產生非預期的電性接觸，以降低晶片封裝結構發生電性短路的機率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．平台
12．．．異物
20．．．熱壓頭
30．．．突刺
50、110．．．可撓性基板
52．．．內引腳
60、140．．．晶片
62、142．．．凸塊
80、144．．．靜電防護環
100．．．晶片封裝結構
110a．．．晶片接合區
120、220、320．．．引腳
122、222、322．．．主體部
122a、222a、322a．．．側壁面
124、224、324．．．內接部
130、130’、230、330．．．絕緣層
132．．．絕緣條
134．．．絕緣塊
140a．．．主動面
140b、140c．．．邊緣
150．．．封裝膠體
160．．．防銲層
圖1及圖2為習知捲帶式封裝結構的製程示意圖。
圖3為本發明一實施例之晶片封裝結構的局部剖面圖。
圖4為圖3之晶片的仰視示意圖。
圖5為圖3之可撓性基板的俯視圖。
圖6為本發明另一實施例之可撓性基板的俯視圖。
圖7為本發明另一實施例引腳及絕緣層的局部剖面圖。
圖8為本發明另一實施例引腳及絕緣層的局部剖面圖。
100．．．晶片封裝結構
110．．．可撓性基板
110a．．．晶片接合區
120．．．引腳
122．．．主體部
122a．．．側壁面
124．．．內接部
130．．．絕緣層
140．．．晶片
140a．．．主動面
140b．．．邊緣
142．．．凸塊
144．．．靜電防護環
150．．．封裝膠體
160．．．防銲層

Claims (10)

  1. 一種晶片封裝結構，包括：一可撓性基板，具有一晶片接合區；多個引腳，配置於該可撓性基板上，其中各該引腳包括相連的一主體部及一內接部，該內接部延伸至該晶片接合區內，該主體部位於該晶片接合區之外且該主體部的厚度大於該內接部的厚度；一絕緣層，配置於該多個引腳之內接部上，其中該絕緣層的上表面不高於該主體部的表面；以及一晶片，具有一主動面，該主動面上設置有多個凸塊與一靜電防護環，其中該靜電防護環鄰近該晶片之邊緣，該晶片設置於該晶片接合區內並透過該多個凸塊對應連接該多個引腳之內接部而與該可撓性基板電性連接；其中該晶片與該可撓性基板電性連接後，該絕緣層適對應該靜電防護環。
  2. 如申請專利範圍第1項所述之晶片封裝結構，其中該多個凸塊沿該晶片之至少二相對邊緣相鄰排列且鄰近該至少二相對邊緣，該靜電防護環位於該多個凸塊與該晶片之該至少二相對邊緣之間。
  3. 如申請專利範圍第2項所述之晶片封裝結構，其中該絕緣層包含至少二絕緣條，該至少二絕緣條分別配置於沿該晶片之至少二相對邊緣相鄰排列的該多個引腳之內接部上。
  4. 如申請專利範圍第1項所述之晶片封裝結構，其中 該絕緣層包含多個絕緣塊，各該絕緣塊分別配置於各該引腳之內接部上。
  5. 如申請專利範圍第1項所述之晶片封裝結構，更包括一封裝膠體，設置於該晶片與該可撓性基板之間，以包覆該多個凸塊與該靜電防護環。
  6. 如申請專利範圍第1項所述之晶片封裝結構，更包括一防銲層，該防銲層位於該晶片接合區之外並局部覆蓋該多個引腳之主體部。
  7. 如申請專利範圍第1項所述之晶片封裝結構，其中該主體部與該內接部的連接處具有一側壁面，該絕緣層延伸至並配置於該側壁面上。
  8. 如申請專利範圍第1項所述之晶片封裝結構，其中該主體部的厚度係該內接部的厚度的1.2至2倍。
  9. 如申請專利範圍第1項所述之晶片封裝結構，其中該凸塊的厚度大於該靜電防護環的厚度與該絕緣層的厚度的和。
  10. 如申請專利範圍第1項所述之晶片封裝結構，其中該可撓性基板係適用於薄膜覆晶封裝或捲帶承載封裝。
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