CN102915990B - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

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CN102915990B
CN102915990B CN201110308024.XA CN201110308024A CN102915990B CN 102915990 B CN102915990 B CN 102915990B CN 201110308024 A CN201110308024 A CN 201110308024A CN 102915990 B CN102915990 B CN 102915990B
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chip
pin
packaging structure
portion inside
insulating barrier
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CN102915990A (zh
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陈纬铭
黄祺家
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Chipmos Technologies Inc
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Abstract

一种芯片封装结构，包括可挠性基板、多个引脚、绝缘层及芯片。可挠性基板具有芯片接合区。引脚配置于可挠性基板上。各引脚包括相连的主体部及内接部。内接部延伸至芯片接合区内。主体部位于芯片接合区之外且主体部的厚度大于内接部的厚度。绝缘层配置于内接部上。芯片具有主动面，主动面上设置有多个凸块与邻近芯片边缘的静电防护环。芯片设置于芯片接合区内并透过凸块电性连接内接部。绝缘层对应静电防护环。

Description

芯片封装结构
技术领域
本发明是有关于一种芯片封装结构，且特别是有关于一种使用可挠性基板的芯片封装结构。
背景技术
随着半导体技术的改良，使得液晶显示器具有低的消耗电功率、薄型量轻、分辨率高、色彩饱和度高、寿命长等优点，因而广泛地应用在笔记型计算机或桌上型计算机的液晶屏幕及液晶电视等与生活息息相关的电子产品。其中，显示器的驱动芯片(integrated circuit，IC)更是液晶显示器不可或缺的重要组件。
因应液晶显示装置驱动芯片各种应用的需求，一般是采用卷带自动接合(tapeautomatic bonding，TAB)封装技术进行芯片封装，其中又分成薄膜覆晶(Chip OnFilm，COF)封装及卷带承载封装(Tape Carrier Package，TCP)。
请参考图1，详细而言，以卷带自动接合方式进行芯片封装的工艺，是在完成可挠性基板50上的线路及芯片60上的凸块62工艺之后，将芯片60置于平台10上，且将可挠性基板50置于芯片60上方，并利用热压头20进行加热及加压，以进行内引脚52接合(inner lead bonding，ILB)，使芯片60上的凸块62与可挠性基板50上的内引脚52产生共晶接合而电性连接。在此压合过程中，可能因可挠性基板50的翘曲弯折而产生边缘接触(edge touch)的问题。也就是说，位于芯片60边缘的静电防护环(seal ring/guard ring)80接触到内引脚52，造成漏电或桥接短路等电性失效问题。此外，设置于切割道上的测试垫(test key)可能于晶圆切割完后未被完全移除，而有部分残留于芯片60边缘，若测试垫残余物翻起形成突刺(burr)30，在可挠性基板50翘曲弯折时残留于芯片60边缘的测试垫凸刺30也可能接触到内引脚52而造成电性短路。
另外，内引脚接合(ILB)工艺亦可如图2所示将可挠性基板50置于平台10上，且利用热压头20将芯片60置于可挠性基板50上方，并进行加热及加压，使内引脚52与凸块62产生共晶接合而电性连接。在此种接合方式之下，若平台10上存在异物12，会造成可挠性基板50翘曲弯折而使内引脚52接触到静电防护环80或残留于芯片60边缘的测试垫突刺(图未显示)，同样可能产生边缘接触(edgetouch)的问题，导致漏电或桥接短路等电性失效。
发明内容
本发明提供一种芯片封装结构，可避免其芯片与其引脚发生非预期的电性接触。
本发明提出一种芯片封装结构，包括可挠性基板、多个引脚、绝缘层及芯片。可挠性基板具有芯片接合区。引脚配置于可挠性基板上。各引脚包括相连的主体部及内接部。内接部延伸至芯片接合区内。主体部位于芯片接合区之外且主体部的厚度大于内接部的厚度。绝缘层配置于引脚的内接部上。芯片具有主动面。主动面上设置有多个凸块与静电防护环。静电防护环邻近芯片的边缘。芯片设置于芯片接合区内并透过凸块对应连接引脚的内接部而与可挠性基板电性连接。芯片与可挠性基板电性连接后，绝缘层适对应静电防护环。
在本发明的一实施例中，上述的凸块沿芯片的至少二相对边缘排列且邻近至少二相对边缘，静电防护环位于凸块与芯片的至少二相对边缘之间。
在本发明的一实施例中，上述的绝缘层包含至少二绝缘条，至少二绝缘条分别配置于沿芯片的至少二相对边缘相邻排列的引脚的内接部上。
在本发明的一实施例中，上述的芯片封装结构更包括封装胶体，设置于芯片与可挠性基板之间，以包覆凸块与静电防护环。
在本发明的一实施例中，上述的芯片封装结构更包括防焊层，防焊层位于芯片接合区之外并局部覆盖引脚的主体部。
在本发明的一实施例中，上述的主体部与内接部的连接处具有侧壁面，绝缘层延伸至并配置于侧壁面上。
在本发明的一实施例中，上述的主体部的厚度是内接部的厚度的1.2至2倍。
在本发明的一实施例中，上述的凸块的厚度大于静电防护环的厚度与绝缘层的厚度的和。
在本发明的一实施例中，上述的可挠性基板是适用于薄膜覆晶封装(chip onfilm package，COF package)或卷带承载封装(tape carrier package，TCP package)。
基于上述，本发明的引脚的主体部具有较大的厚度且绝缘层配置于引脚的内接部上，藉以提升引脚的结构强度，降低引脚受力弯折的机率。此外，绝缘层对应于芯片上的静电防护环而位于引脚与静电防护环之间，可避免引脚与静电防护环因可挠性基板的挠曲及引脚的弯折而产生非预期的电性接触，以降低芯片封装结构发生短路的机率。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1及图2为现有卷带式封装结构的工艺示意图。
图3为本发明一实施例的芯片封装结构的局部剖面图。
图4为图3的芯片的仰视示意图。
图5为图3的可挠性基板的俯视图。
图6为本发明另一实施例的可挠性基板的俯视图。
图7为本发明另一实施例引脚及绝缘层的局部剖面图。
图8为本发明另一实施例引脚及绝缘层的局部剖面图。
具体实施方式
图3为本发明一实施例的芯片封装结构的局部剖面图。请参考图3，本实施例的芯片封装结构100包括可挠性基板110、多个引脚120(图3绘示出一个)及芯片140。引脚120配置于可挠性基板110上，且芯片140透过引脚120与可挠性基板110电性连接。本实施例的芯片封装结构100例如为薄膜覆晶封装，然本发明不以此为限，可挠性基板110除了适用于薄膜覆晶封装，亦适用于卷带承载封装。
详细而言，可挠性基板110具有芯片接合区110a，引脚120包括相连的主体部122及内接部124，内接部124即一般所称的内引脚。引脚120的内接部124延伸至芯片接合区110a内，引脚120的主体部122位于芯片接合区110a之外，且主体部122的厚度大于内接部124的厚度。芯片140具有主动面140a，主动面140a上设置有多个凸块142(图3绘示出一个)与静电防护环144。芯片140设置于芯片接合区110a内并透过凸块142对应连接引脚120的内接部124而与可挠性基板110电性连接。静电防护环144邻近芯片140的边缘以作为芯片140预防电磁干扰(例如：静电)的防护措施。芯片封装结构100更包括绝缘层130，绝缘层130配置于引脚120的内接部124上，当芯片140与可挠性基板110电性连接，绝缘层130适对应于静电防护环144。
在上述配置方式之下，由于引脚120的主体部122具有较大的厚度，因此可提升引脚120的结构强度，降低引脚120受力弯折的机率。此外，通过配置绝缘层130于引脚120的内接部124上，使绝缘层130对应于芯片140上的静电防护环144，芯片140接合至可挠性基板110后，绝缘层130适位于引脚120与静电防护环144之间，可避免引脚120与静电防护环144因可挠性基板110的挠曲及引脚120的弯折而产生非预期的电性接触，以降低芯片封装结构100发生电性短路的机率。
更详细而言，在本实施例中，主体部122与内接部124的连接处具有侧壁面122a，绝缘层130延伸至并配置于侧壁面122a上。图4为图3的芯片的仰视示意图。请参考图3及图4，于本实施例中，凸块142沿芯片140的二相对边缘140b、140c排列并且邻近边缘140b、140c。静电防护环144位于凸块142与芯片140的边缘140b、140c之间，以作为芯片140预防电磁干扰(例如：静电)的防护措施。于本实施例中，静电防护环144环绕于芯片140的四边缘，然而静电防护环144的范围和形状并不以此为限。
在本实施例中，主体部122的厚度例如为内接部124的厚度的1.2至2倍，以有效提升引脚120的结构强度。此外，引脚120的主体部122与芯片140不重迭，且凸块142的厚度大于静电防护环144的厚度与绝缘层130的厚度的和，以避免凸块142与引脚120的内接部124接合不良。
请参考图3，本实施例的芯片封装结构100更包括封装胶体150，封装胶体150设置于芯片140与可挠性基板110之间，以包覆凸块142与静电防护环144。此外，芯片封装结构100更包括防焊层160，防焊层160位于芯片接合区110a之外并局部覆盖引脚120的主体部122，以防止引脚120之间不当接触而造成电性短路。于本实施例中，芯片接合区110a是由防焊层160的开口所定义。
图5为图3的可挠性基板的俯视图。请参考图5，
本实施例的绝缘层130包含至少二绝缘条132，二绝缘条132分别配置于沿芯片140的二相对边缘140b、140c相邻排列的这些引脚120的内接部124上，也就是说，绝缘条132是整条连续地覆盖位于一边缘140b或140c的引脚120的内接部124上。图6为本发明另一实施例的可挠性基板的俯视图。请参考图6，在本实施例中，绝缘层130’亦可由多个绝缘块134组成，各绝缘块134分别配置于各引脚120的内接部124上。
本发明不限制绝缘层130的延伸范围，以下通过图示加以举例说明。图7为本发明另一实施例引脚及绝缘层的局部剖面图。请参考图7，相较于图3的绝缘层130从内接部124往主体部122延伸并往上延伸而覆盖引脚120的侧壁面122a，本实施例的绝缘层230从内接部224往主体部222延伸，但并未覆盖引脚220的侧壁面222a。图8为本发明另一实施例引脚及绝缘层的局部剖面图。请参考图8，相较于图3的绝缘层130从内接部124往主体部122延伸并往上延伸而覆盖引脚120的侧壁面122a，本实施例的绝缘层330从内接部324往主体部322延伸并往上延伸而覆盖引脚320的侧壁面322a，且进一步延伸至主体部322的上表面而覆盖于防焊层160上。
综上所述，本发明的引脚的主体部具有较大的厚度，因此可提升引脚的结构强度，降低引脚受力弯折的机率。此外，通过配置绝缘层于引脚的内接部上，使绝缘层对应于芯片上的静电防护环，芯片接合至可挠性基板后，绝缘层适位于引脚与静电防护环之间，可避免引脚与静电防护环因可挠性基板的挠曲及引脚的弯折而产生非预期的电性接触，以降低芯片封装结构发生电性短路的机率。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视后附的权利要求所界定者为准。

Claims (10)

1.一种芯片封装结构，包括：
一可挠性基板，具有一芯片接合区；
多个引脚，配置于该可挠性基板上，其中各该引脚包括相连的一主体部及一内接部，该内接部延伸至该芯片接合区内，该主体部位于该芯片接合区之外且该主体部的厚度大于该内接部的厚度；
一绝缘层，配置于所述多个引脚的内接部上，其中该绝缘层的上表面不高于该主体部的表面；以及
一芯片，具有一主动面，该主动面上设置有多个凸块与一静电防护环，其中该静电防护环邻近该芯片的边缘，该芯片设置于该芯片接合区内并透过所述多个凸块对应连接所述多个引脚的内接部而与该可挠性基板电性连接；
其中该芯片与该可挠性基板电性连接后，该绝缘层适对应该静电防护环。
2.如权利要求1所述的芯片封装结构，其特征在于，所述多个凸块沿该芯片的至少二相对边缘相邻排列且邻近该至少二相对边缘，该静电防护环位于所述多个凸块与该芯片的该至少二相对边缘之间。
3.如权利要求2所述的芯片封装结构，其特征在于，该绝缘层包含至少二绝缘条，该至少二绝缘条分别配置于沿该芯片的至少二相对边缘相邻排列的所述多个引脚的内接部上。
4.如权利要求1所述的芯片封装结构，其特征在于，该绝缘层包含多个绝缘块，各该绝缘块分别配置于各该引脚的内接部上。
5.如权利要求1所述的芯片封装结构，其特征在于，还包括一封装胶体，设置于该芯片与该可挠性基板之间，以包覆所述多个凸块与该静电防护环。
6.如权利要求1所述的芯片封装结构，其特征在于，还包括一防焊层，该防焊层位于该芯片接合区之外并局部覆盖所述多个引脚的主体部。
7.如权利要求1所述的芯片封装结构，其特征在于，该主体部与该内接部的连接处具有一侧壁面，该绝缘层延伸至并配置于该侧壁面上。
8.如权利要求1所述的芯片封装结构，其特征在于，该主体部的厚度是该内接部的厚度的1.2至2倍。
9.如权利要求1所述的芯片封装结构，其特征在于，该凸块的厚度大于该静电防护环的厚度与该绝缘层的厚度的和。
10.如权利要求1所述的芯片封装结构，其特征在于，该可挠性基板是适用于薄膜覆晶封装或卷带承载封装。
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