CN102915989B - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

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CN102915989B
CN102915989B CN201110308023.5A CN201110308023A CN102915989B CN 102915989 B CN102915989 B CN 102915989B CN 201110308023 A CN201110308023 A CN 201110308023A CN 102915989 B CN102915989 B CN 102915989B
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chip
pin
projection
bonding area
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CN102915989A (zh
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沈弘哲
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Chipmos Technologies Inc
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Abstract

一种芯片封装结构，包括芯片、可挠性基板、多个第一引脚及多个第二引脚。芯片的主动面设有多个第一凸块、多个第二凸块与静电防护环。第一与第二凸块分别邻近芯片相对的第一与第二边。静电防护环位于第一及第二凸块与第一及第二边之间。芯片设置于可挠性基板的芯片接合区内。芯片的第一与第二边分别对应芯片接合区的相对的第一与第二侧。第一引脚配置于可挠性基板上且从第一侧进入芯片接合区并向第二侧延伸而分别与第二凸块电性连接。第二引脚配置于可挠性基板上且从第二侧进入芯片接合区并向第一侧延伸而分别与第一凸块电性连接。

Description

芯片封装结构
技术领域
本发明是有关于一种芯片封装结构，且特别是有关于一种使用可挠性基板的芯片封装结构。
背景技术
随着半导体技术的改良，使得液晶显示器具有低的消耗电功率、薄型量轻、分辨率高、色彩饱和度高、寿命长等优点，因而广泛地应用在笔记型计算机或桌上型计算机的液晶屏幕及液晶电视等与生活息息相关的电子产品。其中，显示器的驱动芯片(integrated circuit，IC)更是液晶显示器不可或缺的重要组件。
因应液晶显示装置驱动芯片各种应用的需求，一般是采用卷带自动接合(tapeautomatic bonding，TAB)封装技术进行芯片封装，其中又分成薄膜覆晶(Chip OnFilm，COF)封装及卷带承载封装(Tape Carrier Package，TCP)。
请参考图1，详细而言，以卷带自动接合方式进行芯片封装的工艺，是在完成可挠性基板50上的线路及芯片60上的凸块62工艺之后进行内引脚52接合(innerlead bonding，ILB)，使芯片60上的凸块62与可挠性基板50上的内引脚52产生共晶接合而电性连接。现行可挠性基板50上包含内引脚52的线路一般是用铜箔形成，而内引脚52上另形成有锡层，以帮助凸块62与内引脚52共晶接合时能确实连接。然而，在使用热压方式进行共晶接合时，内引脚52上的镀锡若过多则可能会产生溢锡70，因内引脚52与凸块62接合之处很接近芯片60边缘，则溢锡70容易沿内引脚52延伸而接触到配置于芯片60边缘的静电防护环(seal ring/guardring)80，造成漏电或桥接短路等电性失效。此外，如图2所示，即使未发生上述溢锡现象，仍可能因可挠性基板50的翘曲弯折而使静电防护环80接触到内引脚52(edge touch)，同样会造成漏电或桥接短路等电性失效。
发明内容
本发明提供一种芯片封装结构，可降低芯片边缘的静电防护环因接触内引脚而电性失效的机率。
本发明提出一种芯片封装结构，包括芯片、可挠性基板、多个第一引脚及多个第二引脚。芯片具有主动面。主动面上设置有多个第一凸块、多个第二凸块与静电防护环。第一凸块邻近芯片的第一边。第二凸块邻近芯片相对第一边的第二边。静电防护环位于第一凸块与第一边之间以及第二凸块与第二边之间。可挠性基板具有芯片接合区。芯片接合区具有相对的第一侧与第二侧。芯片设置于芯片接合区内，且芯片的第一边与第二边分别对应芯片接合区的第一侧与第二侧。第一引脚配置于可挠性基板上，且从第一侧进入芯片接合区内并向第二侧延伸而分别与第二凸块电性连接。第二引脚配置于可挠性基板上，且从第二侧进入芯片接合区内并向第一侧延伸而分别与第一凸块电性连接。
在本发明的一实施例中，上述的芯片封装结构更包括封装胶体，设置于芯片与可挠性基板之间，以包覆第一凸块、第二凸块与静电防护环。
在本发明的一实施例中，上述的第一引脚及第二引脚具有外接端及内接端，外接端远离芯片接合区，内接端终止于芯片接合区内并与相应的凸块连接。
在本发明的一实施例中，上述的第一引脚与第二引脚交错排列。
在本发明的一实施例中，上述的芯片封装结构更包括防焊层，防焊层位于芯片接合区之外并局部覆盖第一引脚及第二引脚。
在本发明的一实施例中，上述的可挠性基板适用于薄膜覆晶封装(chip on filmpackage，COF package)或卷带承载封装(tape carrier package，TCP package)。
基于上述，本发明的第一引脚从芯片接合区的第一侧进入芯片接合区内，并往芯片接合区的第二侧延伸而电性连接邻近第二侧的第二凸块，且第二引脚从芯片接合区的第二侧进入芯片接合区内，并往芯片接合区的第一侧延伸而电性连接邻近第一侧的第一凸块。通过将引脚延伸经过芯片接合区至另一侧而与邻近该侧的凸块接合，使引脚不会横越接合凸块该侧的芯片边缘，当引脚与凸块接合时产生溢锡，溢锡不会沿引脚延伸而接触到配置于芯片边缘的静电防护环，因此可避免引脚与静电防护环透过溢锡产生桥接而有漏电或短路等电性失效情况发生。再者，因为引脚延伸经过芯片接合区内，使可挠性基板强度增加，可防止可挠性基板产生下陷、翘曲等现象，进而避免芯片接合时因可挠性基板翘曲弯折而造成芯片边缘接触引脚(edge touch)的问题。引脚分布于芯片接合区内，也可藉金属的高导热效率提升芯片封装结构的散热效率。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1及图2为现有卷带式封装结构的示意图。
图3为本发明一实施例的芯片封装结构的俯视图。
图4为图3的芯片封装结构沿A-A’线的局部剖面图。
图5为图3的芯片封装结构沿B-B’线的局部剖面图。
图6为图3的芯片封装结构沿C-C’线的局部剖面图。
图7为图3的芯片封装结构沿D-D’线的局部剖面图。
具体实施方式
图3为本发明一实施例的芯片封装结构的俯视图。图4为图3的芯片封装结构沿A-A’线的局部剖面图。图5为图3的芯片封装结构沿B-B’线的局部剖面图。请参考图3至图5，本实施例的芯片封装结构100包括芯片110、可挠性基板120、多个第一引脚130及多个第二引脚140。芯片110具有主动面110a，主动面110a上设置有多个第一凸块112、多个第二凸块114与静电防护环116。第一凸块112邻近芯片110的第一边110b，第二凸块114邻近相对第一边110b的第二边110c。静电防护环116位于第一凸块112与第一边110b之间以及第二凸块114与第二边110c之间。于本实施例中，静电防护环116环绕于芯片四周与第一凸块112及第二凸块114之间，然而静电防护环116的范围和形状并不以此为限。以图3的视角而言，部分第一引脚130、部分第二引脚140、第一凸块112、第二凸块114及静电防护环116被芯片110所遮蔽而以虚线绘示。
可挠性基板120具有芯片接合区122，芯片接合区122具有相对的第一侧122a与第二侧122b。芯片110设置于芯片接合区122内，且芯片110的第一边110b与第二边110c分别对应芯片接合区的第一侧122a与第二侧122b。第一引脚130配置于可挠性基板120上，且从第一侧122a进入芯片接合区122内并向第二侧122b延伸而分别与第二凸块114电性连接。第二引脚140配置于可挠性基板120上，且从第二侧122b进入芯片接合区122内并向第一侧122a延伸而分别与第一凸块112电性连接。藉此，第一引脚130与第二凸块114接合时并不会横跨经过第二凸块114邻近的芯片110的第二边110c，换言之，第一引脚130会终止于第二边110c之前，相同的，第二引脚140与第一凸块112接合时并不会横跨经过第一凸块112邻近的芯片110的第一边110b，即第二引脚140会终止于第一边110b之前，因此引脚130、140与凸块112、114透过热压工艺共晶接合时若产生溢锡，溢锡不会沿引脚130、140延伸而接触到配置于芯片110边缘的静电防护环116，可避免第一引脚130及第二引脚140透过溢锡接触到静电防护环116，进而造成漏电或短路等电性失效问题发生。
芯片封装结构100更包括防焊层160，防焊层160位于芯片接合区122之外并局部覆盖第一引脚130及第二引脚140，以防止引脚130、140之间不当接触而造成电性短路。本实施例的芯片封装结构100例如为薄膜覆晶封装，芯片接合区122是由防焊层160的开口所定义，然本发明不以此为限，可挠性基板120除了适用于薄膜覆晶封装，亦适用于卷带承载封装，于卷带承载封装，芯片接合区122则由组件孔所定义。可挠性基板110的材料可选自聚酰亚胺(polyimide，PI)、聚酯类化合物(polyethylene terephthalate，PET)或其它合适的可挠性材料。
请参考图3，第一引脚130及第二引脚140远离芯片接合区122的部分可视为其外接端，外接端是作为芯片封装结构100后续接合外部组件(例如：玻璃面板、印刷电路板)之用。而第一引脚130及第二引脚140终止于芯片接合区122内并与相应的凸块(112或114)连接的部分可视为其内接端。通过热压或超音波接合工艺，可使第一引脚130及第二引脚140的内接端与相应的凸块112、114共晶接合。由于第一引脚130及第二引脚140延伸经过芯片接合区122，使得可挠性基板120强度增加，因此可防止可挠性基板120产生下陷、翘曲等现象，进而避免芯片110接合时因可挠性基板120翘曲弯折而造成芯片110边缘接触引脚130、140的问题。再者，藉所述延伸分布于芯片接合区122内的引脚130、140的金属高导热效率可帮助消散芯片110运作时产生的热，进而提升芯片封装结构100的散热效率。在本实施例中，第一引脚130与第二引脚140交错排列，以使整体结构较为对称，然本发明不以此为限，在其它实施例中，第一引脚130与第二引脚140亦可以其它适当方式排列。
请参考图4及图5，本实施例的芯片封装结构100更包括封装胶体150，封装胶体150设置于芯片110与可挠性基板120之间，以包覆第一凸块112、第二凸块114与静电防护环116，藉以防止湿气及污染物进入，进而保护凸块112、114与引脚130、140的电性接点。图6为图3的芯片封装结构沿C-C’线的局部剖面图。图7为图3的芯片封装结构沿D-D’线的局部剖面图。如图6所示，第二引脚140延伸经过芯片110的第二边110c所在区域，而在此区域未有凸块与第二引脚140接合，因此不会产生溢锡现象，而可避免静电防护环116透过溢锡而与引脚桥接导致短路。同样地，如图7所示，第一引脚130延伸经过芯片110的第一边110b所在区域，而在此区域未有凸块与第一引脚130接合，因此不会产生溢锡现象，而可避免静电防护环116透过溢锡而与引脚桥接导致短路。
综上所述，本发明的第一引脚从芯片接合区的第一侧进入芯片接合区内，并往芯片接合区的第二侧延伸而电性连接邻近第二侧的第二凸块，且第二引脚从芯片接合区的第二侧进入芯片接合区内，并往芯片接合区的第一侧延伸而电性连接邻近第一侧的第一凸块。通过将引脚延伸经过芯片接合区至另一侧而与邻近该侧的凸块接合，使引脚不会横越接合凸块该侧的芯片边缘，当引脚与凸块接合时产生溢锡，溢锡不会沿引脚延伸而接触到配置于芯片边缘的静电防护环，因此可避免引脚与静电防护环透过溢锡产生桥接而有漏电或短路等电性失效情况发生。再者，因为引脚延伸经过芯片接合区内，使可挠性基板强度增加，可防止可挠性基板产生下陷、翘曲等现象，进而避免芯片接合时因可挠性基板翘曲弯折而造成芯片边缘接触引脚(edge touch)的问题。引脚分布于芯片接合区内，也可藉金属的高导热效率提升芯片封装结构的散热效率。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视后附的权利要求所界定者为准。

Claims (6)

1.一种芯片封装结构，包括：
一芯片，具有一主动面，该主动面上设置有多个第一凸块、多个第二凸块与一静电防护环，所述多个第一凸块邻近该芯片的一第一边，所述多个第二凸块邻近该芯片相对该第一边的一第二边，该静电防护环环绕于该芯片四周，并且位于所述多个第一凸块与该第一边之间以及所述多个第二凸块与该第二边之间；
一可挠性基板，具有一芯片接合区，其中该芯片接合区具有相对的一第一侧与一第二侧，该芯片设置于该芯片接合区内，且该芯片的该第一边与该第二边分别对应该芯片接合区的该第一侧与该第二侧；
多个第一引脚，配置于该可挠性基板上，且从该第一侧进入该芯片接合区内并向该第二侧延伸而分别与所述多个第二凸块电性连接；以及
多个第二引脚，配置于该可挠性基板上，且从该第二侧进入该芯片接合区内并向该第一侧延伸而分别与所述多个第一凸块电性连接。
2.如权利要求1所述的芯片封装结构，其特征在于，还包括一封装胶体，设置于该芯片与该可挠性基板之间，以包覆所述多个第一凸块、所述多个第二凸块与该静电防护环。
3.如权利要求1所述的芯片封装结构，其特征在于，各所述多个第一引脚及所述多个第二引脚具有一外接端及一内接端，该外接端远离该芯片接合区，该内接端终止于该芯片接合区内并与相应的该凸块连接。
4.如权利要求1所述的芯片封装结构，其特征在于，所述多个第一引脚与所述多个第二引脚交错排列。
5.如权利要求1所述的芯片封装结构，其特征在于，还包括一防焊层，该防焊层位于该芯片接合区之外并局部覆盖所述多个第一引脚及所述多个第二引脚。
6.如权利要求1所述的芯片封装结构，其特征在于，该可挠性基板是适用于薄膜覆晶封装或卷带承载封装。
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