TWI452630B - A method for forming an amorphous carbon-nitrogen film, an amorphous carbon-nitrogen film, a multilayer photoresist film, a method of manufacturing a semiconductor device, and a memory medium having a memory control program - Google Patents

A method for forming an amorphous carbon-nitrogen film, an amorphous carbon-nitrogen film, a multilayer photoresist film, a method of manufacturing a semiconductor device, and a memory medium having a memory control program Download PDF

Info

Publication number
TWI452630B
TWI452630B TW098128747A TW98128747A TWI452630B TW I452630 B TWI452630 B TW I452630B TW 098128747 A TW098128747 A TW 098128747A TW 98128747 A TW98128747 A TW 98128747A TW I452630 B TWI452630 B TW I452630B
Authority
TW
Taiwan
Prior art keywords
film
amorphous carbon
gas
nitride film
carbon nitride
Prior art date
Application number
TW098128747A
Other languages
English (en)
Other versions
TW201021121A (en
Inventor
Hiraku Ishikawa
Eiichi Nishimura
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW201021121A publication Critical patent/TW201021121A/zh
Application granted granted Critical
Publication of TWI452630B publication Critical patent/TWI452630B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/26Deposition of carbon only
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34Nitrides
    • C23C16/347Carbon nitride
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C23C16/509Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
    • C23C16/5096Flat-bed apparatus
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/09Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/3146Carbon layers, e.g. diamond-like layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/318Inorganic layers composed of nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Structural Engineering (AREA)
  • Architecture (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)
  • Materials For Photolithography (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Description

非晶質碳氮膜之形成方法,非晶質碳氮膜、多層光阻膜、半導體裝置之製造方法及記憶有控制程式之記憶媒體
本發明係關於用於半導體裝置之非晶質碳氮膜的形成方法,非晶質碳氮膜、多層光阻膜、半導體裝置的製造方法及記憶有控制程式的記憶媒體。
於半導體元件之製造過程中,係利用光微影製程技術並以形成有圖型之光阻作為蝕刻遮罩來進行電漿蝕刻,藉以將電路圖型轉印至蝕刻對象膜。利用光微影製程來將圖型投影至光阻時,CD(Critical dimention;關鍵尺寸)45nm的世代係使用配合圖型微細化之ArF光阻,且ArF光阻之曝光係使用波長為193nm之ArF雷射光源。
然而,ArF光阻具有電漿耐受性低的特性。因此,已被提出一種在ArF光阻下層積SiO2 膜及電漿耐受性高之光阻膜,並利用該多層光阻膜來進行圖型化之技術。
另外,亦已被提出一種將取代SiO2 膜或作為反射防止層,並藉由利用碳化氫氣體及惰性氣體之CVD(Chemical Vapor Deposition;化學氣相沉積法)處理所形成的非晶質碳膜應用在多層光阻膜的技術(譬如,參照專利文獻日本特開第2002-12972號公報)。
又,近年來,被提出一種在部分的步驟中不使用光微影製程技術之圖型化技術。具體來說,譬如,在ArF光阻膜下之SiO2 膜、SiO2 膜下層積非晶質碳膜以構成多層光阻膜後,對多層光阻膜進行以下的圖型化步驟。亦即,首先,將ArF光阻膜圖型化,利用經圖型化後之ArF光阻膜來蝕刻SiO2 膜。接下來,利用經圖型化後之SiO2 膜來蝕刻非晶質碳膜。其結果為,ArF光阻膜圖型化步驟以外的步驟不使用光微影製程技術即可將形成於ArF光阻膜之圖型轉印至非晶質碳膜。
然而,利用光微影製程技術來將ArF光阻膜圖型化時,不單是入射光,ArF光阻膜亦會因在ArF光阻膜下層的反射光而感光。其結果為,即使藉由入射光正確地將期望的圖型投影在ArF光阻膜上,卻會被未受控制的反射光感光而使得投影到ArF光阻膜圖型的交界部分變得模糊,而妨害到圖型的高精確度。
因此,為解決上述課題,本發明提出一種形成於光阻膜下,且蝕刻耐受性佳,並且可在使光阻膜曝光時降低照射光的反射率之非晶質碳膜。
為解決上述課題,本發明人經過多方實驗後,得到以下(1)~(4)項的結果。
(1)非晶質碳膜中碳原子的含有率愈高,則愈可提高蝕刻耐受性。
(2)為提高碳原子含有率,必須降低氫原子含有率。
(3)藉由在CVD法中,以分子中不含氫原子之一氧化碳取代碳化氫氣體來作為供給碳之氣體,可產生氫原子含有率極低之非晶質碳膜。
(4)藉由在氫原子含有率極低之非晶質碳膜上,再進一步地植入氮氣,可使光阻膜曝光時,降低照射光在非晶質碳膜發生反射的機率。
從該觀點來看,本發明的其中一個實施樣態係提供一種非晶質碳氮膜的形成方法,其包含:將被處理體設置於處理容器內之步驟;將含有一氧化碳氣體及氮氣的處理氣體供給至該處理容器內之步驟;以及將該處理容器內的一氧化碳氣體及氮氣分解以在被處理體上形成非晶質碳氮膜之步驟。
藉此,可形成一種蝕刻耐受性佳,且在光阻膜曝光時,可降低照射光的反射率之非晶質碳氮膜。藉此,利用光微影製程技術來形成圖型時,可將光阻膜正確地進行圖型化。又,藉由高蝕刻耐受性,即使在進行之後的蝕刻步驟時,亦可在下層膜形成良好的圖型,且蝕刻對象膜的圖型不會產生變形,而可達成將圖型正確地轉印。
該非晶質碳氮膜中的氮原子含有率可為同膜中所含有碳原子的10%以下。
該非晶質碳氮膜可藉由電漿CVD裝置而形成於被處理體上。
該電漿CVD裝置係於該處理容器內設置有上電極及下電極之平行平板型電漿CVD裝置,並且在被處理體設置於該下電極上的狀態下,至少對該上電極施加高頻電力以由該處理氣體來產生電漿。並且,亦可對下電極施加用以形成偏壓之高頻電力。此時,該上電極可為碳電極。處理氣體可包含惰性氣體。
又,為解決上述課題,本發明其他的實施樣態提供一種非晶質碳氮膜,其係利用含有一氧化碳氣體及氮氣之處理氣體並藉由電漿CVD法而形成於被處理體上。
又,為解決上述課題,本發明其他的實施樣態提供一種多層光阻膜,其係藉由將含有一氧化碳氣體及氮氣之處理氣體供給至處理容器內並將該處理容器內的一氧化碳氣體及氮氣分解而具有:形成於蝕刻對象膜上之非晶質碳氮膜;形成於該非晶質碳氮膜上之矽系薄膜;以及形成於該矽系薄膜上之光阻膜。
又,為解決上述課題,本發明其他的實施樣態提供一種半導體裝置之製造方法,其包含:於被處理體上形成蝕刻對象膜之步驟;將含有一氧化碳氣體及氮氣的處理氣體供給至處理容器內之步驟;將該處理容器內的一氧化碳氣體及氮氣分解以在被處理體上形成非晶質碳氮膜之步驟;於該非晶質碳氮膜上形成矽系薄膜之步驟;於該矽系薄膜上形成光阻膜之步驟;將該光阻膜進行圖型化之步驟;以該光阻膜作為蝕刻遮罩來蝕刻該矽系薄膜之步驟;以該矽系薄膜作為蝕刻遮罩來蝕刻該非晶質碳氮膜之步驟;以及以該非晶質碳氮膜作為蝕刻遮罩來蝕刻該蝕刻對象膜之步驟。
此時,亦可利用波長為193nm的光線來將作為該光阻膜之ArF光阻膜進行圖型化。
又,為解決上述課題,本發明其他的實施樣態係提供一種記憶有在電腦上作動的控制程式之電腦可讀取記憶媒體,其中該控制程式係實行上述方法以使該電腦可控制用以形成非晶質碳氮膜的成膜裝置。
又,為解決上述課題,本發明其他的實施樣態提供一種非晶質碳氮膜的形成方法,其係包含:將被處理體設置於處理容器內之步驟;將只由碳原子與氧原子組成的氣體及氮氣供給至該處理容器內之步驟;以及於該處理容器內利用電漿在被處理體上形成非晶質碳氮膜之步驟。
如以上所說明地,本發明可形成蝕刻耐受性佳,且可在光阻膜曝光時降低照射光的反射率之非晶質碳膜。
以下參照所添附的圖式,詳細說明本發明其中一個實施形態。另外,在以下的說明及添附圖式中,對具有同樣的結構及功能之構成要素,則賦予相同的符號而省略重複說明。又,本說明書中之1mTorr為(10-3 ×101325/760)Pa,1sccm為(10-6 /60)m3 /sec。
首先,以平行平板型電漿CVD裝置為例,說明可應用於本發明一實施形態之非晶質碳氮膜的形成方法之成膜處理。圖1係以模組的方式來表示平行平板型電漿CVD裝置之剖面圖。
(電漿CVD裝置的結構)
電漿CVD裝置10係具有圓筒狀處理容器100。處理容器100為接地的狀態。處理容器100內設置有載置晶圓W之晶座105。晶座105係藉由支承體110所支承。晶座105的載置面附近埋設有下電極115,其下方埋設有加熱器120。下電極115係透過整合器125連接有高頻電源130。依需要,從高頻電源130輸出用以形成偏壓之高頻電力來施加到下電極115。加熱器120連接有加熱器電源135,並依需要,從加熱器電源135施加交流電壓以將晶圓W調整至期望的溫度。晶座上方的外緣部設置有固定環140以將晶圓W固定。
處理容器100在頂部具有圓筒狀的開口,其開口係透過絕緣體145嵌入有圓筒狀沖淋器150。沖淋器150內設置有可使氣體擴散之緩衝區域150a。由氣體供給源155所供給之期望的氣體係經由氣體通路L由氣體導入口160導入沖淋器150內,並經過緩衝區域150a從數個氣體噴出口165供給至處理容器內。所期望的氣體係含有一氧化碳氣體、氬氣及氮氣。沖淋器150係透過整合器170連接有高頻電源175。藉此,沖淋器150亦可被作為上電極。具體來說,藉由從高頻電源175輸出用以產生電漿之高頻電力並施加到上電極(沖淋器150),上電極及下電極間會因電場產生而發生放電,藉此被供給至處理容器內的氣體會被激發而產生電漿。
處理容器的底壁設置有排氣管180,而排氣管180連結有具真空幫浦(未在圖式中表示)之排氣裝置185。排氣裝置185係藉由使其作動來將處理容器100的內部減壓至期望的真空度。處理容器100的壁面係設置有將晶圓W搬入/搬出之搬入出口190,以及使搬入出口190開閉之閘閥195。
以上述方式構成的電漿CVD裝置10係藉由控制裝置200而被加以控制。控制裝置200具有CPU200a、ROM200b、RAM200C及界面200d。CPU200a、ROM200b、RAM200C及界面200d係藉由匯流排200e而分別連接。
ROM200b係記憶有具有非晶質碳氮膜的形成方法之控制程式(指令)或各種程式。RAM200C儲存有用以形成非晶質碳氮膜的各種資訊。控制裝置200係依照控制程式(指令)的步驟順序,透過界面200d將控制訊號傳送至用以形成偏壓之高頻電源130、加熱器電源135、氣體供給源155、用以激發電漿之高頻電源175及排氣裝置185,並藉由該控制訊號來使各個機器在所訂定的時間作動。像這樣地,藉由使CPU200a實行儲存在機構區域的資訊及控制程式,而可在晶圓W上形成期望的非晶質碳氮膜。
界面200d係連接有作業員可操作的PC或顯示器(皆未在圖式中表示),而控制裝置200係將作業員的指示反應至電漿CVD裝置10。另外,控制程式亦可被記憶在硬碟或EEPROM、DVD等記憶體,或透過網路來傳送。
(非晶質碳氮膜的形成方法)
接下來,詳細說明利用電漿CVD裝置10來形成本實施形態之非晶質碳氮膜的方法。
首先,將用以形成非晶質碳氮膜之晶圓W載置在晶座上。又,由氣體供給源155向處理容器內供給Ar氣體等惰性氣體以作為電漿激發氣體。並且排氣裝置185開始作動,將處理容器內排氣以將處理容器內維持在期望的減壓狀態。由高頻電源175向沖淋器150施加高頻電力,藉以將處理容器內的氣體電漿化。此狀態下,由氣體供給源155供給含有一氧化碳氣體及氮氣的氣體。譬如,將一氧化碳氣體CO、氮氣N2 及氬氣Ar的混合氣體導入處理容器內。另外,也可不供給Ar氣、He氣、Ne氣等惰性氣體,但為了維持均勻的電漿,較佳地係和一氧化碳氣體及氮氣一起供給。
其結果為,如圖2所示,一氧化碳氣體CO被電漿激發分解成碳C與氧自由基O*(1-1:CO→C+O*),而使得產生的碳原子C堆積。碳原子C的一部分在和從氮氣分解的氮原子N結合的狀態下(1-2:C+N→CN),會混入碳原子C的堆積物中。像這樣地使碳中混入有氮的狀態下來形成非晶質碳氮膜。
另外,較佳地係以沖淋器150來作為碳電極。其原因為,如上所述,一氧化碳氣體CO被分解時,會產生氧自由基O*,但藉由以沖淋器150來作為碳電極,該氧自由基O*會被使用於一氧化碳的生成反應(2:O*+C→CO),且產生的一氧化碳CO會被使用於產生上述非晶質碳氮膜。其結果為,可提高非晶質碳氮膜的成膜速度。另外,氧自由基O*的一部分會在反應室內被使用於二氧化碳的生成反應(3:O*+CO→CO2 ),因上述而產生的二氧化碳CO2 則從排氣管180被排出去。
成膜中,較佳地係依需要加熱加熱器以調整晶圓W的溫度。譬如,使晶圓W的溫度為350℃以下,較佳地係調整為150~250℃。又,電漿CVD裝置10不限於平行平板型(容量結合型),亦可為誘導結合型的電漿處理裝置、使用微波來產生電漿之電漿處理裝置或遠隔式電漿。特別是,使用微波之電漿處理裝置可產生電子密度Ne高且電子溫度Te低的電漿。因此,可將步驟中的溫度維持在低溫,而較適於包含Cu配線之後段製程。
又,亦可依需要,由高頻電源130向下電極115施加用以形成偏壓之高頻電力以將電漿中的N離子吸引至晶座側。藉此,可在非晶質碳氮膜中確實地混入N離子。此舉可如後所述地降低非晶質碳氮膜的反射率、使非晶質碳氮膜更細緻,並可在之後的步驟中達成對蝕刻對象膜(被蝕刻膜)進行蝕刻時的高選擇比。
(含有非晶質碳氮膜之多層膜的層積構造)
接下來參照圖3,針對用以製造半導體裝置之非晶質碳氮膜的多層膜的層積構造詳細說明於下。在晶圓W上依序層積SiC膜305、SiOC膜(Low-k膜)310、SiC膜315、SiO2 膜320及SiN膜325來作為蝕刻對象膜。
在蝕刻對象膜上依序層積非晶質碳氮膜330、氧化矽膜335(SiO2 )、反射防止膜340(DARC(登錄商標):dielectric anti-reflective coating)及ArF光阻膜345。ArF光阻膜345為光阻膜的一例。氧化矽膜335為矽系薄膜的一例。反射防止膜340可由氧化矽膜或經氮化後之氧化矽膜來形成。以上的層積構造在進行後述半導體裝置的製造方法時,ArF光阻膜345、反射防止膜340、氧化矽膜335、非晶質碳氮膜330可具有多層光阻膜的功能。另外,雖多層光阻膜係包含反射防止膜340較佳,但不包含亦可。
關於蝕刻對象膜的膜厚,SiC膜305可為30nm,SiOC膜(Low-k膜)310可為150nm,SiC膜315可為30nm,SiO2 膜320可為150nm,SiN膜325可為70nm。關於多層光阻膜的膜厚,非晶質碳氮膜330的厚度可為100-800nm(譬如280nm),氧化矽膜335的厚度可為10~100nm(譬如50nm),反射防止膜340(DARC)的厚度可為30-100nm(譬如70nm),ArF光阻膜345的厚度可為200nm以下(譬如180nm)。另外,亦可用SiOC、SiON、SiCN、SiCNH等其他的矽系薄膜來取代氧化矽膜335。
(半導體裝置之製造方法)
接下來,針對可應用於上述層積構造的多層膜之半導體裝置的製造方法,參照圖4~圖8詳細說明。
圖4係利用光微影製程來將ArF光阻膜圖型化之示意圖。圖5係顯示非晶質碳膜及非晶質碳氮膜反射率的測定值之圖。圖6~圖8係利用蝕刻來將多層膜圖型化之示意圖。
(利用光微影製程來進行圖型化)
首先說明如何利用光微影製程來將ArF光阻膜進行圖型化。如圖4上方之曝光步驟所示地,ArF光阻膜345係藉由利用波長193nm之ArF準分子雷射來使ArF光阻膜345感光,以投影未在圖式中表示的遮罩圖型。圖4中,係將投影圖型一部份的圖型交界部分以B來顯示。ArF光阻膜345的感光部分係藉由如圖4下方之顯影步驟中所示地被除去,藉以完成ArF光阻膜345之圖型化步驟。
該光微影製程之圖型化過程中,雷射光會透過ArF光阻膜345的下層。此時,藉由反射防止膜340來抑制朝ArF光阻膜345反射的光線。然而,透過反射防止膜340的光線,亦有再被更下層的膜反射的情況發生。在該情況下,該反射光會使ArF光阻膜345感光。其結果為,即使藉由入射光正確地將圖型B清楚地投影在ArF光阻膜345,卻會因未被控制的反射光而使得ArF光阻膜345產生不必要的感光,讓投影在ArF光阻膜345的圖型交界部分B變得模糊而妨害正確圖型化之進行。因此,本實施形態係利用以下說明的非晶質碳氮膜330來抑制反射的發生。
(非晶質碳氮膜的反射率)
本實施形態之非晶質碳氮膜330係在非晶質碳混入有氮原子。發明人經過多方研究的結果,發現如圖5所示,193nm光線在非晶質碳氮膜330發生反射的反射率會因所添加N原子的量而不同。
為進行圖5的實験,發明人首先利用電漿CVD裝置10來形成非晶質碳氮膜。具體來說,根據從控制裝置200來的指示訊號,電漿CVD裝置10的各組件會被下述方式控制。亦即,將晶圓載置後,藉由從氣體供給源155透過氣體通路L及沖淋器150來將Ar氣體供給至處理容器內,並藉由排氣裝置18來將處理容器內排氣,以將處理容器內維持在20mTorr的減壓狀態。又,使上壁、下壁、晶座105的溫度分別為60℃、50℃、40℃方式來調整處理容器內的溫度。由高頻電源175對沖淋器(上電極)150施加4.0W/cm2 之高頻電力。未施加用以形成偏壓的高頻電力。沖淋器150與晶座105間的間隙為30cm。處理容器內的氣氛安定後,由氣體供給源155供給一氧化碳(CO)氣體、氬(Ar)氣體及氮(N2 )氣體之混合氣體。
當CO/Ar/N2 的氣體流量比為18:1:0時,未添加氮之非晶質碳膜(稱為膜1)的C原子含有率為96.8(Atomic%)。像這樣地,在未添加氮之非晶質碳膜上照射193nm之雷射光時,相對於入射光之反射光的比例,亦即,反射率為「4.42」。
另一方面,當CO/Ar/N2 的氣體流量比為17:1:1時,非晶質碳氮膜330(稱為膜2)的N原子及C原子含有率分別為6.7、88.2(Atomic%)。此表示相對於C原子,非晶質碳氮膜中大約有含有7.6%的N原子。此時,在非晶質碳氮膜330上照射193nm之雷射光時,反射率減少至「2.16」。
再者,當CO/Ar/N2 的氣體流量比為17:1:2時,非晶質碳氮膜330(稱為膜3)的N原子及C原子含有率分別為10.0、83.2(Atomic%)。此表示相對於C原子,非晶質碳氮膜中大約含有12%的N原子。此時,在非晶質碳氮膜330上照射193nm之雷射光時,反射率增加至「4.20」。
由上述實驗,發明人得知在非晶質碳氮膜中添加的N原子為C原子的大約10%以下時,193nm的雷射光幾乎不會在ArF光阻膜345側發生反射,而可實施光微影製程步驟。藉此,發明人可利用N原子的含有率相對於C原子為10%以下之非晶質碳氮膜330,以在ArF光阻膜345正確地形成圖型。
(利用蝕刻來進行圖型化)
接下來說明藉由蝕刻來將形成於ArF光阻膜345之圖型轉印至下層膜的步驟。以圖3所示之ArF光阻膜345作為蝕刻遮罩,並利用電漿CVD裝置10以電漿來將反射防止膜340及氧化矽膜335蝕刻。其結果如圖6所示,ArF光阻膜345的圖型會轉印在氧化矽膜335上。由於ArF光阻膜345的蝕刻耐受性低,因此本步驟中ArF光阻膜345會消失。又,反射防止膜340亦會被蝕刻而變薄。
接下來,以圖6所示之氧化矽膜335作為蝕刻遮罩,並利用電漿CVD裝置10以電漿來將非晶質碳氮膜330蝕刻。其結果如圖7所示,ArF光阻膜345的圖型會轉印在非晶質碳氮膜330。如後所述,非晶質碳氮膜330具有充分的電漿耐受性。因此,非晶質碳氮膜330在本步驟中,可在維持良好形狀的狀態下被蝕刻。其結果為,可正確地將ArF光阻膜345的圖型轉印至非晶質碳氮膜330。
接下來,以圖7所示之非晶質碳氮膜330作為蝕刻遮罩,並利用電漿CVD裝置10,依SiN膜325、SiO2 膜320、SiC膜315、SiOC膜(Low-k膜)310、SiC膜305的順序來對蝕刻對象膜進行蝕刻。如上所述地,由於非晶質碳氮膜330的電漿耐受性(蝕刻耐受性)高,因此在蝕刻中,相對於蝕刻對象膜具有高的選擇比。其結果為,非晶質碳氮膜330在SiC膜305的蝕刻結束前,可作為蝕刻遮罩充分地殘留下來,且蝕刻對象膜的圖型不會產生變形而可正確地將圖型轉印。另外,蝕刻結束後,利用O2 系氣體來將殘留的非晶質碳氮膜330灰化,藉此,如圖8所示,可在非晶質碳氮膜330消失的狀態下完成蝕刻對象膜之圖型化。另外,進行灰化時,可利用O2 氣體及Ar的混合氣體,或O2 氣體及N2 的混合氣體,亦可利用N2 氣體及H2 氣體的混合氣體。
(非晶質碳氮膜的電漿耐受性)
以下針對上述非晶質碳氮膜的電漿耐受性,說明發明人所進行的實験。步驟條件與形成非晶質碳氮膜時幾乎相同,將處理容器內維持在20mTorr的減壓狀態,並使上壁、下壁、晶座105的溫度分別為60℃、50℃、40℃方式來調整處理容器內的溫度。對沖淋器(上電極)150施加「15秒」由高頻電源175所輸出之4.0W/cm2 的高頻電力。未施加用以形成偏壓的高頻電力。沖淋器150與晶座105間的間隙為30cm。
處理容器內的氣氛安定後,測量以下各膜的消失量。具體來說,該步驟條件係對照射光源(g線)波長為436nm之光阻膜(比較膜1)、非晶質碳膜(膜1)及非晶質碳氮膜(膜2、膜3)進行相同的評估。將其結果示於圖9。圖9中,在對蝕刻對象膜進行15秒的蝕刻期間,比較膜1在中央部只消失了Δ70nm,在端部只消失了Δ90nm。亦即,在進行15秒的蝕刻期間,比較膜1的中央部只有70nm變薄,端部只有90nm變薄。
相對於此,膜1、膜2、膜3在中央部只分別消失了Δ37.6nm、Δ42.7nm、Δ54.8nm,在端部只分別消失了Δ37.8nm、Δ48.6nm、Δ57.7nm的膜。由該結果得知,非晶質碳氮膜330可較照射光源(g線)波長為436nm之光阻膜其電漿耐受性更加提高。不僅如此,非晶質碳氮膜330可較照射g線之光阻膜,具有在蝕刻進行時較高的面均勻性。在經驗上已知照射g線之光阻膜在實用面上具有充分的電漿耐受性。因此,在此實験中證明了膜消失量較少且在蝕刻進行時具有較高的面均勻性之非晶質碳氮膜係一種選擇比高於照射g線之光阻膜且實用上亦為具優異耐受性之膜。
簡單地歸納上述說明,本實施形態之半導體裝置的製造方法至少包含以下步驟。
(a)於晶圓上形成蝕刻對象膜之步驟
(b)將含有一氧化碳氣體及氮氣之處理氣體供給至處理容器的內部之步驟
(c)於該處理容器內將一氧化碳氣體及氮氣分解以在被處理體上形成非晶質碳氮膜之步驟
(d)於非晶質碳氮膜330上形成氧化矽膜335之步驟
(e)於氧化矽膜335上形成ArF光阻膜345之步驟
(f)將ArF光阻膜345進行圖型化之步驟
(g)以ArF光阻膜345作為蝕刻遮罩來蝕刻氧化矽膜335之步驟
(h)利用氧化矽膜335作為蝕刻遮罩來蝕刻非晶質碳氮膜330以將ArF光阻膜345的圖型轉印之步驟
(i)以非晶質碳氮膜330作為蝕刻遮罩來將蝕刻對象膜蝕刻之步驟
藉此,利用蝕刻耐受性佳且可在以193nm之雷射光來將ArF光阻膜345曝光時降低照射光的反射率之非晶質碳氮膜330,可正確地將圖型轉印至蝕刻對象膜。
以上,係參照添附圖式來說明本發明之最佳實施形態,但毋須贅言本發明不限定上述實施形態。該技術所屬技術領域中具通常技術者應當可在申請專利範圍所記載的範圍內,想得到各種的變化或修正例,而該等亦應當屬於本發明之技術範圍。
譬如,該實施形態中,本發明係顯示將非晶質碳氮膜應用在乾顯影技術中之多層光阻膜中的下方層的情況,但不限於此,亦可使同樣的膜形成於通常的光阻膜正下方來作為具有反射防止膜功能之蝕刻遮罩等,亦可用於其他各種用途。
又,譬如,該實施形態係以一氧化碳氣體作為形成非晶質碳氮膜時所使用的氣體,但依步驟不同也可利用二氧化碳氣體。
又,該實施形態係以半導體晶圓來作為被處理體的例子,但不限於此,亦可應用在以液晶顯示裝置(LCD)為代表的平面顯示器(FPD)用玻璃基板等其他的基板。
B...圖型的交界部分
L...氣體通路
W...晶圓
10...電漿CVD裝置
100...處理容器
105...晶座
110...支承體
115...下電極
120...加熱器
125...整合器
130...高頻電源
135...加熱器電源
140...固定環
145...絕緣體
150...沖淋器
150a...緩衝區域
155...氣體供給源
160...氣體導入口
165...氣體噴出口
170...整合器
175...高頻電源
180...排氣管
185...排氣裝置
190...搬入出口
195...閘閥
200...控制裝置
200a...CPU
200b...ROM
200c...RAM
200d...界面
200e...匯流排
305‧‧‧SiC膜
310‧‧‧SiOC膜
315‧‧‧SiC膜
320‧‧‧SiO2
325‧‧‧SiN膜
330‧‧‧非晶質碳氮膜
335‧‧‧氧化矽膜
340‧‧‧反射防止膜
345‧‧‧ArF光阻膜
圖1係可應用於形成本發明實施形態的非晶質碳氮膜之電漿CVD裝置的縱剖面圖。
圖2係用以說明同實施形態產生非晶質碳氮膜時的分解、生成反應之示意圖。
圖3係顯示同實施形態利用非晶質碳氮膜來製造半導體裝置之多層膜構造的縱剖面圖。
圖4係用以說明同實施形態藉由光微影製程來將ArF光阻膜進行圖型化步驟之示意圖。
圖5係顯示同實施形態之非晶質碳氮膜反射率的實験結果。
圖6係顯示同實施形態以圖型化後之ArF光阻膜作為遮罩來蝕刻氧化矽膜後的結果之剖面圖。
圖7係顯示同實施形態以圖型化後之氧化矽膜作為遮罩來蝕刻非晶質碳氮膜後的結果之剖面圖。
圖8係顯示同實施形態以圖型化後之非晶質碳氮膜作為遮罩來蝕刻蝕刻對象膜後的結果之剖面圖。
圖9係顯示對同實施形態之非晶質碳氮膜的電漿耐受性進行評估後的實験結果。
W...晶圓
305...SiC膜
310...SiOC膜
315...SiC膜
320...SiO2
325...SiN膜
330...非晶質碳氮膜
335...氧化矽膜
340...反射防止膜
345...ArF光阻膜

Claims (12)

  1. 一種非晶質碳氮膜的形成方法,係包含:將被處理體設置於處理容器內之步驟;將含有一氧化碳氣體及氮氣,但分子中不含氫原子的處理氣體供給至該處理容器內之步驟;以及將該處理容器內的一氧化碳氣體及氮氣分解以在被處理體上形成非晶質碳氮膜之步驟。
  2. 如申請專利範圍第1項之非晶質碳氮膜的形成方法,其中該非晶質碳氮膜中的氮原子含有率為同膜中所含有碳原子的10%以下。
  3. 如申請專利範圍第1項之非晶質碳氮膜的形成方法,其中該非晶質碳氮膜係利用電漿CVD裝置而成膜在被處理體上。
  4. 如申請專利範圍第3項之非晶質碳氮膜的形成方法,其中該電漿CVD裝置係於該處理容器內設置有上電極及下電極之平行平板型電漿CVD裝置,並且在被處理體設置於該下電極上的狀態下,至少對該上電極施加高頻電力以由該處理氣體來產生電漿。
  5. 如申請專利範圍第4項之非晶質碳氮膜的形成方法,其中係對該下電極施加用以形成偏壓之高頻電力。
  6. 如申請專利範圍第4項之非晶質碳氮膜的形成方法,其中該上電極係碳電極。
  7. 如申請專利範圍第1項之非晶質碳氮膜的形成方法,其中該處理氣體係包含惰性氣體。
  8. 一種非晶質碳氮膜,係利用含有一氧化碳氣體及氮氣,但分子中不含氫原子之處理氣體並藉由電漿CVD裝置而形成於被處理體上。
  9. 一種多層光阻膜,係藉由將含有一氧化碳氣體及氮氣,但分子中不含氫原子之處理氣體供給至處理容器內並將該處理容器內的一氧化碳氣體及氮氣分解而具有:形成於蝕刻對象膜上之非晶質碳氮膜;形成於該非晶質碳氮膜上之矽系薄膜;以及形成於該矽系薄膜上之光阻膜。
  10. 一種半導體裝置之製造方法,其包含:於被處理體上形成蝕刻對象膜之步驟;將含有一氧化碳氣體及氮氣,但分子中不含氫原子的處理氣體供給至處理容器內之步驟;將該處理容器內的一氧化碳氣體及氮氣分解以在被處理體上形成非晶質碳氮膜之步驟;於該非晶質碳氮膜上形成矽系薄膜之步驟;於該矽系薄膜上形成光阻膜之步驟;將該光阻膜進行圖型化之步驟;以該光阻膜作為蝕刻遮罩來蝕刻該矽系薄膜之步驟;以該矽系薄膜作為蝕刻遮罩來蝕刻該非晶質碳氮 膜之步驟;以及以該非晶質碳氮膜作為蝕刻遮罩來蝕刻該蝕刻對象膜之步驟。
  11. 如申請專利範圍第10項之半導體裝置之製造方法,其中係利用波長為193nm的光線來將作為該光阻膜之ArF光阻膜進行圖型化。
  12. 一種非晶質碳氮膜的形成方法,係包含:將被處理體設置於處理容器內之步驟;對該處理容器內供應含有氮氣及第1氣體,但分子中不含氫原子的處理氣體之步驟,其中該第1氣體僅含有碳原子與氧原子;以及於該處理容器內利用電漿在被處理體上形成非晶質碳氮膜之步驟。
TW098128747A 2008-08-28 2009-08-27 A method for forming an amorphous carbon-nitrogen film, an amorphous carbon-nitrogen film, a multilayer photoresist film, a method of manufacturing a semiconductor device, and a memory medium having a memory control program TWI452630B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008219359A JP5289863B2 (ja) 2008-08-28 2008-08-28 アモルファスカーボンナイトライド膜の形成方法、多層レジスト膜、半導体装置の製造方法および制御プログラムが記憶された記憶媒体

Publications (2)

Publication Number Publication Date
TW201021121A TW201021121A (en) 2010-06-01
TWI452630B true TWI452630B (zh) 2014-09-11

Family

ID=41721211

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098128747A TWI452630B (zh) 2008-08-28 2009-08-27 A method for forming an amorphous carbon-nitrogen film, an amorphous carbon-nitrogen film, a multilayer photoresist film, a method of manufacturing a semiconductor device, and a memory medium having a memory control program

Country Status (6)

Country Link
US (1) US8741396B2 (zh)
JP (1) JP5289863B2 (zh)
KR (1) KR101194192B1 (zh)
CN (1) CN102112651B (zh)
TW (1) TWI452630B (zh)
WO (1) WO2010024037A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5289863B2 (ja) * 2008-08-28 2013-09-11 東京エレクトロン株式会社 アモルファスカーボンナイトライド膜の形成方法、多層レジスト膜、半導体装置の製造方法および制御プログラムが記憶された記憶媒体
JP5568340B2 (ja) 2010-03-12 2014-08-06 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
WO2011158703A1 (en) * 2010-06-18 2011-12-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN102115878B (zh) * 2010-11-26 2012-09-26 中国科学院微电子研究所 一种单晶立方型氮化碳薄膜的制备方法
CN101985744B (zh) * 2010-11-26 2012-07-04 中国科学院微电子研究所 一种单晶立方型氮化碳薄膜的制备方法
JP5588856B2 (ja) 2010-12-27 2014-09-10 東京エレクトロン株式会社 カーボン膜上への酸化物膜の成膜方法及び成膜装置
DE102013112855A1 (de) * 2013-11-21 2015-05-21 Aixtron Se Vorrichtung und Verfahren zum Fertigen von aus Kohlenstoff bestehenden Nanostrukturen
US9449821B2 (en) * 2014-07-17 2016-09-20 Macronix International Co., Ltd. Composite hard mask etching profile for preventing pattern collapse in high-aspect-ratio trenches
JP2019047119A (ja) * 2017-09-04 2019-03-22 Tdk株式会社 磁気抵抗効果素子、磁気メモリ、および磁気デバイス
JP6782211B2 (ja) * 2017-09-08 2020-11-11 株式会社東芝 透明電極、それを用いた素子、および素子の製造方法
KR20220012474A (ko) 2020-07-22 2022-02-04 주식회사 원익아이피에스 박막 증착 방법 및 이를 이용한 반도체 소자의 제조방법
EP3945067A1 (en) 2020-07-27 2022-02-02 Universitat Rovira I Virgili A method for producing an s-triazine or s-heptazine-based polymeric or oligomeric materials and s-triazine or s-heptazine-based coatings and composites derived therefrom

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000072415A (ja) * 1998-08-20 2000-03-07 Riyuukoku Univ 結晶質の窒化炭素膜を形成する方法
US6486082B1 (en) * 2001-06-18 2002-11-26 Applied Materials, Inc. CVD plasma assisted lower dielectric constant sicoh film
US20070262705A1 (en) * 2004-04-05 2007-11-15 Idemitsu Kosan Co., Ltd. Organic Electroluminescence Display Device

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4504519A (en) * 1981-10-21 1985-03-12 Rca Corporation Diamond-like film and process for producing same
US6099457A (en) * 1990-08-13 2000-08-08 Endotech, Inc. Endocurietherapy
US5606056A (en) * 1994-05-24 1997-02-25 Arizona Board Of Regents Carbon nitride and its synthesis
CN1138635A (zh) * 1995-06-16 1996-12-25 南京大学 一种低温镀复金刚石薄膜的方法及设备
JP2000285437A (ja) * 1999-03-31 2000-10-13 Hoya Corp 磁気記録媒体及びその製造方法
JP5121090B2 (ja) 2000-02-17 2013-01-16 アプライド マテリアルズ インコーポレイテッド アモルファスカーボン層の堆積方法
WO2001085811A2 (en) * 2000-05-05 2001-11-15 E.I. Du Pont De Nemours And Company Copolymers for photoresists and processes therefor
US7498066B2 (en) * 2002-05-08 2009-03-03 Btu International Inc. Plasma-assisted enhanced coating
JP3941627B2 (ja) * 2002-08-07 2007-07-04 株式会社豊田中央研究所 密着層を備える積層体
JP3921528B2 (ja) * 2002-09-06 2007-05-30 独立行政法人物質・材料研究機構 リソグラフィ用基板被覆構造体
JP3931229B2 (ja) * 2002-09-13 2007-06-13 独立行政法人物質・材料研究機構 酸化炭素薄膜および酸化窒化炭素薄膜とこれら酸化炭素系薄膜の製造方法
JP4150789B2 (ja) * 2003-01-14 2008-09-17 独立行政法人産業技術総合研究所 非晶質窒化炭素膜及びその製造方法
US20040227197A1 (en) * 2003-02-28 2004-11-18 Shinji Maekawa Composition of carbon nitride, thin film transistor with the composition of carbon nitride, display device with the thin film transistor, and manufacturing method thereof
JP4439943B2 (ja) * 2003-02-28 2010-03-24 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI250558B (en) * 2003-10-23 2006-03-01 Hynix Semiconductor Inc Method for fabricating semiconductor device with fine patterns
KR100628029B1 (ko) * 2004-12-04 2006-09-26 주식회사 아이피에스 박막 증착 방법 및 이를 이용한 반도체 제조방법
JPWO2007078011A1 (ja) * 2006-01-06 2009-06-11 日本電気株式会社 多層配線の製造方法と多層配線構造
US7473950B2 (en) * 2006-06-07 2009-01-06 Ovonyx, Inc. Nitrogenated carbon electrode for chalcogenide device and method of making same
JP2008105321A (ja) * 2006-10-26 2008-05-08 Kyocera Mita Corp 画像形成装置
JP5200371B2 (ja) * 2006-12-01 2013-06-05 東京エレクトロン株式会社 成膜方法、半導体装置及び記憶媒体
WO2008105321A1 (ja) * 2007-02-28 2008-09-04 Tokyo Electron Limited アモルファスカーボン膜の形成方法、アモルファスカーボン膜、多層レジスト膜、半導体装置の製造方法およびコンピュータ可読記憶媒体
WO2008114609A1 (ja) * 2007-03-19 2008-09-25 Nec Corporation 半導体装置及びその製造方法
US8071872B2 (en) * 2007-06-15 2011-12-06 Translucent Inc. Thin film semi-conductor-on-glass solar cell devices
SE532721C2 (sv) * 2007-10-01 2010-03-23 Mircona Ab Produkt med vibrationsdämpande keramisk beläggning för spånavskiljning vid materialbearbetning samt metod för dess tillverkning
TW200947670A (en) * 2008-05-13 2009-11-16 Nanya Technology Corp Method for fabricating a semiconductor capacitor device
WO2009143618A1 (en) * 2008-05-28 2009-12-03 Sixtron Advanced Materials, Inc. Silicon carbide-based antireflective coating
JP5064319B2 (ja) * 2008-07-04 2012-10-31 東京エレクトロン株式会社 プラズマエッチング方法、制御プログラム及びコンピュータ記憶媒体
JP5289863B2 (ja) * 2008-08-28 2013-09-11 東京エレクトロン株式会社 アモルファスカーボンナイトライド膜の形成方法、多層レジスト膜、半導体装置の製造方法および制御プログラムが記憶された記憶媒体
US20100203339A1 (en) * 2009-02-06 2010-08-12 Osman Eryilmaz Plasma treatment of carbon-based materials and coatings for improved friction and wear properties
JP2012038815A (ja) * 2010-08-04 2012-02-23 Toshiba Corp 磁気抵抗素子の製造方法
JP5412402B2 (ja) * 2010-11-02 2014-02-12 株式会社日立製作所 摺動部品およびそれを用いた機械装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000072415A (ja) * 1998-08-20 2000-03-07 Riyuukoku Univ 結晶質の窒化炭素膜を形成する方法
US6486082B1 (en) * 2001-06-18 2002-11-26 Applied Materials, Inc. CVD plasma assisted lower dielectric constant sicoh film
US20070262705A1 (en) * 2004-04-05 2007-11-15 Idemitsu Kosan Co., Ltd. Organic Electroluminescence Display Device

Also Published As

Publication number Publication date
JP2010053397A (ja) 2010-03-11
US8741396B2 (en) 2014-06-03
CN102112651A (zh) 2011-06-29
KR101194192B1 (ko) 2012-10-25
CN102112651B (zh) 2013-05-22
WO2010024037A1 (ja) 2010-03-04
JP5289863B2 (ja) 2013-09-11
KR20110027759A (ko) 2011-03-16
US20110201206A1 (en) 2011-08-18
TW201021121A (en) 2010-06-01

Similar Documents

Publication Publication Date Title
TWI452630B (zh) A method for forming an amorphous carbon-nitrogen film, an amorphous carbon-nitrogen film, a multilayer photoresist film, a method of manufacturing a semiconductor device, and a memory medium having a memory control program
TWI801673B (zh) 用來蝕刻含碳特徵之方法
JP7199381B2 (ja) リソグラフィにおける確率的な歩留まりへの影響の排除
JP7058080B2 (ja) Aleおよび選択的蒸着を用いた基板のエッチング
KR100777043B1 (ko) 비정질 탄소막 형성 방법 및 이를 이용한 반도체 소자의제조 방법
CN105190840B (zh) 用于多图案化应用的光调谐硬掩模
TWI413187B (zh) Method for forming amorphous carbon film, amorphous carbon film, multilayer resist film, manufacturing method of semiconductor device, and computer readable recording medium
KR101813954B1 (ko) 플라즈마 처리 방법 및 플라즈마 처리 장치
TWI463529B (zh) An amorphous carbon film forming method and a film forming apparatus, and a method of manufacturing the semiconductor device using the film forming method, and a computer readable memory medium
US20130048606A1 (en) Methods for in-situ chamber dry clean in photomask plasma etching processing chamber
JP2020527856A (ja) フォトレジストパターニングスカムの除去のための原子層洗浄
KR20060127250A (ko) 금속 에칭 하드마스크 분야용 비정질 탄소막 증착 방법
TWI518217B (zh) Etching method and etching device
KR20070089082A (ko) 기판의 부식을 제어하기 위한 방법
US20150177624A1 (en) Method for manufacturing reflective mask and apparatus for manufacturing reflective mask
JP2007266099A (ja) 低誘電率膜のダメージ修復方法、半導体製造装置、記憶媒体
JP2024026599A (ja) プラズマ処理装置
US20100043821A1 (en) method of photoresist removal in the presence of a low-k dielectric layer
US6044850A (en) Semiconductor device manufacturing method including ashing process
WO2005055305A1 (ja) 半導体基板導電層表面の清浄化方法
JP4058669B2 (ja) シリコン基板上への導電性珪化物層の形成方法および導電性珪化物接点の形成方法
JP2974376B2 (ja) 半導体装置の製造方法
KR20080102928A (ko) 비정질 탄소막 형성 방법 및 이를 이용한 반도체 소자의제조 방법
WO2024058135A1 (ja) 基板処理方法及び基板処理システム
JP2020177958A (ja) 基板処理方法及び基板処理装置

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees