TWI420601B - 製造一氮化閘極介電層之方法 - Google Patents

製造一氮化閘極介電層之方法 Download PDF

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TWI420601B
TWI420601B TW095106163A TW95106163A TWI420601B TW I420601 B TWI420601 B TW I420601B TW 095106163 A TW095106163 A TW 095106163A TW 95106163 A TW95106163 A TW 95106163A TW I420601 B TWI420601 B TW I420601B
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dielectric layer
gate
forming
substrate
interface
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TW200644127A (en
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Sangwoo Lim
Paul A Grudowski
Tien Ying Luo
Olubunmi O Adetutu
Hsing H Tseng
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Freescale Semiconductor Inc
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Description

製造一氮化閘極介電層之方法
本發明關於製造半導體裝置，且較特別的是關於製造具有氮化閘極介電層之半導體裝置結構。
隨著半導體裝置結構持續在變小，閘極介電層亦變得越來越薄。其中一項困難係說明於圖1中，即一半對數圖，其揭示隨著有效閘極厚度Tox(有效閘極氧化物厚度係一從閘極至通道之電氣性量測值)減小，通過閘極介電層之漏電密度Jg則顯著增加。在下方之閘極厚度處，僅2埃之變化即導致漏電密度以10的倍數增加。減小閘極介電層厚度之主要動機在於改善電晶體之電流驅動Ion。電流驅動與閘極厚度大體上具有減小厚度10%則增加電流驅動10%之一致性。因此對於減小2埃厚度即大約10%之情況中，驅動電流僅增加10%，但是漏電密度增加10倍。因此，隨著閘極介電層厚度已進入20－30埃之範圍，想透過閘極介電層厚度減小同時維持漏電在一合理程度，以尋求一達成驅動電流增加之方法已日益困難。
因此，吾人仍需要尋求達成電流驅動增加同時將閘極漏電維持在一合理程度之方法。
在一態樣中，一閘極介電層係由一氮化步驟及一退火處理。隨後，執行另一氮化步驟及退火。第二氮化步驟及退火造成最終形成之電晶體之閘極漏電密度與電流驅動之間關係的改善。此可以藉由參考諸圖及文後說明而獲得最佳之瞭解。
圖2中所示者係一裝置結構10，其包含一半導體基板12及一位於基板12上之閘極介電層14。基板12較佳為矽，但是也可以是其他半導體材料，例如矽鍺。半導體基板12被揭示為一大型矽基板，但是也可以是一SOI基板。此範例中之閘極介電層14係以高溫生長之氧化矽，且大約12埃厚度。此處之厚度為實質厚度，除非另有說明。
圖3中所示者係在一電漿氮化步驟16後之一裝置結構10，其導致閘極介電層14變成一摻雜氮之閘極介電層18。摻雜氮之閘極介電層14變成閘極介電層18較佳為藉由電漿達成，但是其他方法亦可使用，例如熔爐或植入。利用熔爐或植入二者將氮摻雜之缺點在於其在閘極介電層18與基板12之間之介面處之氮容易比利用電漿時多。該電漿氮化之一範例為達成3至10原子百分比之氮濃度。
圖4中所示者係在一氧氣環境中執行退火後之一裝置結構10。此具有將一無氮之氧化物層19生長大約1埃之效果。退火較佳在大約攝氏1000度時執行。一示範性製程係以一大約250 SCCM流動率及10托(Torr)壓力將氧施加作為分子氧。在選項上，另一氧化物生長步驟可經執行以令氧化物層19更厚些。在另一替代型式中，退火步驟可在一惰氣環境中執行，例如N2或氫氣，接著為一氧化物生長步驟。在使用一惰氣環境之例子中，氧化物層19並未形成。在一氧氣環境中退火相似於氧化物生長之處在於此二者皆為較高溫度，且氧化物之形成係由於閘極介電層18與基板12之間之介面處之氧化物生長所致。若此二者皆被執行，則基本上之差異為氧化物生長溫度較低於退火者，且其執行時間較長。相似於利用氮化及退火之圖4所示裝置結構10的一裝置結構之形成已知具有減少閘漏之優點，但是其代價為減少電流驅動。據信其係因為在基板與電漿氮化介電層之間之介面處形成一氧化物層所致，其將閘極氮化介電層退火而將一部分氮移離該介面，因而形成一極微細之平滑介面。
圖4之裝置結構10之形成不同於先前技術之處在於圖4之裝置結構10係針對後續之氮化及退火而製備。
圖5中所示者係在執行一電漿氮化步驟20後之裝置結構10。其藉由增添1至3原子百分比而具有增加氮百分比之效果。例如，若圖3之裝置結構10中之氮濃度為3原子百分比，則圖5之裝置結構10中之濃度約為4至6百分比。此製程可以相同於圖3所示氮化步驟中使用之製程。
圖6中所示者係在一氧氣環境中執行退火後之裝置結構10，其形成一實質上無氮之氧化物層23。退火較佳在大約攝氏1100度時執行。一示範性製程係以一大約250 SCCM流動率及10托壓力將氧施加作為分子氧。
圖7中所示者係一電晶體使用閘極介電層22作為該電晶體所用閘極介電層時之裝置結構10。該電晶體包含一位於閘極介電層22上方之閘極24、一位於閘極24周側之側壁填隙物26、一位於基板12內且鄰接於閘極24一側之源極/汲極28、及一位於基板12內且鄰接於閘極24另一側之源極/汲極30。
圖8中所示者係電流驅動(Ion)對閘極漏電密度(Jg)之關係之一曲線32及34之圖表。曲線32係用於單一氮化及一退火以及無氮化與退火之例子。曲線34係用於如圖2－7所示之另一氮化及退火之例子。單一氮化及退火實質上與無氮化及退火之曲線並無變化，而是僅沿著曲線32將位置移向較少漏電及較少電流驅動之方向中。第二氮化及退火造成曲線32移至曲線34。吾人相信這是在遠離於基板12處氮化及在氧化物層23與基板12之間之介面25處有一實質上無氮介面的結果。曲線34上之一位置36與曲線32上之一位置38具有相同電流驅動，但是前者之漏電密度較低於位置38者。同樣地，曲線34上之一位置39具有較低於位置40者之漏電密度，但是維持相同的電流驅動。
圖8中說明之改良處已藉由依相同於第一氮化及退火之條件摻雜第二氮化及退火而被發現。例如，二次氮化皆以350瓦、20%工作週期、10仟赫、15秒、10毫托、250 SCCM氮流動率執行，且二次退火皆以攝氏1000度、0.5托、15秒、及250 SCCM氧流動率執行，其造成閘極漏電密度大約70%之改善，同時維持電流驅動實質相同。
圖9中所示者係一流程圖，揭示用於形成圖7之裝置結構10之製程步驟及提供圖8中所示之效益。步驟42為形成一閘極介電層。隨後係如步驟44所示之執行電漿氮化。步驟46為退火，較佳在一氧氣環境中執行。步驟48係一形成多數個閘極介電層之選項性步驟。如果退火步驟發生在一氧氣環境中，則通常不需要執行步驟48。步驟50為另一氮化步驟，較佳以相同於步驟44之方式執行。步驟52為另一退火步驟，較佳以相同於步驟46之方式執行。在此流程中，在二次氮化/退火步驟之後，一電晶體即在步驟54中形成。氮化/退火步驟可以在形成該電晶體前超過二次。
圖10－13揭示圖2－7所示者之一可替代實施例。
圖10中所示者係一裝置結構60，其包含一半導體基板62及一閘極介電層，該閘極介電層係由一位於基板62上之介面氧化物層64及一高K介電層組成，該高K介電層例如可為一金屬氧化物、一金屬矽酸鹽、一金屬鋁酸鹽、一金屬氮氧矽化物、或一金屬鑭酸鹽。基板62較佳為矽，但是也可以是其他半導體材料，例如矽鍺。半導體基板62被揭示為一大型矽基板，但是也可以是一SOI基板。在此例子中該高K介電層66為利用原子層沉積(ALD)而沉積之氧化鉿。介面氧化物層64係一氧化物層，在實施上，其在形成閘極介電層時一直都存在著，特別是形成於矽上時。
圖11中所示者係在一電漿氮化步驟68後之裝置結構60，其導致高K介電層66變成一摻雜氮之金屬氧化物層70，及介面氧化物層64變成一具有些許氮之介面氧化物層72。摻雜之高K介電層66變成高K介電層70較佳為藉由電漿達成，但是其他方法亦可使用，例如熔爐或植入，不過會有上述缺點。該電漿氮化之一範例為達成3至10原子百分比之氮濃度。接著是在一氧氣環境中之退火。退火較佳在大約攝氏1000與1200度之間執行。一示範性製程係以一大約250 SCCM流動率及10托壓力將氧施加作為分子氧。在選項上，另一高K介電層沉積步驟可經執行以令高K層70更厚些。相似於利用氮化及退火之圖11所示裝置結構60的一裝置結構之形成已屬習知，且已知其具有減少閘漏之優點，但是其代價為減少電流驅動。據信其係因為在基板與電漿氮化介電層之間之介面處形成一氧化物層所致，其將閘極氮化介電層退火而將一部分氮移離該介面，因而形成一極微細之平滑介面。
圖11之裝置結構60之形成不同於先前技術之處在於圖11之裝置結構60係針對後續之氮化及退火而製備。
圖12中所示者係在執行一電漿氮化步驟20與在一氧氣環境中執行一退火後之裝置結構60。此製程可以相同於圖11所示氮化與退火步驟中使用之製程。其具有改變高K介電層70與介面層72以分別形成高K介電層76與介面氧化物層78之效果。層76、78包含一閘極介電層80。
圖13中所示者係一電晶體使用閘極介電層80作為該電晶體所用閘極介電層時之裝置結構60。該電晶體包含一位於閘極介電層80上方之閘極82、一位於閘極82周側之側壁填隙物84、一位於基板62內且鄰接於閘極82一側之源極/汲極86、及一位於基板62內且鄰接於閘極82另一側之源極/汲極88。
本文揭述一種雙氮化/退火製程。所述之氮化/退火步驟數可以延續超過二次。在金屬氧化物之例子中，多數次氮化/退火步驟優於單一氧化與退火之處在於氮構型之調制與高K介電品質之改善。
在先前之說明中，本發明已參考特定實施例說明於前，惟，習於此技者可以瞭解的是在不脫離文後請求項所載之本發明範疇下，仍可達成多種修改及變化。特定材料已揭述於上且其可以改變。對於其他替代型式，氧化鉿被揭述作為示範性金屬氧化物，但是其他高K介電質亦可使用，例如氧化鋯，或其他金屬氧化物例如氮氧化鋁鑭亦可自此製程獲益。據此，說明書及圖式應視為闡釋而非侷限，且諸此修改應包括在本發明範疇內。
效益、其他優點及對於問題之解決辦法已相關於特定實施例說明於前，惟，效益、優點、對於問題之解決辦法、及可能使任意效益、其他優點或解決辦法發生或更彰顯之任意要素不應解釋為任意或所有請求項之一重要、必要或主要特性或要素。本文所用之"包含"、"含有"、或其變換型式皆在涵蓋一非排他性之包攝，例如含有一表列元件之製程、方法、物件或裝置不僅包括諸元件，而是可包括未列示或此製程、方法、物件或裝置原有之其他元件。
10、60．．．裝置結構
12、62．．．半導體基板
14、18、22、80．．．閘極介電層
16、20、68．．．電漿氮化步驟
19、23．．．氧化物層
24、82．．．閘極
25．．．介面
26、84．．．側壁填隙物
28、30、86、88．．．源極/汲極
32、34．．．曲線
36、38、39、40．．．位置
64、72、78．．．介面氧化物層
66、70、76．．．高K介電層
本發明係利用範例說明且不受附圖限制，其中相同參考編號表示相同元件，及其中：圖1係有效閘極厚度對閘極漏電密度之關係之圖表；圖2係根據本發明第一實施例之一製程中之一階段之一裝置結構之截面圖；圖3係圖2所示之後續製程中之一階段之圖2所示裝置結構之截面圖；圖4係圖3所示之後續製程中之一階段之圖3所示裝置結構之截面圖；圖5係圖4所示之後續製程中之一階段之圖4所示裝置結構之截面圖；圖6係圖5所示之後續製程中之一階段之圖5所示裝置結構之截面圖；圖7係圖6所示之後續製程中之一階段之圖6所示裝置結構之截面圖；圖8係一圖表，揭示針對一氮化與退火及另一氮化與退火之電流驅動對閘極漏電密度之關係；圖9係根據本發明第一實施例之一方法之流程圖；圖10係根據本發明第二實施例之一製程中之一階段之一裝置結構之截面圖；圖11係圖10所示之後續製程中之一階段之圖10所示裝置結構之截面圖；圖12係圖11所示之後續製程中之一階段之圖11所示裝置結構之截面圖；圖13係圖12所示之後續製程中之一階段之圖12所示裝置結構之截面圖。
習於此技者應瞭解圖中的元件僅為簡單與清晰目的而說明，因此未依比例繪製。例如，圖中某些元件的尺寸可相對於其他元件誇大，以協助增進對本發明實施例的瞭解。
10．．．裝置結構
12．．．半導體基板
20．．．電漿氮化步驟
22．．．閘極介電層

Claims (11)

  1. 一種形成一閘極氮化介電層之方法，其包含：形成一介電層且其疊覆於一基板；藉由將該介電層曝露於一電漿氮化以形成一電漿氮化介電層以執行一第一氮化步驟；在該基板與該電漿氮化介電層之間之一介面處形成一氧化物層，其藉由將該閘極氮化介電層退火而從該介面處移動一部分氮，藉此形成一極微細之平滑介面；藉由將該電漿氮化介電層曝露於電漿氮化，以將更多氮添加至該電漿氮化介電層以執行一第二氮化步驟；及在該第二氮化步驟之後，藉由將該介面進一步平滑化，在氧的存在下將該閘極氮化介電層退火以處理該基板與該電漿氮化介電層之間之介面，使得該介面實質上無氮。
  2. 如請求項1之方法，尚包含：將該介電層形成如同二氧化矽、一金屬氧化物、一金屬矽酸鹽、一金屬鋁酸鹽、或一預定金屬之一組合或多數個金屬與一氧化物、一矽酸鹽、一鑭酸鹽、或一鋁酸鹽其中一者之一組合之其中一者。
  3. 如請求項2之方法，尚包含：將該金屬氧化物形成如同氧化鉿。
  4. 如請求項1之方法，其中將該氧化物層形成尚包含：在該基板與該電漿氮化介電層之間之該介面處形成該氧化物層，其藉由以一實質上為攝氏500度至1200度範圍 內之溫度將該閘極氮化介電層退火。
  5. 如請求項1之方法，其中將該氧化物層形成尚包含：在一惰性氣體環境中，以一實質上為攝氏500度至1200度範圍內之溫度將該閘極氮化介電層退火；及將該閘極氮化介電層放置於一氧氣環境中，以在該基板與該電漿氮化介電層之間之該介面處形成該氧化物層。
  6. 如請求項1之方法，尚包含：藉由將該介電層生長於該基板上而形成該介電層。
  7. 如請求項1之方法，尚包含：將以下步驟重複1至100次以內之一預定次數：(1)執行該第一氮化步驟；及(2)在氧的存在下進行退火。
  8. 一種形成一閘極氮化介電層之方法，其包含：(a)形成一介電層且其疊覆於一基板，及在該基板與該介電層之間之一介面處產生一氧化物層；(b)將該介電層曝露於一電漿氮化以形成一電漿氮化介電層；(c)以一預定溫度將該閘極氮化介電層退火；及(d)將步驟(a)、(b)及(c)重複1至100次以內之一預定次數以形成一閘極介電層，其與該基板具有一介面，該介面實質上無氮。
  9. 一種在一半導體內形成一閘極氮化介電層之方法，其包含： (a)形成一閘極介電層且其疊覆於一基板；(b)將該閘極介電層曝露於一氮氣環境中，以在金屬氧化物介電層內形成氮及形成一氮化閘極介電層；及(c)在氧的存在下將該閘極介電層退火；及將步驟(b)及(c)重複一預定次數以導致在該氮化閘極介電層與該基板之間之一介面，該介面實質上無氮；形成一閘極電極且其疊覆於該氮化閘極介電層，該閘極電極與該基板具有一實質上無氮之介面；及形成鄰接於該閘極電極之第一及第二電流電極，以於該半導體內提供一電晶體。
  10. 如請求項9之方法，尚包含：將該介電層形成如同二氧化矽、一金屬氧化物、一金屬矽酸鹽、一金屬鋁酸鹽、或一預定金屬之一組合或多數個金屬與一氧化物、一矽酸鹽、一鑭酸鹽、或一鋁酸鹽其中一者之一組合之其中一者。
  11. 如請求項9之方法，尚包含：藉由ALD、MOCVD及PVD其中一者沉積形成氧化鉿，以形成該閘極介電層。
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WO2006093631A2 (en) 2006-09-08
US20060194423A1 (en) 2006-08-31
EP1856724A2 (en) 2007-11-21
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