JP4762169B2 - 半導体装置の製造方法 - Google Patents
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- JP4762169B2 JP4762169B2 JP2007038436A JP2007038436A JP4762169B2 JP 4762169 B2 JP4762169 B2 JP 4762169B2 JP 2007038436 A JP2007038436 A JP 2007038436A JP 2007038436 A JP2007038436 A JP 2007038436A JP 4762169 B2 JP4762169 B2 JP 4762169B2
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- 239000004065 semiconductor Substances 0.000 title claims description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 40
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 86
- 229910052757 nitrogen Inorganic materials 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 32
- 238000000137 annealing Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 31
- 239000012535 impurity Substances 0.000 claims description 27
- 239000007789 gas Substances 0.000 claims description 25
- 229910052710 silicon Inorganic materials 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 17
- 230000001590 oxidative effect Effects 0.000 claims description 9
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 24
- 229910021529 ammonia Inorganic materials 0.000 description 12
- 238000005259 measurement Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- 238000005121 nitriding Methods 0.000 description 11
- 230000007547 defect Effects 0.000 description 8
- 239000010410 layer Substances 0.000 description 7
- 238000002474 experimental method Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002829 nitrogen Chemical class 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
半導体基板の表面に絶縁膜を形成する工程と、
前記絶縁膜に活性窒素を導入する工程と、
前記活性窒素が導入された絶縁膜に対して、窒素原子を含有する非酸化系のガスの雰囲気中で熱処理を行う工程と、
を有することを特徴とする半導体装置の製造方法。
前記半導体基板としてシリコン基板を用いることを特徴とする付記1に記載の半導体装置の製造方法。
前記絶縁膜を形成する工程は、前記シリコン基板の表面を酸化することにより、シリコン酸化膜を形成する工程を有することを特徴とする付記2に記載の半導体装置の製造方法。
前記活性窒素を導入する工程は、前記絶縁膜に対しプラズマ窒化を行う工程を有することを特徴とする付記1乃至3のいずれか1項に記載の半導体装置の製造方法。
前記窒素原子を含有する非酸化系のガスとして、NH3ガスを用いることを特徴とする付記1乃至4のいずれか1項に記載の半導体装置の製造方法。
前記熱処理を行う工程の後に、酸素原子を含有するガスの雰囲気中でアニールを行う工程を有することを特徴とする付記1乃至5のいずれか1項に記載の半導体装置の製造方法。
前記酸素原子を含有するガスとして、O2ガス、N2Oガス及びNOガスからなる群から選択された少なくとも1種を用いることを特徴とする付記6に記載の半導体装置の製造方法。
前記熱処理を行う際の前記半導体基板の温度を、前記活性窒素を導入する際の前記半導体基板の温度よりも高くすることを特徴とする付記1乃至7のいずれか1項に記載の半導体装置の製造方法。
前記アニールを行う際の前記半導体基板の温度を、前記熱処理を行う際の前記半導体基板の温度よりも高くすることを特徴とする付記6乃至8のいずれか1項に記載の半導体装置の製造方法。
前記活性窒素の導入を、前記絶縁膜の表面にダメージが生じない条件下で行うことを特徴とする付記1乃至9のいずれか1項に記載の半導体装置の製造方法。
前記熱処理を、前記絶縁膜中の窒素が表面に残存する条件下で行うことを特徴とする付記1乃至10のいずれか1項に記載の半導体装置の製造方法。
前記熱処理を行う工程の後に、前記絶縁膜の上にゲート電極を形成する工程を有することを特徴とする付記1乃至11のいずれか1項に記載の半導体装置の製造方法。
前記ゲート電極として、不純物を含有する多結晶シリコンからなるものを形成することを特徴とする付記12に記載の半導体装置の製造方法。
半導体基板上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記ゲート電極の側面に側壁絶縁膜を形成する工程と、
前記側壁絶縁膜をマスクとして、半導体基板内に不純物を導入する工程と、
を有し、
前記ゲート絶縁膜を形成する工程は、
シリコン酸化膜を形成する工程と、
前記シリコン酸化膜に、活性窒素を導入する工程と、
次いで、窒素原子を含むガスの雰囲気中で、加熱する工程と、
を有することを特徴とする半導体装置の製造方法。
4:シリコン酸化膜
5:シリコン酸窒化膜
14:ゲート絶縁膜
Claims (8)
- 半導体基板の表面に絶縁膜を形成する工程と、
前記絶縁膜に活性窒素を導入する工程と、
前記活性窒素が導入された絶縁膜に対して、窒素原子を含有する非酸化系のガスの雰囲気中で熱処理を行う工程と、
前記熱処理を行う工程の後に、N 2 Oガス又はNOガスの雰囲気中でアニールを行う工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記半導体基板としてシリコン基板を用いることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記絶縁膜を形成する工程は、前記シリコン基板の表面を酸化することにより、シリコン酸化膜を形成する工程を有することを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記活性窒素を導入する工程は、前記絶縁膜に対しプラズマ窒化を行う工程を有することを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。
- 前記窒素原子を含有する非酸化系のガスとして、NH3ガスを用いることを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
- 前記活性窒素の導入を、前記絶縁膜の表面にダメージが生じない条件下で行うことを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置の製造方法。
- 前記熱処理を、前記絶縁膜中の窒素が表面に残存する条件下で行うことを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置の製造方法。
- 半導体基板上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記ゲート電極の側面に側壁絶縁膜を形成する工程と、
前記側壁絶縁膜をマスクとして、半導体基板内に不純物を導入する工程と、
を有し、
前記ゲート絶縁膜を形成する工程は、
シリコン酸化膜を形成する工程と、
前記シリコン酸化膜に、活性窒素を導入する工程と、
次いで、窒素原子を含むガスの雰囲気中で、加熱する工程と、
前記加熱する工程の後に、N 2 Oガス又はNOガスの雰囲気中でアニールを行う工程と、
を有することを特徴とする半導体装置の製造方法。
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JP2007038436A JP4762169B2 (ja) | 2007-02-19 | 2007-02-19 | 半導体装置の製造方法 |
TW097101635A TW200837834A (en) | 2007-02-19 | 2008-01-16 | Method for manufacturing semiconductor device |
CNA2008100049262A CN101252085A (zh) | 2007-02-19 | 2008-01-29 | 半导体器件的制造方法 |
KR1020080012920A KR100981332B1 (ko) | 2007-02-19 | 2008-02-13 | 반도체 장치의 제조 방법 |
US12/032,030 US20080200000A1 (en) | 2007-02-19 | 2008-02-15 | Method for manufacturing semiconductor device |
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KR (1) | KR100981332B1 (ja) |
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KR101929384B1 (ko) * | 2012-05-24 | 2018-12-14 | 삼성전자주식회사 | 선택적으로 질화처리된 게이트 절연막을 갖는 반도체 장치의 제조 방법 |
TWI608614B (zh) * | 2012-12-07 | 2017-12-11 | 聯華電子股份有限公司 | 半導體結構及其製程 |
US9634083B2 (en) | 2012-12-10 | 2017-04-25 | United Microelectronics Corp. | Semiconductor structure and process thereof |
CN103035732B (zh) * | 2012-12-17 | 2015-10-28 | 华南理工大学 | 一种vdmos晶体管及其制备方法 |
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US6162687A (en) * | 1998-08-19 | 2000-12-19 | Advanced Micro Devices, Inc. | Method of manufacturing semiconductor device having oxide-nitride gate insulating layer |
US6780719B2 (en) * | 2001-06-20 | 2004-08-24 | Texas Instruments Incorporated | Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures |
CN1223555C (zh) * | 2001-07-13 | 2005-10-19 | 埃克森美孚研究工程公司 | 直接生产高纯度的费-托蜡 |
JP2004022902A (ja) * | 2002-06-18 | 2004-01-22 | Fujitsu Ltd | 半導体装置の製造方法 |
US6649538B1 (en) * | 2002-10-09 | 2003-11-18 | Taiwan Semiconductor Manufacturing Co. Ltd. | Method for plasma treating and plasma nitriding gate oxides |
JP2005033098A (ja) * | 2003-03-05 | 2005-02-03 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2005101503A (ja) * | 2003-03-26 | 2005-04-14 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US7514376B2 (en) * | 2003-04-30 | 2009-04-07 | Fujitsu Microelectronics Limited | Manufacture of semiconductor device having nitridized insulating film |
JP4059183B2 (ja) * | 2003-10-07 | 2008-03-12 | ソニー株式会社 | 絶縁体薄膜の製造方法 |
US20050130448A1 (en) * | 2003-12-15 | 2005-06-16 | Applied Materials, Inc. | Method of forming a silicon oxynitride layer |
US8119210B2 (en) * | 2004-05-21 | 2012-02-21 | Applied Materials, Inc. | Formation of a silicon oxynitride layer on a high-k dielectric material |
US7402472B2 (en) * | 2005-02-25 | 2008-07-22 | Freescale Semiconductor, Inc. | Method of making a nitrided gate dielectric |
JP4413809B2 (ja) * | 2005-03-29 | 2010-02-10 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20070134861A1 (en) * | 2005-12-14 | 2007-06-14 | Jin-Ping Han | Semiconductor devices and methods of manufacture thereof |
-
2007
- 2007-02-19 JP JP2007038436A patent/JP4762169B2/ja not_active Expired - Fee Related
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2008
- 2008-01-16 TW TW097101635A patent/TW200837834A/zh unknown
- 2008-01-29 CN CNA2008100049262A patent/CN101252085A/zh active Pending
- 2008-02-13 KR KR1020080012920A patent/KR100981332B1/ko active IP Right Grant
- 2008-02-15 US US12/032,030 patent/US20080200000A1/en not_active Abandoned
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CN101252085A (zh) | 2008-08-27 |
KR20080077325A (ko) | 2008-08-22 |
KR100981332B1 (ko) | 2010-09-10 |
US20080200000A1 (en) | 2008-08-21 |
JP2008205127A (ja) | 2008-09-04 |
TW200837834A (en) | 2008-09-16 |
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