TWI416614B - 用以改善臨界尺寸均勻度之邊緣氣體注入 - Google Patents

用以改善臨界尺寸均勻度之邊緣氣體注入 Download PDF

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TWI416614B
TWI416614B TW096121534A TW96121534A TWI416614B TW I416614 B TWI416614 B TW I416614B TW 096121534 A TW096121534 A TW 096121534A TW 96121534 A TW96121534 A TW 96121534A TW I416614 B TWI416614 B TW I416614B
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semiconductor substrate
etching
germanium
plasma
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Harmeet Singh
David Cooperberg
Vahid Vahedi
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Lam Res Corp
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    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
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    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching

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Description

用以改善臨界尺寸均勻度之邊緣氣體注入
本發明提供一種以改善之臨界尺寸均勻度蝕刻半導體基板之方法。該方法包括：將一半導體基板支撐於一電漿蝕刻室中之基板支架上；將一第一蝕刻氣體供應至該半導體基板上方一中心區域；將一包括至少一種含矽氣體之第二氣體供應至該半導體基板上方一環繞該中心區域之周邊區域，其中該第二氣體中矽之濃度大於該第一蝕刻氣體中矽之濃度；自該第一蝕刻氣體及該第二氣體中產生電漿；且電漿蝕刻該半導體基板之一暴露表面。
在諸如積體電路等基於半導體之產品之製造期間，可使用蝕刻及/或沉積步驟在諸如晶圓等半導體基板上建造或移除材料層。一習用蝕刻程序包括使用一個或多個激發成電漿狀態之蝕刻氣體來實施對一材料層之電漿蝕刻。欲蝕刻之形體包括(例如)開孔、通路、溝道及閘極結構。
許多電漿蝕刻應用依賴於產生一鈍化層以得到所期望之形體輪廓。輪廓控制之主要機制包括蝕刻及沉積反應之平衡。該蝕刻反應通常藉由諸如輸入功率、壓力及氣流等反應室參數直接控制。在矽晶圓之電漿蝕刻中，蝕刻反應產物係主要沉積源，其結果係沉積機制受到間接控制。
臨界尺寸(CD)係最小幾何形體之尺寸(例如互連線、觸點、溝道等之寬度)，該等幾何形體可於半導體裝置/電路製造期間使用既定技術形成。當一晶圓中心處形體之臨界尺寸與更接近於該晶圓邊緣之形體之臨界尺寸相同時，提供臨界尺寸均勻度。極其期望臨界尺寸均勻度到達幾乎完美之程度，其中接近一晶圓中心之所蝕刻形體與更接近於該晶圓邊緣之所蝕刻等效形體係大致均等，因為否則所製造的積體電路將具有超出所期望偏離之電子特性。隨著晶圓直徑大小的每一次增大，愈加難以保證在越來越大的晶圓上形成的積體電路之均勻度。
在蝕刻應用中使用多種蝕刻氣體化學品。舉例而言，當使用HBr－O2 蝕刻氣體化學品時，該鈍化層係主要由Six Bry Oz 構成。對於Cl2 －O2 蝕刻氣體化學品，該鈍化層係主要由Six Cly Oz 構成。該鈍化層之其他成份可包含N、C、H及F。此外，作為蝕刻矽晶圓及/或諸如石英成分等室材料之結果，揮發性矽蝕刻副產物被倂入到該鈍化層中。
由於蝕刻諸如矽晶圓及/或室材料等矽源，可將矽倂入到鈍化層中。該等矽源係不直接由該蝕刻氣體化學品控制的次要產物。此外，由於該揮發性矽蝕刻副產物被自該晶圓表面向抽真空埠輸送，存在含矽副產物沉積在該晶圓表面上之有限可能性。此外，該揮發性矽蝕刻副產物可在電漿區域中解離成反應劑，使得含矽副產物更有可能沉積在該晶圓表面上。含矽副產物沉積在該晶圓表面上可導致該晶圓上非均勻矽副產物濃度且導致所蝕刻形體臨界尺寸之非均勻度。
本文提供一種以經改善臨界尺寸均勻度蝕刻半導體基板之方法，該方法包括：將一半導體基板支撐於一電漿蝕刻室中之基板支架上；將一第一蝕刻氣體供應至該半導體基板上方一中心區域；將一包括至少一種含矽氣體之第二氣體供應至該半導體基板上方一環繞該中心區域之周邊區域，其中該第二氣體中矽之濃度大於該第一蝕刻氣體中矽之濃度；自該第一蝕刻氣體及該第二氣體中產生電漿；且電漿蝕刻該半導體基板之一暴露表面。較佳地，接近該半導體基板中心之所蝕刻形體與更接近於該晶圓邊緣之所蝕刻等效形體大致均等。
實例性含矽氣體包括(例如)SiCl4 、SiHCl3 、SiH2 Cl2 、SiH3 Cl、SiH4 、Si2 H6 、SiH3 CH3 、SiH(CH3 )3 、SiF4 、SiBr4 、原矽酸四乙酯(TEOS)或其混合物。包括至少一種含矽氣體之該第二氣體可進一步包括：(1)一惰性載氣，諸如(例如)He、Ne、Ar、Kr、Xe或其混合物；(2)一蝕刻劑氣體，諸如(例如)Cl2 、Cx Fy 、HBr、Cx Fy Hz 、SF6 、HCl或其混合物(諸如(例如)SF6 與CH2 F2 之一混合物)；及/或(3)一鈍化氣體，諸如(例如)O2 、N2 或其混合物。
該第一蝕刻氣體可包含或不包含矽。該方法可進一步包括調節：(1)供應至該周邊區域之第二氣體量；(2)供應至該周邊區域之矽量；及/或(3)該第二氣體中矽之濃度與該第一蝕刻氣體中矽之濃度之比率。
該半導體基板之暴露表面可包括一矽層，該矽層可係一諸如氮化矽、氧化矽或氮氧化矽遮罩層等遮罩下方之單晶矽晶圓之一部分。或者，該矽層可係一諸如單晶矽晶圓等基板上之磊晶層、應變型矽層或矽鍺層。該矽層可包括一矽晶圓上之多晶矽層，其中該多晶矽層係在一下層閘極氧化物與一上層硬或軟遮罩層(諸如氮化矽、氧化矽或氧氮化矽遮罩層)或光阻劑之間。或者，所揭示之蝕刻方法可應用於諸如(例如)多晶矽閘極、金屬閘極、高介電常數(K)、W及WSi閘極及間隔層蝕刻等其它蝕刻應用。
舉例而言，對於一300毫米晶圓，所蝕刻形體係較佳地小於50奈米(例如45奈米、25奈米、18奈米等)且具有小於或等於1.5奈米3σ之非均勻度。
較佳地，該電漿係一在自Lam研究公司購得的變壓器耦合電漿反應器(TCPTM )(亦被稱為感應耦合電漿(ICP)反應器)中製作的高密度電漿。
較佳地，在一感應耦合電漿反應器中執行當前揭示之方法，該感應耦合電漿反應器藉由連接至該反應器壁中一出口之真空泵而保持在一所期望之真空壓力。可藉由將來自一氣體供應之氣體供應至圍繞介電窗口底側延伸之充氣部而將蝕刻氣體供應至一蓮蓬頭或注入器配置。藉由將來自一射頻源之射頻能量供應至一外部射頻天線(諸如在該反應器頂部上該介電窗口外面具有一個或多個匝之平面或非平面線圈)，可於該反應器中產生一高密度電漿。該電漿產生源可係一模組安裝配置之一部分，其以真空密閉方式可移除地安裝在該反應器上端上。
可將一晶圓支撐於該反應器內一諸如懸臂夾盤配置等基板支架上，該懸臂夾盤配置由一模組安裝配置可移除地支撐於該反應器之一側壁上。該基板支架係處於以懸臂方式安裝的支撐臂之一末端處，使得可藉由使該組件穿過該反應器側壁中一開孔而自該反應器中移除整個基板支架/支撐臂組件。該基板支架可包括一諸如靜電夾盤等夾盤設備且該基板可由介電聚焦環環繞。該夾盤可包括一用於在蝕刻製成期間將射頻偏壓施加至該基板之射頻偏壓電極。由一氣體供應源供應之蝕刻氣體可通過該窗口與一下層氣體分佈板之間的通道流動並通過氣體分佈板中之氣體出口進入該室內部。該反應器亦可包括一自該氣體分佈板延伸之經加熱襯墊。
或者，如共同讓與之美國專利公開案第2003/0070620 A1號中所揭示，蝕刻氣體可由安裝在該介電窗口中之多區氣體注入器供應，該專利公開案之揭示內容以引用方式全部倂入本文。圖1a－b顯示包括同軸注入器出口124及軸外注入器出口126的多區氣體注入器，其中同軸注入器出口124給一中心區域供應製程氣體，該製程氣體在垂至於該基板表面之軸向方向上供應至該中心區域；而軸外注入器出口126給一鈍化層區域供應製程氣體，該製程氣體在不垂至於該基板之傾斜方向上供應至該鈍化層區域。為控制每一線路中之氣體流動，可將諸如可變流量限制裝置136a、136b等流動控制器放置在供應不同注入區之分離氣體線路之每一者中。裝置136a、136b可手動設定或藉由適當之電子控制器自動操作。藉由獨立地改變可變流量限制裝置136a、136b之設定值，可改變通過該兩個出口124、126之流量比率。替代實施方案包括多個出口及可變流量限制閥門及/或固定限制器及閥門之網路，其使得能夠將到達每一注入區之總傳導調節至一個或多個預定動態控制值。
在圖1a中，中心氣體注入出口124被顯示接續中心膛孔125。舉例而言，如美國專利第6,052,176號中所揭示，膛孔125之上端可由窗口127密封，窗口127經配置以與諸如燈、光譜計、光纖及透鏡配置等監視設備129通信，該美國專利之揭示內容以引用方式全部倂入本文。在此配置中，同軸出口124較佳地具有一大於軸外出口126之直徑。在圖1b中，同軸出口124具有一小於膛孔125之直徑。可選擇同軸出口124及軸外出口126之相對大小以達成合意之氣體流量分佈。舉例而言，軸外出口126之總橫截面積可小於、等於或大於同軸出口124之總橫截面積。
熟習此項技術者應瞭解，各種氣體之流速將相依於諸如電漿反應器類型、功率設定、反應器中真空壓力、電漿源離解速率等因素。
較佳地，將反應器壓力保持在適合於維持反應器中電漿之位凖。一般而言，過低的反應器壓力可導致電漿消失，而在高密度蝕刻反應器中，過高的反應器壓力可導致蝕刻停止問題。對於高密度電漿反應器，該反應器較佳地處於低於100 mTorr之壓力下。用於在TCPTM 反應器中產生高密度電漿之典型製程方案包括約450 W之功率、60 V之射頻偏壓、5－70 mT之壓力及50－1000 sccm之氣體流速。由於正經受蝕刻之半導體基板處之電漿限制，基板表面處之真空壓力可高於該反應器之真空壓力設定。
支撐該經受蝕刻之半導體基板的基板支架較佳充分冷卻該基板以防止諸如任何光阻劑在基板上燃燒及形成不期望之反應氣體自由基等有害副反應。在高密度電漿反應器中，使一流體在該基板支架中流動以保持－10至＋80攝氏度之基板溫度係足夠。該基板支架可包括一用於在處理期間向該基板供應一射頻偏壓之底部電極及一用於夾持該基板之ESC。舉例而言，該基板可包括一矽晶圓，該矽晶圓藉靜電夾持且藉由該晶圓與該ESC之頂表面之間以一所期望壓力供應氦(He)來控制其溫度。為將晶片保持在所期望溫度，可在晶片與夾盤之間之空間中將He維持在2至30 Torr之壓力。
可藉由通過該反應器頂部一介電窗口、通過舉例一接近介電窗口之側壁、通過一夾盤或通過一基板托架之外半徑注入該氣體在基板邊界處供應特定氣體化學品。具體而言，參照圖2，其顯示一可用於邊緣氣體注入之電漿室之實施例，特定氣體化學品可由注入器20通過電漿室之一側壁供應且沿流線21流動，而其他氣體化學品可由蓮蓬頭噴嘴23通過電漿室之頂篷供應及且沿流線24流動。儘管上文已描述各種用於在基板邊界處供應更多特定氣體化學品之注入設備之實例，任何能夠在該基板邊界處比在該基板中心處供應更多含矽氣體之合適氣體供應配置皆可用於參照圖3及圖4所描述之蝕刻製程。
圖3係一顯示一電漿蝕刻室中SiClx 之徑向濃度分佈之示意圖，其中用自Cl2 形成之電漿蝕刻一半導體基板上之矽層。因蝕刻反應310所致的SiClx 濃度在半導體基板320及反應器中心330上方達到峰值。隨著半徑增大，SiClx 物質之濃度由於SiClx 物質之向外唧送340及SiClx 物質損失至室壁350沉積反應而減小。
圖4係一顯示一電漿蝕刻室中SiClx 之徑向濃度分佈之示意圖，其中用自Cl2 形成之電漿蝕刻一半導體基板上之矽層且含矽氣體被供應至該電漿蝕刻室之周邊區域。類似於圖3，因蝕刻反應410所致之SiClx 濃度在半導體基板420及反應器中心430上方達到峰值，且隨著半徑增大，SiClx 物質之濃度由於SiClx 物質之向外唧送440及SiClx 物質損失至室壁450沉積反應而減小。然而，SiClx 濃度由於向電漿蝕刻室460之周邊區域供應含矽氣體而顯著地減小總SiClx 濃度470中之徑向變化。
不希望受任何理論束縛，據信總SiClx 濃度中徑向變化之減小改善了達到該半導體基板之鈍化物質通量之均勻度，從而改善該蝕刻製程之徑向臨界尺寸均勻度。更一般而言，一含矽鈍化物質鈍化經蝕刻形體之側壁。該含矽鈍化物質可由該電漿蝕刻產生(亦即來自該半導體基板)及/或可係在該第二氣體中之含矽氣體。較佳地，該蝕刻氣體含氯(諸如(例如)當電漿由Cl2 形成時)，且SiClx 鈍化經蝕刻形體之側壁。
雖然已描述各種實施例，應理解，如熟悉此項技術者所明瞭，可實施改變及修改。該等改變及修改被認為係屬於隨附申請專利範圍之範圍及範疇內。
20．．．注入器
21．．．流線
23．．．蓮蓬頭噴嘴
24．．．流線
124．．．同軸注入器出口
125．．．中心膛孔
126．．．軸外注入器出口
127．．．窗口
129．．．監視設備
136a．．．可變流量限制裝置
136b．．．可變流量限制裝置
310．．．蝕刻反應
320．．．半導體基板
330．．．反應器中心
340．．．向外唧送
350．．．室壁
410．．．蝕刻反應
420．．．半導體基板
430．．．反應器中心
440．．．向外唧送
450．．．室壁
460．．．電漿蝕刻室
470．．．總SiClx 濃度
圖1A－B顯示一雙區注入器之詳圖；圖2顯示一可用於邊緣氣體注入之電漿室之實施例；圖3係一顯示一電漿蝕刻室中SiClx 之徑向濃度分佈之示意圖，其中用自Cl2 形成之電漿蝕刻半導體基板上一矽層；且圖4係一顯示一電漿蝕刻室中SiClx 之徑向濃度分佈之示意圖，其中用自Cl2 形成之電漿蝕刻半導體基板上一矽層且含矽氣體被供應至該半導體基板上方一周邊區域。
124．．．同軸注入器出口
125．．．中心膛孔
126．．．軸外注入器出口
127．．．窗口
129．．．監視設備
136a．．．可變流量限制裝置
136b．．．可變流量限制裝置

Claims (19)

  1. 一種以經改善臨界尺寸均勻度蝕刻半導體基板之方法，其包括：將一半導體基板支撐於一電感耦合電漿蝕刻室中一基板支架上；將一第一蝕刻氣體供應至該半導體基板上方一中心區域，該第一蝕刻氣體包含一含矽氣體；將一包括至少一種含矽氣體之第二氣體供應至該半導體基板上方一環繞該中心區域之周邊區域，其中該第二氣體中矽之濃度大於該第一蝕刻氣體中矽之濃度；將該第一蝕刻氣體中一數量的矽相對於該第二氣體中一數量的矽做調整；藉由將射頻能量電感地耦合至該室中，自該第一蝕刻氣體及該第二氣體中產生一電漿；且使用該電漿對該半導體基板之一暴露表面進行電漿蝕刻，至少一含矽鈍化物質，其鈍化蝕刻至該半導體基板內之形體之側壁；以及該第一蝕刻氣體包含氯，且該含矽鈍化物質包含SiClx ，其中x為1、2、3或4。
  2. 如請求項1之方法，其包括電漿蝕刻該半導體基板之暴露表面中由至少一個開孔、通路、溝道及閥門結構組成之群組中選出之形體。
  3. 如請求項1之方法，其中該含矽鈍化物質由電漿蝕刻及 由該第二氣體產生。
  4. 如請求項1之方法，其中該含矽鈍化物質由該含矽氣體提供。
  5. 如請求項1之方法，其中該含矽氣體係選自由SiCl4 、SiHCl3 、SiH2 Cl2 、SiH3 Cl及其混合物組成之群組。
  6. 如請求項1之方法，其中該第二氣體進一步包括一惰性載氣。
  7. 如請求項6之方法，其中該惰性載氣係選自由He、Ne、Ar、Kr、Xe及其混合物組成之群組。
  8. 如請求項1之方法，其中該第二氣體進一步包含一蝕刻劑氣體。
  9. 如請求項8之方法，其中該蝕刻劑氣體係選自由Cl2 、CF、CF2 、CF3 、HBr、CF2 H2 、SF6 、HCl及其混合物組成之群組。
  10. 如請求項1之方法，其中該第二氣體進一步包括一鈍化氣體。
  11. 如請求項10之方法，其中該鈍化氣體係選自由O2 、N2 及其混合物組成之群組。
  12. 如請求項1之方法，其中藉由將射頻能量供應至平行於該半導體基板配置之平面線圈而藉由將射頻能量電感耦合至該電漿室中來產生電漿。
  13. 如請求項2之方法，其中接近該半導體基板中心之所蝕刻形體係與更接近於該晶圓邊緣之所蝕刻等效形體大致均等。
  14. 如請求項13之方法，其中該半導體基板係一300毫米晶圓且該等形體係小於50奈米且具有小於或等於1.5奈米3σ之非均勻度。
  15. 一種利用改善臨界尺寸均勻度蝕刻一半導體基板的方法，其包含：將一半導體基板支撐於一電感耦合電漿蝕刻室中一基板支架上；將一第一蝕刻氣體供應至該半導體基板上方一中心區域，該第一蝕刻氣體包含一含矽氣體；將一包括至少一種含矽氣體之第二氣體供應至該半導體基板上方一環繞該中心區域之周邊區域，其中該第二氣體中矽之濃度大於該第一蝕刻氣體中矽之濃度；將該第一蝕刻氣體中一數量的矽相對於該第二氣體中一數量的矽做調整；藉由將射頻能量電感地耦合至該室中，自該第一蝕刻氣體及該第二氣體中產生一電漿；且使用該電漿對該半導體基板之一暴露表面進行電漿蝕刻，其中該半導體基板之該暴露表面包含一矽層，以及其中該矽層包括一單晶矽晶圓之暴露區域、一應變型矽層或一矽鍺層之暴露區域。
  16. 如請求項15之方法，其中該矽層係在氮化矽、氧化矽或氧氮化矽、遮罩層下方。
  17. 如請求項15之方法，其中該矽層係在一下層閘極氧化物 及一上層硬或軟遮罩層或光阻劑之間。
  18. 如請求項17之方法，其中該矽層在一氮化矽、氧化矽或氧氮化矽遮罩層或光阻劑下方。
  19. 一種以經改善臨界尺寸均勻度蝕刻半導體基板之方法，其包括：將一半導體基板支撐於一電感耦合電漿蝕刻室中一基板支架上；將一第一蝕刻氣體供應至該半導體基板上方一中心區域，該第一蝕刻氣體包含一含矽氣體；將一包括至少一種含矽氣體之第二氣體供應至該半導體基板上方一環繞該中心區域之周邊區域，其中該第二氣體中矽之濃度大於該第一蝕刻氣體中矽之濃度；將該第一蝕刻氣體中一數量的矽相對於該第二氣體中一數量的矽做調整；藉由將射頻能量電感地耦合至該室中，自該第一蝕刻氣體及該第二氣體中產生一電漿；且使用該電漿對該半導體基板之一暴露表面進行電漿蝕刻，其中該第二氣體包含(i)SiCl4(ii)CxFy或CxFyHz及(iii)一惰性氣體之三者的一混合物。
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