DE69508273T2 - Verfahren zum ätzen von siliziumnitrid mit verstärkung der kritischen abmessung - Google Patents

Verfahren zum ätzen von siliziumnitrid mit verstärkung der kritischen abmessung

Info

Publication number
DE69508273T2
DE69508273T2 DE69508273T DE69508273T DE69508273T2 DE 69508273 T2 DE69508273 T2 DE 69508273T2 DE 69508273 T DE69508273 T DE 69508273T DE 69508273 T DE69508273 T DE 69508273T DE 69508273 T2 DE69508273 T2 DE 69508273T2
Authority
DE
Germany
Prior art keywords
reinforcement
silicon nitride
critical dimensions
etching silicon
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69508273T
Other languages
English (en)
Other versions
DE69508273D1 (de
Inventor
Maria Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69508273D1 publication Critical patent/DE69508273D1/de
Application granted granted Critical
Publication of DE69508273T2 publication Critical patent/DE69508273T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
DE69508273T 1994-11-18 1995-11-08 Verfahren zum ätzen von siliziumnitrid mit verstärkung der kritischen abmessung Expired - Lifetime DE69508273T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34217494A 1994-11-18 1994-11-18
PCT/US1995/014703 WO1996016437A1 (en) 1994-11-18 1995-11-08 Silicon nitride etch process with critical dimension gain

Publications (2)

Publication Number Publication Date
DE69508273D1 DE69508273D1 (de) 1999-04-15
DE69508273T2 true DE69508273T2 (de) 1999-11-04

Family

ID=23340690

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69508273T Expired - Lifetime DE69508273T2 (de) 1994-11-18 1995-11-08 Verfahren zum ätzen von siliziumnitrid mit verstärkung der kritischen abmessung

Country Status (4)

Country Link
US (1) US6593245B1 (de)
EP (1) EP0792516B1 (de)
DE (1) DE69508273T2 (de)
WO (1) WO1996016437A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926690A (en) * 1997-05-28 1999-07-20 Advanced Micro Devices, Inc. Run-to-run control process for controlling critical dimensions
EP1014434B1 (de) * 1998-12-24 2008-03-26 ATMEL Germany GmbH Verfahren zum anisotropen plasmachemischen Trockenätzen von Siliziumnitrid-Schichten mittels eines Fluor-enthaltenden Gasgemisches
US7932181B2 (en) * 2006-06-20 2011-04-26 Lam Research Corporation Edge gas injection for critical dimension uniformity improvement
US8614151B2 (en) 2008-01-04 2013-12-24 Micron Technology, Inc. Method of etching a high aspect ratio contact

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4028155A (en) 1974-02-28 1977-06-07 Lfe Corporation Process and material for manufacturing thin film integrated circuits
DE3164742D1 (en) 1980-09-22 1984-08-16 Tokyo Shibaura Electric Co Method of smoothing an insulating layer formed on a semiconductor body
DE3420347A1 (de) 1983-06-01 1984-12-06 Hitachi, Ltd., Tokio/Tokyo Gas und verfahren zum selektiven aetzen von siliciumnitrid
JPH0642510B2 (ja) * 1983-06-13 1994-06-01 エヌ・シー・アール・インターナショナル・インコーポレイテッド 半導体構造の形成方法
US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
IT1213230B (it) * 1984-10-23 1989-12-14 Ates Componenti Elettron Processo planox a becco ridotto per la formazione di componenti elettronici integrati.
JPH07118474B2 (ja) * 1984-12-17 1995-12-18 ソニー株式会社 エツチングガス及びこれを用いたエツチング方法
US4966870A (en) * 1988-04-14 1990-10-30 International Business Machines Corporation Method for making borderless contacts
EP0337109A1 (de) * 1988-04-14 1989-10-18 International Business Machines Corporation Verfahren zum Herstellen von Kontakten
US4836885A (en) * 1988-05-03 1989-06-06 International Business Machines Corporation Planarization process for wide trench isolation
JP3033104B2 (ja) 1989-11-17 2000-04-17 ソニー株式会社 エッチング方法
JP2663739B2 (ja) * 1991-04-08 1997-10-15 日本電気株式会社 半導体装置の製造方法
US5217567A (en) 1992-02-27 1993-06-08 International Business Machines Corporation Selective etching process for boron nitride films

Also Published As

Publication number Publication date
EP0792516B1 (de) 1999-03-10
DE69508273D1 (de) 1999-04-15
WO1996016437A1 (en) 1996-05-30
US6593245B1 (en) 2003-07-15
EP0792516A1 (de) 1997-09-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SPANSION LLC (N.D.GES.D. STAATES DELAWARE), SU, US