TWI397616B - 利用有機表面鈍化及微差電鍍延遲進行由底部往上電鍍 - Google Patents

利用有機表面鈍化及微差電鍍延遲進行由底部往上電鍍 Download PDF

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Publication number
TWI397616B
TWI397616B TW098139365A TW98139365A TWI397616B TW I397616 B TWI397616 B TW I397616B TW 098139365 A TW098139365 A TW 098139365A TW 98139365 A TW98139365 A TW 98139365A TW I397616 B TWI397616 B TW I397616B
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TW
Taiwan
Prior art keywords
substrate
passivation film
trench
via structure
seed layer
Prior art date
Application number
TW098139365A
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English (en)
Chinese (zh)
Other versions
TW201026911A (en
Inventor
Jenn-Yue Phillip Wang
Hua Chung
Rong Tao
Hong Zhang
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Applied Materials Inc
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Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of TW201026911A publication Critical patent/TW201026911A/zh
Application granted granted Critical
Publication of TWI397616B publication Critical patent/TWI397616B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1052—Formation of thin functional dielectric layers
    • H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
    • H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemically Coating (AREA)
TW098139365A 2008-11-24 2009-11-19 利用有機表面鈍化及微差電鍍延遲進行由底部往上電鍍 TWI397616B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11754008P 2008-11-24 2008-11-24

Publications (2)

Publication Number Publication Date
TW201026911A TW201026911A (en) 2010-07-16
TWI397616B true TWI397616B (zh) 2013-06-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW098139365A TWI397616B (zh) 2008-11-24 2009-11-19 利用有機表面鈍化及微差電鍍延遲進行由底部往上電鍍

Country Status (6)

Country Link
US (1) US8293647B2 (enExample)
JP (1) JP5409801B2 (enExample)
KR (1) KR101368308B1 (enExample)
CN (1) CN102224574B (enExample)
TW (1) TWI397616B (enExample)
WO (1) WO2010059857A2 (enExample)

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US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
JP5667485B2 (ja) * 2011-03-17 2015-02-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法、及び半導体装置
US20130051530A1 (en) * 2011-08-30 2013-02-28 Fujifilm Corporation High Aspect Ratio Grid for Phase Contrast X-ray Imaging and Method of Making the Same
CN102798471B (zh) * 2011-10-19 2015-08-12 清华大学 一种红外探测器及其制备方法
US8754531B2 (en) * 2012-03-14 2014-06-17 Nanya Technology Corp. Through-silicon via with a non-continuous dielectric layer
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
JP6273257B2 (ja) 2012-03-27 2018-01-31 ノベラス・システムズ・インコーポレーテッドＮｏｖｅｌｌｕｓ Ｓｙｓｔｅｍｓ Ｉｎｃｏｒｐｏｒａｔｅｄ タングステンによるフィーチャ充填
US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR101972969B1 (ko) * 2012-08-20 2019-04-29 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
CN104112697B (zh) * 2013-04-18 2017-09-15 中芯国际集成电路制造(上海)有限公司 一种改善铜填充质量的方法
JP6187008B2 (ja) * 2013-08-07 2017-08-30 大日本印刷株式会社 金属充填構造体の製造方法及び金属充填構造体
US9899234B2 (en) 2014-06-30 2018-02-20 Lam Research Corporation Liner and barrier applications for subtractive metal integration
US9349637B2 (en) * 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9859124B2 (en) * 2015-04-17 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd Method of manufacturing semiconductor device with recess
US10170320B2 (en) 2015-05-18 2019-01-01 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US20160351493A1 (en) * 2015-05-27 2016-12-01 Macronix International Co., Ltd. Semiconductor device and manufacturing method for the same
US11028477B2 (en) * 2015-10-23 2021-06-08 Applied Materials, Inc. Bottom-up gap-fill by surface poisoning treatment
US10438847B2 (en) 2016-05-13 2019-10-08 Lam Research Corporation Manganese barrier and adhesion layers for cobalt
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
US10242879B2 (en) 2017-04-20 2019-03-26 Lam Research Corporation Methods and apparatus for forming smooth and conformal cobalt film by atomic layer deposition
KR102828798B1 (ko) 2018-12-05 2025-07-02 램 리써치 코포레이션 보이드 프리 (void free) 저응력 (low stress) 충진
SG11202108725XA (en) 2019-02-13 2021-09-29 Lam Res Corp Tungsten feature fill with inhibition control
KR102890997B1 (ko) * 2019-06-18 2025-11-25 도쿄엘렉트론가부시키가이샤 기판 처리 방법 및 기판 처리 장치

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Also Published As

Publication number Publication date
JP5409801B2 (ja) 2014-02-05
CN102224574B (zh) 2014-06-11
CN102224574A (zh) 2011-10-19
JP2012510162A (ja) 2012-04-26
TW201026911A (en) 2010-07-16
KR101368308B1 (ko) 2014-02-26
WO2010059857A2 (en) 2010-05-27
WO2010059857A3 (en) 2010-08-19
US20100130007A1 (en) 2010-05-27
KR20110102374A (ko) 2011-09-16
US8293647B2 (en) 2012-10-23

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