WO2010059857A2 - Bottom up plating by organic surface passivation and differential plating retardation - Google Patents

Bottom up plating by organic surface passivation and differential plating retardation Download PDF

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Publication number
WO2010059857A2
WO2010059857A2 PCT/US2009/065193 US2009065193W WO2010059857A2 WO 2010059857 A2 WO2010059857 A2 WO 2010059857A2 US 2009065193 W US2009065193 W US 2009065193W WO 2010059857 A2 WO2010059857 A2 WO 2010059857A2
Authority
WO
WIPO (PCT)
Prior art keywords
trench
substrate
seed layer
passivation film
via structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2009/065193
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English (en)
French (fr)
Other versions
WO2010059857A3 (en
Inventor
Jenn-Yue Wang
Hua Chung
Rong Tao
Hong Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to JP2011537626A priority Critical patent/JP5409801B2/ja
Priority to CN200980147108.0A priority patent/CN102224574B/zh
Priority to KR1020117014681A priority patent/KR101368308B1/ko
Publication of WO2010059857A2 publication Critical patent/WO2010059857A2/en
Publication of WO2010059857A3 publication Critical patent/WO2010059857A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1052—Formation of thin functional dielectric layers
    • H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
    • H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric

Definitions

  • Embodiments of the present invention generally relate to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for performing a bottom up plating.
  • trench or via structures formed on a semiconductor substrate during fabrication become increasingly narrow and high in aspect ratio.
  • Narrow opening and high aspect ratio usually present difficulties and challenges for subsequent material filling process.
  • voids are more likely to form in the filling material because the narrow openings would be pinched off during filling process.
  • the seed layer is usually deposited on the trench or via structure using a physical vapor deposition (PVD) process.
  • PVD physical vapor deposition
  • the seed layer is usually thicker near an entrance of the trench or via and near a bottom of the trench or via.
  • the thick portion of the seed layer has smaller electrical resistance, therefore attracting more plating current and resulting in quick plating.
  • plating is faster near the opening of the trench or via and material plated near the opening pinches off the opening before the trench or via is filled, forming voids in the trench or via.
  • FIG. 1 schematically illustrates problems in plating trench and via.
  • Trench or via structures 14 are formed in a dielectric material 11 of a substrate 10.
  • a barrier layer 16 is then deposited over the trench or via structures 14.
  • a seed layer 12 is then deposited over the barrier layer 16.
  • the seed layer 16 is thicker near entrances 17 of the trench or via structures 14 resulting in faster plating near the entrances 17.
  • a metal layer 13 is then deposited to fill the trench or via structures 14.
  • voids 15 are formed in trench or via structures 14 with high aspect ratio during deposition of the metal layer 13.
  • Conventional fabrication process generally uses a sputtering process to reduce the thickness of the seed layer 12 near the entrances 17 prior to plating.
  • Sputtering generally uses positive ions to physically knock out atoms in the seed layer.
  • the positive ions such as positive argon ions, are usually generated in a plasma chamber and then accelerated towards the target.
  • the positive ions gain momentum during acceleration and strike top surfaces of the substrate.
  • the ions physically knock out atoms in the seed layer.
  • the ions strike the entire substrate. Additionally, the dislodged particles generated during sputtering require additional cleaning process and may still become potential source of contamination for subsequent processing.
  • Embodiments of the present invention generally relate to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relate to methods and apparatus facilitating a bottom up trench or via structure filling.
  • One embodiment provides a method for processing a substrate comprising forming a seed layer over a substrate having trench or via structures formed therein, coating a portion of the seed layer with an organic passivation film, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the organic passivation film.
  • Another embodiment provides a method for processing a substrate comprising depositing a seed layer over surfaces of trench or via structures formed in the substrate, applying a passivation film over the substrate to cover the seed layer near top openings of the trench or via structures, and plating a conductive material in the trench or via structures by immersing the trench or via structures in a plating solution, wherein the passivation film dissolves in the plating solution during plating.
  • Yet another embodiment provides a method processing a substrate comprising depositing a seed layer on a substrate having trench or via structures formed therein, spinning coating the substrate to form a passivation film over at least a portion of the seed layer, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the passivation film and to dissolve the passivation film in the plating solution.
  • Figure 1 schematically illustrates problems in plating trench and via structures.
  • Figure 7 is a schematic flow chart of a process for filling trench or via structures in accordance with one embodiment of the present invention.
  • Block 240 of the process 200 comprises coating a portion of the seed layer with a passivation film.
  • the passivation film is coated over the seed layer on upper portions of the trench or via structures.
  • the passivation film is configured to prevent metal deposition over the seed layer underneath.
  • the passivation film comprises a surface acting agent, also known as surfactant.
  • the passivation film 104 may comprise an anti- corrosion agent for materials comprised in the seed layer 103.
  • the anti-corrosion agent comprise imidazole (IMA).
  • Figure 2A shows a passivation film 104 formed over top portions of the trench or via structures 106.
  • the seed layer 103 on lower portions of the trench or via structures 106 are not covered by the passivation film 104.
  • FIG. 2B schematically illustrates a sectional side view of the substrate 100 after being plated for a while.
  • the conductive material 107 has filled bottom portions of the trench or via structures 106, while the top portions of the trench or via structures 106 remaining under the cover of the passivation film 104.
  • the passivation film 104 is dissolving into the plating solution 105.
  • the passivation film 104 would eventually dissolve completely in the plating solution 104, and allow deposition of the conductive material 107 over the top portions of the trench or via structures 106, as shown in Figure 2D.
  • FIGS 4A-4C schematically illustrate a method for applying a passivation film in accordance with one embodiment of the present invention.
  • the passivation film may be a layer of surfactant applied by spinning coating. Due to centrifugal force in the spinning coating process, the applied passivation film may have a diminishing thickness profile from top of the trench or via structure to the bottom of the trench or via structure. High rotation rate results in little or no coating at the bottom of the trench or via structure.
  • the physical properties of solution also play an equivalent role in delivering protective surfactant into structure for intended depth.
  • the bottom surface of the trench or via structure exposes to the electrolyte first when the surfactant covers top surfaces of the trench or via structure before the surfactant dissolves. Therefore, a bottom-up plating can be achieve.
  • the liquid solution 303 generally comprises a carrier and a solute, such as such as a surfactant or an anti corrosion agent.
  • the carrier may comprise isopropyl alcohol (IPA).
  • the depth 307 of the thin layer 305 in the trench or via structures 306 may be controlled by adjusting properties of a carrier of the liquid solution 303. In one embodiment, the depth 307 may be increased by selecting a more hydrophilic or volatile carrier. . In one embodiment, the depth 307 may be adjusted by adjusting viscosity of the carrier.
  • the depth 307 of the thin layer 305 in the trench or via structures 306 may be controlled by adjusting properties of a solute of the liquid solution 303.
  • the properties of the solute usually changes the properties of the liquid solution.
  • the carrier vaporizes after spinning coating, leaving the solute remaining on the substrate 302 in the thin layer 305.
  • the thin layer 305 may comprise several molecule layers of the solute, such as a surfactant or an anti corrosion agent.
  • the substrate 302 may be baked after spinning coating to vaporize the carrier from the thin layer 305.
  • FIG. 5 schematically illustrates applying a passivation film by dipping a substrate in a liquid solution.
  • a substrate 401 having trench or via structures 403 formed therein may be faced down and dipped into a liquid solution 402 to form a passivation film, such as the passivation film 104 of Figure 2A.
  • the liquid solution 402 generally has a hydrophobic carrier to obtain a thin film over upper portions (portions near entrances of the trench or via structures) of the trench or via structures.
  • Figures 6A-6D schematically illustrate a method for filling trench or via structures with various dimension in accordance with one embodiment of the present invention.
  • Figure 7 is a schematic flow chart of a process 600 for filling trench or via structures in accordance with the method showing in Figures 6A-6D.
  • Block 610 of the process 600 comprises depositing a seed layer over a substrate having trench or via structures of different dimension.
  • a large trench or via structure 506 and a small trench or via structure 505 are formed in a dielectric material 501 of a substrate 500.
  • a barrier layer 507 is deposited over surfaces of the trench or via structures 505, 506.
  • a seed layer 502 is deposited over the barrier layer 507.
  • the seed layer 502 may be deposited using physical vapor deposition (PVD).
  • PVD physical vapor deposition
  • Block 620 of the process 600 comprises coating a portion of the seed layer with a passivation film.
  • the passivation film may be coated over the seed layer on upper portions of the trench or via structures.
  • the passivation film is configured to prevent metal deposition over the seed layer underneath.
  • the passivation film comprises a surfactant.
  • the passivation film may be formed by spinning coating or by dipping the substrate in a liquid solution, as discussed above with Figures 4 and 5. As shown in Figure 6A, a passivation film 503 is formed over upper portions of the trench or via structures 505, 506.
  • Block 630 of the process 600 comprises filling the trench or via structures with a conductive material.
  • filling the trench or via structures are performed by immersing the trench or via structures in a plating solution. Similar to the plating process described in the process 200, the passivation film enables a bottom up filling effect in trench or via structures by retarding plating on upper portions of the trench or via structures.
  • Figure 6B illustrates a plating result after the substrate 500 has been immersed in a plating solution for a while.
  • the small trench or via structure 505, having a high aspect ratio, is mostly filled up by a conductive material 504, while the large trench or via structure 506 still have a majority of inner volume unfilled.
  • the passivation film 503 may still remain over the seed layer 502.
  • the substrate 500 can remain in the plating solution till the large trench or via structure 506 is also filled if the passivation film 503 is dissolvable in the plating solution.
  • a plating rate is generally set at a low value when filling high aspect ratio trench or via structures to reduce void formation. After the small trench or via structure 505 is filled, it is not necessarily to remain the low plating rate. Therefore, it is desirable to change the plating parameters for an increase plating rate in filling the large trench or via structure 506.
  • Block 640 of the process 600 comprises drying the substrate after narrow trench or via structures are filled with a conductive material.
  • the process 600 is also useful when the passivation film is not dissolvable in the plating solution.
  • Figure 8 is an optical microscope image of via filling result in accordance with one embodiment of the present invention.
  • the vias in Figure 8 are formed in a silicon substrate and have a depth of about 140 microns and a diameter of about 14 microns.
  • a copper seed layer having a thickness of about 6000 angstroms is deposited prior to passivation coating.
  • passivation coating a liquid solution of 1- 2-3-Benzotriazole (BTA) dissolved in isopropyl alcohol (IPA) is spinning coated over the substrate. The coated substrate is then immersed in a plating solution configured to plate copper on the substrate.
  • Figure 8 is an image after the plating.
  • the copper body is shown in white.
  • the vias are filled with copper in a bottom up manner.
  • Figure 9 is a transmission electron microscopy image of filling results of trench structures using a method in accordance with one embodiment of the present invention.
  • the trench structures have a critical dimension of 25nm near the bottoms.
  • the trenches are filled by copper in an electroplating process after a passivation coating is applied in accordance with embodiments of the present invention.
  • the trenches are filled from bottom up. It can be observed that the electroplated copper "spill" out of the trenches like mushrooms, while the original copper seed layer remains intact.
  • trench or via structure filling is described in the present application, embodiments of the present invention are applicable in filling other structures, such as trench and via combinations, or any other openings.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemically Coating (AREA)
PCT/US2009/065193 2008-11-24 2009-11-19 Bottom up plating by organic surface passivation and differential plating retardation Ceased WO2010059857A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2011537626A JP5409801B2 (ja) 2008-11-24 2009-11-19 有機表面パッシベーションでめっきの進行に差を付けて遅らせることによるボトムアップめっき
CN200980147108.0A CN102224574B (zh) 2008-11-24 2009-11-19 利用有机表面钝化及微差电镀延迟进行由底部往上镀层的方法
KR1020117014681A KR101368308B1 (ko) 2008-11-24 2009-11-19 유기 표면 패시베이션에 의한 바텀 업 도금 및 차등 도금 지연

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11754008P 2008-11-24 2008-11-24
US61/117,540 2008-11-24
US12/620,818 2009-11-18
US12/620,818 US8293647B2 (en) 2008-11-24 2009-11-18 Bottom up plating by organic surface passivation and differential plating retardation

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WO2010059857A2 true WO2010059857A2 (en) 2010-05-27
WO2010059857A3 WO2010059857A3 (en) 2010-08-19

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PCT/US2009/065193 Ceased WO2010059857A2 (en) 2008-11-24 2009-11-19 Bottom up plating by organic surface passivation and differential plating retardation

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US (1) US8293647B2 (enExample)
JP (1) JP5409801B2 (enExample)
KR (1) KR101368308B1 (enExample)
CN (1) CN102224574B (enExample)
TW (1) TWI397616B (enExample)
WO (1) WO2010059857A2 (enExample)

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CN102224574B (zh) 2014-06-11
CN102224574A (zh) 2011-10-19
JP2012510162A (ja) 2012-04-26
TWI397616B (zh) 2013-06-01
TW201026911A (en) 2010-07-16
KR101368308B1 (ko) 2014-02-26
WO2010059857A3 (en) 2010-08-19
US20100130007A1 (en) 2010-05-27
KR20110102374A (ko) 2011-09-16
US8293647B2 (en) 2012-10-23

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