TWI385738B - Method for Eliminating Bubble of Adhesive Adhesive Layer in Semiconductor Packaging - Google Patents

Method for Eliminating Bubble of Adhesive Adhesive Layer in Semiconductor Packaging Download PDF

Info

Publication number
TWI385738B
TWI385738B TW096142523A TW96142523A TWI385738B TW I385738 B TWI385738 B TW I385738B TW 096142523 A TW096142523 A TW 096142523A TW 96142523 A TW96142523 A TW 96142523A TW I385738 B TWI385738 B TW I385738B
Authority
TW
Taiwan
Prior art keywords
wafer
semiconductor
bubble
adhesive
adhesive material
Prior art date
Application number
TW096142523A
Other languages
English (en)
Other versions
TW200921808A (en
Original Assignee
Ableprint Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ableprint Technology Co Ltd filed Critical Ableprint Technology Co Ltd
Priority to TW096142523A priority Critical patent/TWI385738B/zh
Priority to US12/289,809 priority patent/US7863094B2/en
Publication of TW200921808A publication Critical patent/TW200921808A/zh
Application granted granted Critical
Publication of TWI385738B publication Critical patent/TWI385738B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/8388—Hardening the adhesive by cooling, e.g. for thermoplastics or hot-melt adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

半導體封裝之晶片黏著膠層氣泡排除方法
本發明係關於一種半導體封裝製程之設計，特別是關於一種半導體封裝之晶片黏著膠層氣泡排除方法。
半導體晶片封裝之功能主要有提供電能輸入、信號溝通、散熱功能與保護功能四大部分。若半導體晶片要有動作則需要有外來的電源來驅動，而外來的電源的供應必須藉由半導體晶片封裝以分佈於半導體晶片，提供穩定地電源的供應去驅動半導體晶片而運作。半導體晶片封裝亦可提供信號溝通的連線。半導體晶片所產生的訊號或由外界輸入半導體晶片中的訊號均需透過封裝過程中所佈設之線路來傳送，而構成布設之線路最主要者即為載板。
半導體晶片無論是接受外界輸入的訊號或是在運作時都會產生大量的熱能，藉由半導體晶片封裝設計中的熱傳設計，將系統運作中所產生的熱能有效率的去除使半導體晶片可在正常工作溫度下運作。然而若是封裝中存在氣泡則系統運作中所產生的熱將導致氣泡中所蘊含之水氣受熱膨脹而直接影響產品的可靠性與品質因此封裝製程中的氣泡去除一直是重要的工作。
習知之半導體晶片封裝過程中，必須先從晶圓切割出適當大小之晶片後再黏附於載板上。於黏附之過程中，膠著材料中、膠著材料與載板或晶片界面間、或於膠著材料老化的過程中會產生許多氣泡，造成老化後之膠著材料中會有空腔而影響產品的可靠度、品質甚至功能。
傳統之方法有利用模壓膠體成型過程中短暫的高溫高壓條件，使膠著材料之膠層氣泡排出。或是藉由真空方式使氣泡由膠著材料之膠層中排除。或是藉由調整上晶片機之製程參數及製具使晶片與膠著材料界面間達到無氣泡。
然以上所知之習用技術卻仍各有其缺點以模壓膠體成型方式因乃是利用短暫的高溫高壓條件施予已經老化或相當程度老化的膠著材料因此擁有較窄之製程條件，且對較大面積晶片因其短暫的特性往往效果是有限的。
以真空方式使氣泡由膠著材料之膠層中排除，通常僅限於膠著材料為膠狀類(paste)而非膠膜類(film)其使用範圍更為侷限，而且效果相當程度為材料所影響，因此製程條件相當窄小。
以調整上晶片機之製程方法為達到黏著界面無空隙，上晶片機參數中的所施予的晶片溫度、上片力量與力量停留時間為其經常施實的方法。但為達到上片時的膠著界面溼潤度，溫度提高、增加上片力量及增加上片力量停留時間都是經常施實的方向。
然而這些方向都不利於晶片品質或導致生產效率降低。此外對存在於膠著材料中的氣泡此方法是無效的。另外當遇上愈大面積晶片其效果也就愈差。
緣此，本發明之主要目的即是提供一種可提高排除膠層中氣泡效果之方法，用以將氣泡由膠著材料中及膠著材料與晶片或載板黏著界面間排出。
本發明之另一目的是提供一種提高產能之半導體封裝製程之方法。
本發明為解決習知技術之問題所採用之技術手段係先將半導體晶片之其中一面以膠著材料黏於載板，膠著材料係可為具有熱塑(Thermoplastic)或與具熱固(Thermosetting)性質之合成樹酯(Synthetic resin)如聚亞醯胺(Polyimide)、環氧樹酯(Epoxy resin)與丙烯酸樹酯(Acryl resin)等在材料未老化前加熱具黏性特質的材料。
在膠著材料尚未老化或未完全老化前，將上晶片完成之載板承置於一特定的處理槽中。針對此一特定處理槽的環境條件可做一設定，且使承置於處理槽中之黏附有半導體晶片之載板可在一預定的時間內，較佳地為大於5分鐘，維持在一具有預定升溫速度、預定溫度，較佳地為介於攝氏80度至175度之間，以及預定壓力，較佳地為大於2個大氣壓，之槽室環境中。
利用處理槽所設定之環境條件，將存在於膠著材料中或與黏著物界面間之氣泡經由氣泡能量之激化(Antonie equation，描述飽和蒸汽壓與溫度的關係)、密閉空間裡體積、溫度、壓力之變化之必然現象(理想氣體方程式)、氣泡膨脹壓力與槽內所施加壓力之平衡結果而自然排出。
本發明之較佳實施例中，經過排除膠層氣泡的處理後可將自處理槽中取出之半導體第一晶片實施封裝製程中之打線作業。於半導體晶片表面上所設置之銲點處焊接金屬線至載板表面上所預設之接觸點，並繼續完成半導體封裝後續之步驟。
本發明之另一實施例中，已實施完打線作業之第一晶片半成品持續以另一第二晶片利用膠著材料黏著於原先第一晶片之上並反覆上述製程，置入處理槽中進行氣泡之去除及老化、取出後進行打線作業。若有後續第三、第四等晶片皆可依序實施進行氣泡移除之作業。
經由本發明所採用之技術手段，於膠著材料未老化或未完全老化前利用一可在預定的時間內維持於一具有預定升溫速率、預定溫度及預定壓力之處理槽環境中，用以將氣泡由膠著材料中及膠著材料與晶片或載板黏著界面四周排出。
本發明之膠著材料氣泡排除方法可無視於氣泡之多寡、大小以及晶片之大小而適用於排除不同面積晶片之膠層氣泡，以減少習知方法中利用增加晶片加壓黏附於載板或上晶片之時間與力量去排除膠層中氣泡之方法所需之時間。此外，即使於黏附過程中有氣泡產生也可經由後續本發明之膠著材料氣泡排除方法有效排除。
本發明半導體封裝之晶片黏著膠層氣泡排除方法能廣泛配合具有一定要求之材料特質所產生之製程條件且可無視於上晶片時氣泡之存在，因此上晶片時所需要之溫度、壓力與時間均可有效縮短與降低使半導體封裝之產能得以提高，更可以節省投資設備與成本。
本發明所採用的具體實施例，將藉由以下之實施例及附呈圖式作進一步之說明。
參閱第1圖所示，其係顯示本發明半導體封裝之晶片黏著膠層氣泡排除方法之流程圖，用以說明本發明所設計之膠著材料其膠層中之氣泡排除方法。
載板1可為基板或導線架等各種可以承載晶片用以聯繫外部電子訊號用之承載物，且於載板1表面上預設有複數個晶片固定區11(如第2圖所示)。
首先，將製備好之半導體晶片2其中一面(如第3圖所示)藉由先塗佈於晶片固定區11之膠著材料12以黏附於載板1表面之晶片固定區11中(步驟101)。
亦可於載板1a之晶片固定區11中設置有一貫穿載板1a之金屬線貫孔111。膠著材料12可先塗佈於晶片固定區11，再將半導體晶片2黏著於載板1a之晶片固定區11(如第4圖所示)。
於步驟101中，膠著材料12也可不必事先塗佈於晶片固定區11而是以附著於半導體晶片2之上的方式連同半導體晶片2一併黏著於載板1其上。
從步驟102至105，以載板1為實例說明，而載板1a同樣適用於步驟102至105。
載板1之表面上已黏附有複數個上片完成之半導體晶片2、2a、2b、2c(如第5圖所示)，且於半導體晶片2、2a、2b、2c與載板1表面之間之膠著材料12未老化或未完全老化前，將黏附有半導體晶片2、2a、2b、2c之載板1承置在一處理槽4(如第6圖所示)中(步驟102)。
膠著材料12於黏著過程中，會在膠著材料12之膠層中、膠著材料12與載板1之交界面或是與半導體晶片2之交界面處會有例如第7圖中所示之膠層中氣泡51或是交界面之氣泡52、53的產生。氣泡51、52、53會使得膠著材料12所形成之膠層為一不連續面如第8圖中所示。
為解決氣泡51、52、53形成之問題，本發明之設計中之處理槽4可針對環境條件做一設定，且使承置於處理槽4中之黏附有半導體晶片2、2a、2b、2c之載板1在預定的時間中，較佳地為大於5分鐘，以一預定升溫速率維持於一具有預定溫度，較佳地為介於攝氏80度至175度之間，以及預定壓力，較佳地為大於2個大氣壓，之槽室環境中(步驟103)。
藉由處理槽4所設定之環境條件，將存在於膠著材料12中之氣泡51、膠著材料12與載板1交界面之氣泡52與膠著材料12與半導體晶片2交界面之氣泡53由膠著材料12如第7圖中箭頭所指示之方向往四周排出(步驟104)。
將經過本發明之膠層氣泡排除方法處理後之載板1連同黏附於載板1表面之半導體晶片2一同移出處理槽4(步驟105)。
排除膠著材料12中之膠層氣泡後，載板1所黏附之半導體晶片3(如第9圖所示)其晶片表面31上設置有一銲點(Bond Pad)321、322，且銲點321、322可焊接金屬線331、332並經過打線(Bonding)處理連接於載板1表面上所預設之接觸點341、342(步驟106)。
於執行完步驟106後，半導體晶片3繼續完成半導體封裝之後續步驟。於半導體晶片3之晶片表面31藉由一模具裝置(未示)，以合模注膠方式去模壓形成一封裝膠體6(如第10圖中所示)於半導體晶片3外(步驟107)。
模壓後所形成於半導體晶片3外之封裝膠體6，需經過一烘烤處理(Post mold cure)造成封裝膠體6開始老化。老化完全之封裝膠體6即可模封該半導體晶片3(步驟108)，用以防止濕氣由外部侵入半導體晶片3。
步驟106中，亦可於載板1a所黏附之半導體晶片7(如第11圖)排除膠著材料12中之膠層氣泡後，半導體晶片7其晶片表面71上設置有一銲點721、722，且銲點721、722可焊接金屬線731、732。金屬線731、732藉由打線處理並通經過金屬線貫孔111後，連接於載板1a所預設之接觸點741、742。最後以合模注膠方式去模壓形成一封裝膠體6a(如第12圖中所示)於半導體晶片7外。
本發明半導體封裝之晶片黏著膠層氣泡排除方法亦可應用於多顆疊置晶片封裝結構中。其製程步驟參閱第1圖，當第一晶片例如半導體晶片3完成打線處理(步驟106)後，欲疊置多顆晶片則僅需重複半導體封裝製程步驟101至106即可。
於載板1表面上黏附之完成打線處理的半導體晶片3其晶片表面31處以另一黏附有膠著材料13之第二晶片例如半導體晶片8疊置於第一晶片之半導體晶片3上(如第13圖中所示)，再將此半成品置入處理槽4中進行排除膠層中之氣泡。
進行完氣泡排除後的半成品，於半導體晶片8其晶片表面81上設置之銲點821、822焊接一金屬線831、832，並再經過打線處理連接於載板1表面上所預設之接觸點841、842並接續打線處理，最後以合模注膠方式去模壓形成一封裝膠體6b於半導體晶片3、8外。
亦可於載板1a表面上黏附之完成打線處理的半導體晶片7其晶片表面71處於以另一黏附有膠著材料13之第二晶片例如半導體晶片9疊置於第一晶片之半導體晶片7上(第14圖中所示)，再將此半成品置入處理槽4中進行排除膠層中之氣泡。
進行完氣泡排除後的半成品，於半導體晶片9其晶片表面91上設置之銲點921、922焊接一金屬線931、932，並再經過打線處理連接於載板1a上所預設之接觸點941、942，並接續打線處理，最後以合模注膠方式去模壓形成一封裝膠體6c於半導體晶片7、9外。
由以上之實施例可知，本發明所提供之半導體封裝之晶片黏著膠層氣泡排除方法確具產業上之利用價值，故本發明業已符合於專利之要件。惟以上之敘述僅為本發明之較佳實施例說明，凡精於此項技藝者當可依據上述之說明而作其它種種之改良，惟這些改變仍屬於本發明之發明精神及以下所界定之專利範圍中。
1、1a．．．載板
11．．．晶片固定區
111．．．金屬線貫孔
12、13．．．膠著材料
2、2a、2b、2c、3、7、8、9．．．半導體晶片
31、71、81、91．．．晶片表面
321、322、721、722、821、822、921、922．．．焊點
331、332、731、732、831、832、931、932．．．金屬線
341、342、741、742、841、842、941、942．．．接觸點
4．．．處理槽
51、52、53．．．氣泡
6、6a、6b、6c．．．封裝膠體
第1圖係顯示本發明半導體封裝之晶片黏著膠層氣泡排除方法之流程圖；第2圖係顯示本發明第一實施例之載板與晶片固定區示意圖；第3圖係顯示本發明第一實施例之半導體晶片黏附位置示意圖；第4圖係顯示本發明第二實施例之半導體晶片黏附位置示意圖；第5圖係顯示第一實施例之複數個半導體晶片與載板之縱剖圖；第6圖係顯示第一實施例之半導體晶片與載板承置於處理槽之縱剖圖；第7圖係顯示第一實施例之膠層氣泡、半導體晶片與載板之縱剖圖；第8圖係顯示第7圖實施例中之膠層氣泡8－8橫剖圖；第9圖係顯示第一實施例之單一打線處理之半導體晶片之縱剖圖；第10圖係顯示第一實施例之單一晶片模封結構之縱剖圖；第11圖係顯示第二實施例之單一打線處理之半導體晶片之縱剖圖；第12圖係顯示第二實施例之單一晶片模封結構之縱剖圖；第13圖係顯示第一實施例之疊置晶片模封結構之縱剖圖；第14圖係顯示第二實施例之疊置晶片模封結構之縱剖圖。
1．．．載板
12．．．膠著材料
2．．．半導體晶片
51、52、53．．．氣泡
8．．．半導體晶片

Claims (9)

  1. 一種半導體封裝之晶片黏著膠層氣泡排除方法，包括下列步驟：(a)將至少一個製備好之半導體晶片之其中一面以膠著材料黏附在一載板之表面；(b)在該膠著材料於未老化或未完全老化前，將該黏附有半導體晶片之載板承置在一處理槽中；(c)將該處理槽設定在一具有預定溫度及大於2個大氣壓預定壓力之槽室環境，並維持一預定時間；(d)在該預定壓力之加壓下，使該膠著材料中之氣泡或膠著材料與半導體晶片間之氣泡或膠著材料與載板膠著界面間之氣泡由該膠著材料之四周排出。
  2. 如申請專利範圍第1項所述之半導體封裝之晶片黏著膠層氣泡排除方法，其中於步驟(c)所預定溫度係介於攝氏80度至175度之間。
  3. 如申請專利範圍第1項所述之半導體封裝之晶片黏著膠層氣泡排除方法，其中於步驟(c)所預定時間大於5分鐘。
  4. 一種半導體封裝之晶片黏著膠層氣泡排除方法，包括下列步驟：(a)將複數個製備好之半導體晶片之第一晶片其中一面 以膠著材料黏附在一載板之表面；(b)在該膠著材料於未老化或未完全老化前，將該黏附有半導體晶片之載板承置在一處理槽中；(c)將該處理槽設定在一具有預定溫度及大於2個大氣壓預定壓力之槽室環境，並維持一預定時間；(d)在該預定壓力之加壓下，使該膠著材料中之氣泡或膠著材料與半導體晶片間之氣泡或膠著材料與載板膠著界面間之氣泡由該膠著材料之四周排出；(e)將該含有半導體晶片之載板從該處理槽中取出；(f)以另一黏附有膠著材料之第二晶片疊置於該第一晶片其上，再將此半成品置入該處理槽依程序(b)、(c)與(d)執行消除氣泡製程，並於消除氣泡後移出該處理槽；(g)多顆疊置晶片即可依如上程序執行(f)步驟。
  5. 如申請專利範圍第4項所述之半導體封裝之晶片黏著膠層氣泡排除方法，其中於步驟(c)所預定溫度係介於攝氏80度至175度之間。
  6. 如申請專利範圍第4項所述之半導體封裝之晶片黏著膠層氣泡排除方法，其中於步驟(c)所預定時間大於5分鐘。
  7. 如申請專利範圍第4項所述之半導體封裝之晶片黏著 膠層氣泡排除方法，其中於步驟(e)之後更包括有半導體製程之打線處理步驟。
  8. 如申請專利範圍第4項所述之半導體封裝之晶片黏著膠層氣泡排除方法，其中於步驟(f)之後更包括有半導體製程之打線處理步驟。
  9. 如申請專利範圍第4項所述之半導體封裝之晶片黏著膠層氣泡排除方法，其中於步驟(g)之後更包含下列步驟：(h)藉由合模注膠方式模壓形成一封裝膠體於該半導體晶片之表面；(i)將該封裝膠體予以烘烤處理，使該封裝膠體老化以模封該半導體晶片。
TW096142523A 2007-11-09 2007-11-09 Method for Eliminating Bubble of Adhesive Adhesive Layer in Semiconductor Packaging TWI385738B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW096142523A TWI385738B (zh) 2007-11-09 2007-11-09 Method for Eliminating Bubble of Adhesive Adhesive Layer in Semiconductor Packaging
US12/289,809 US7863094B2 (en) 2007-11-09 2008-11-05 Method for removing bubbles from adhesive layer of semiconductor chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096142523A TWI385738B (zh) 2007-11-09 2007-11-09 Method for Eliminating Bubble of Adhesive Adhesive Layer in Semiconductor Packaging

Publications (2)

Publication Number Publication Date
TW200921808A TW200921808A (en) 2009-05-16
TWI385738B true TWI385738B (zh) 2013-02-11

Family

ID=40624088

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096142523A TWI385738B (zh) 2007-11-09 2007-11-09 Method for Eliminating Bubble of Adhesive Adhesive Layer in Semiconductor Packaging

Country Status (2)

Country Link
US (1) US7863094B2 (zh)
TW (1) TWI385738B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI700499B (zh) * 2019-07-17 2020-08-01 美商第一檢測有限公司 晶片測試系統

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016096297A (ja) * 2014-11-17 2016-05-26 イビデン株式会社 金属塊内蔵配線板及びその製造方法
TWI751919B (zh) * 2021-02-26 2022-01-01 印能科技股份有限公司 接觸式電軌高架搬運車（ｏｈｔ）集塵系統
CN114736648B (zh) * 2022-03-17 2023-08-01 广东华智芯电子科技有限公司 一种可常温b阶段化的胶粘剂
TWI800472B (zh) * 2022-11-16 2023-04-21 印能科技股份有限公司 半導體封裝之晶片黏著膠層氣泡排除方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW211538B (zh) * 1990-08-08 1993-08-21 Texas Instruments Inc
TW582078B (en) * 2002-11-29 2004-04-01 Chipmos Technologies Bermuda Packaging process for improving effective die-bonding area

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200949960A (en) * 2008-05-16 2009-12-01 Lingsen Precision Ind Ltd Flip-chip process using photo-curable adhesive

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW211538B (zh) * 1990-08-08 1993-08-21 Texas Instruments Inc
TW582078B (en) * 2002-11-29 2004-04-01 Chipmos Technologies Bermuda Packaging process for improving effective die-bonding area

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI700499B (zh) * 2019-07-17 2020-08-01 美商第一檢測有限公司 晶片測試系統

Also Published As

Publication number Publication date
US20090124044A1 (en) 2009-05-14
TW200921808A (en) 2009-05-16
US7863094B2 (en) 2011-01-04

Similar Documents

Publication Publication Date Title
TW498516B (en) Manufacturing method for semiconductor package with heat sink
JP4326786B2 (ja) 樹脂封止装置
CN108231607A (zh) 芯片封装方法及封装结构
TWI385738B (zh) Method for Eliminating Bubble of Adhesive Adhesive Layer in Semiconductor Packaging
CN108321134A (zh) 高功率密度塑封式ipm模块的封装结构及加工工艺
US7947530B2 (en) Method of manufacturing wafer level package including coating and removing resin over the dicing lines
WO2011150879A2 (zh) 半导体器件封装方法及其结构
CN101375389A (zh) 用于电路管芯的高热性能封装
CN208077964U (zh) 高功率密度塑封式ipm模块的封装结构
TW201705316A (zh) 晶片封裝製程及晶片封裝體
JP2010251346A5 (zh)
JP4842177B2 (ja) 回路基板及びパワーモジュール
JP5234884B2 (ja) 樹脂封止金型
CN103456649A (zh) 半导体封装方法
JP2006295010A (ja) モールド成型装置およびモールド成型方法
CN204243026U (zh) 一种高导热daf膜封装件
CN105321867A (zh) 一种互联载板的制作方法
CN101221909A (zh) 散热型封装件的制法及其所应用的散热结构
WO2024089880A1 (ja) 半導体装置の製造方法
CN118053767A (zh) 半导体封装的晶片黏着胶层气泡排除方法
KR100439188B1 (ko) 반도체 패키지 몰딩장치
JP2010153521A (ja) 半導体素子の樹脂封止方法
CN201134426Y (zh) 芯片封装结构
JPH10209194A (ja) 半導体装置、その製造方法およびそれに用いる樹脂モールド工程装置
JP2006066486A (ja) 樹脂封止型