TW211538B - - Google Patents

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TW211538B
TW211538B TW081100260A TW81100260A TW211538B TW 211538 B TW211538 B TW 211538B TW 081100260 A TW081100260 A TW 081100260A TW 81100260 A TW81100260 A TW 81100260A TW 211538 B TW211538 B TW 211538B
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cover
package
pressure
plasma
cavity
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TW081100260A
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Texas Instruments Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01L2224/73265Layer and wire connectors
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
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    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Closing Of Containers (AREA)
  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Packaging Frangible Articles (AREA)

Description

Λ 6 |{6 2li〇〇3 五、發明説明(1 ) [發明之技術領域] 概言之,本發明有關於半導醴裝置之空腔封装並且 特別有關於一種方法其可於一空腔封装之罩與本體間獲 得密封。 [發明之背景] 傳统積鱧電路塑膠封装方法包含利用壓鑄 '/(transfer molding)技術將積謾電路封入囊中。於此一 方法中,鑄·造混合物偽與積體霄路之表面相接觸。因為 晶片及封装中所使用之多種材料具有不同之機械與物理 特性,所以該封装之晶片使用琛境中之變化限制該封裝 之性能。 晶片可靠度問題常偽封装材料特性上差異所造成之 結果。許多常見的可靠度問題.例如金屬切變(meta 1 shear)、鈍化(passivation)、砂、以及在印刷接線板 附著期間之封装破裂,至少部分可歸因於持性上之差異 。舉例而言,封装之熱性能偽受使用於封裝晶Η之鑄造混 合物之熱導性(the rma 1 conductivity)所限制。 此空腔封裝概念使得傳统之塑膠封裝無法逹成之以 多種熱連接選擇方式製造封裝能夠實現。空腔封裝亦提 供一具有一空腔之封装,該空腔偽用以安装積髏電路晶 片使得該鑄造混合物與晶片之間不接觸。利用空腔封装之 多種熱連接滢擇方式可避免使用較昂貴之陶瓷封装。 本紙张尺度逍用中國國家標準(CHS)甲Ί規tS(210>:25)7公龙) (請先閲讀背而之注意事項#蜞寫本頁) 裝- 線- 經7S部中央榀準局β工消#合作杜印31 2ll^〇3 V 經濟部屮央櫺準局员工消费合作杜印製 五、發明説明6 ) 習知技轻之塑膠空腔封装及方法無法提供耐久的與 可靠的罩密封,其曽·影響封裝之積疆電路晶Η之可靠度。 、/梳形模(comb mo Id)方法即係此習知技轻之一種, 其在引線框架介面處具有封装密封。此種方法之缺失在 於製造困難、防潮性能不佳、模對準困難以及昂貴的工 具費用。 習知技薛之塑膠空腔封裝方法之一値問題偽各種欲 粘合在一起之零件之粘著力與表面處理。介於粘合剤與 聚合物及金屬粘合體間之粘著力不夠強。此外.習知之 表面處理方法無法與裂程相容。 [附圖之簡要説明] 圖1偽一安装至印刷接線板上之空腔封装之剖視圖 0 圖2偽一圖表其顯示不同之電漿氣體在粘著力上之 清洗效果。 圖3偽一圖表其顯示清洗時間在粘著力上之效果。 圖4偽圖1之空腔封装在封裝製程之一部分期間之 一剖視圖。 圖5偽本發明製程之一方塊圖。 [較佳實施例之詳細說明] 本發明係有關於美國專利第4,874,722號,併於此 择 — 壶、出供你.參考。 -4 - (請先閲讀背而之注意事項再项窩木頁} 裝- 訂- 線- 本紙51尺度边用中a S家楳準(CNS)肀4規格(210X297公龙)
五、發明説明6 ) 經濟部屮央楳準局兵工消伢合作杜印製 圖1顯示本發明之一塑膠空腔封裝10。如圖示,該 空腔封裝10傜附著至印刷接線板12。一積體電路晶片 14偽利用粘合劑11a而附著至引線框架13之模墊11處。 晶片14偽置於封装10内之空腔15中。導绨搭接17將晶片 14之搭接墊(未圔示)附著至引绨框架13。引線框架13之 部分延伸穿過空腔封爱i〇以便將封裝10電連 接至印刷接線板12。熱粘合劑19將模墊11附著至罩22。 矽酮(si 1 icone)外套14a亦可形成以覆蓋晶片14作為進 一步之保護。 空腔封装10具有一琛狀部分18,較佳偽一聚合物之 化合物,其形成空腔15且適於S圍積體電路晶H14。雖 然圖1所示之較佳實施例中環狀部分18偽矩形,但其可 為任何適當之形狀。環狀部分18係圍繞引線框架13而形 成,其偽依同時審査中之美画專利申請案第511,877號 所描述之方法而製造,該申請案於1 990年4月20日提出 申請,參考案號為TI-13619.1,其亦偽本案之譲受人所 擁有且併於此處提出供作參考。 如圖1所示,環狀部分18具有罩銜接肩部20,其延 伸進入空腔15。於此較佳S施例中,扃部20圍繞環狀部 分13之整値内側而延渖。扃部20具有罩銜接表面21其較 佳亦圍繞空腔15之周圍而延伸。該表面21係設計為能緊 密地與上軍22及下罩23銜接。 本紙張疋度逍用中BBS家樣準(CNS)T4規格(210x297公龙) (請先聞讀背而之注意事項再填寫本頁) 裝< 線- Λ 6 Π 6 2ΐ1ό〇8 五、發明説明(4 ) 上罩22及下罩23傜設計為能與由環狀部分18及肩部 20之銜接表面21以及圍繞罩22之周圍而延伸之接觸表面 • 24所界定之開口相配合。當罩22置於封裝10之上時.接 觸表面24係設計為能將與肩部20之銜接予以密封。 該等罩可以由不同之材料製成,其依據封裝之應用 而決定。其可以為金屬,例如鋁、不綉鋼、銅或合金。 塑穋,無論是熱固性或是熱塑性皆可使用。如有必要, 可使用高熱導性之材料,例如箱或鎢合金、銀、鍍金或 鍍S3。 如果本發明之封装欲用於封装EPROM,其罩必須能 傳導紫外線。其可以使用石英、硼矽酸鹽 ((bo「osilicate)玻璃、或藍賛石等材料。另一種可能 性偽使用鍍金之Kovar合金其中央設有石英玻璃以通過 紫外線。 封装10僅具有一痼罩22或23亦靥本發明範圍内9舉 例而言,如果封装10偽用於封装EPROM,其可能使用環 狀部分13與罩23而僅具一某種型式之外套以取代罩22。 任何其他型式之半導體晶Η亦可以此相同方式予以封装 〇 如果封装必須具有高功率能力,罩22之形狀可與圖 式之不同。因為此應用中須要散熱,其罩可設有翼片或自 罩延伸之其他突出物。 -6 - 本紙张尺度逍用中SIS家樣準(CNS)甲4規怙(210x297公龙) (請先閲讀背而之注念事項洱蜞寫本頁) 裝· 線. 經濟部中央#準局A工消#合作杜印製 經济部屮央櫺準局CX工消作合作社印製 五、發明説明(5) 為能在表面24與罩銜接表面20間形成密封,粘合劑 26係安置於表面24與罩銜接表面20之間。為具有一可抗 拒®力與濕氣之密封,在空腔封裝1〇之裝配之前須處理 表面24及20。 為確保成品之可靠度,必須將環狀部分13與罩22之 表面予以處理使環狀部分18與罩22有效地结合在一起。 粘合體(環狀部分18與罩22)之適當處理可確保粘合劑能 適當地將欲.接合之表面予以潤濕。如果粘合劑未適當地 將表面予以潤濕,接合將會較弱且不可靠。當接合處之 最弱點在粘合劑層本身而非在粘合劑與粘合體間之介面 處時可産生最強之接合。 罩22之表面處理可採用下列步驟之一或金部:清洗 、打毛(「oughen 丨 ng)、穩定(stabilization)、以及 活化(activation)。
如果封装欲包含塑膠罩,本發明之較佳方法含有利用電 漿以處理表面20及24。該電漿本質上較佳偽為等向性者 (isotropic)以便達成複合表面幾何學之表面處理。因 為装配過程中使用之材料僅有罩22與環狀部分18會暴露 在電漿中,所以此電漿之使用應不致損傷裝配過程中使 用之非粘合華材料Q 該聚合物表面偽利用電漿表面處理方法予以處理( 其可包含清洗及修飾)。粘合體(環狀部分18及罩22)偽 本紙乐尺度边用中國Η家標準(CNS)甲4規怙(210x297公龙) (請先閲讀背而之注意事項洱蜞寫本頁) 訂< 線. Λ 6 Β6 經濟部屮央櫺準局頁工消设合作杜印31 五、發明説明(6) 置於電漿環境中。該電漿較佳係利用40仟赫Η (ΟΖ)或 13.56百萬赫玆(MHz)之射頻所産生。來源氣體較佳偽g 或氪。環狀部分18及罩22在電漿室中係宜接安置於電極 上或案置於電極間之架子上。 例如,用於處理塑嘐環狀部分18及罩22組件之一種 表面處理方法係如下所述:施加13.56百萬赫H (MHz)及 150瓦(W)之射頻能量,其在240微米(micron)之電漿室 中一壓力處‘具有90毫升/分((CC/Min)之氣流速率。該方 法在溫度為85 - 1 0(TC間進行1 0分鐘。該氣體較佳偽氬。 上述方法不致損傷装配過程中使用之非粘合醴材料 ,例如氣化砂(silicon nitr丨de)與砂銅((silicone)外 套、金接合専線。引線框架電鍍、晶片之金靥噴鍍 (metallization)及衝擊(bump )。 該方法亦易於與整 饈空腔封装製程之其餘製程調和一致,從而可減少成本 與製程中斷。 本發明之粘合體處理方法有效地完成表面處理而不 須化學或機槭處理。此方法亦將封裝中之斷裂模式自粘 合破壞(adhesion failure)改變為内聚斷裂(cohesive fracture)模式,其傜吾人所欲者,因其賦予封装極大 之強度。 圖2及圖3偽於多種類型之電漿氣體與不同之處理 時間筷件下比較粘合力。如圖2中所示,經由一氬氣電 (請先閲請背而之注意事項#蜞寫木頁) 裝- 订· 本紙張尺度A用中a S家«準(CNS)甲4規格(210x297公Jt) 經濟部中央#準局员工消设合作杜印虹 2110〇d___ 五、發明説明I?) 漿或氮氣電漿處理後所形成接合之粘合力強度實質上偽 較未經電漿處理後所形成接合者為大。 . 圖3偽以於一由13.56百萬赫茲(MHz)頻率所産生之 電漿中之電漿處理時間為函數說明坫合力強度之增加。 如果罩22偽由金屬製成,可以利用化學方法實施表 處理。銅金靥之處理可利用黑色氣化物塗料,例如 Ebonol "C",或利用過硫酸较((Ammonium Persulfate)處理方法。如果罩偽Kovar合金材料,可利 用硝酸或三氧化鉻-鹽酸混合物處其表面。 於EPROM封装上使用之玻璃罩22可利數種方法之一 加以處理。一種方法法俱利用細砂之輕噴砂以買施溶劑 清洗或蒸氣除脂,随後以過濾之空氣將表面吹乾淨。第 二種方法偽首先實施除脂,在一由三氣化鉻(1重置份數 (PBW))與蒸蹓水(4重量份數)所形成之混合物中於室溫 下清洗15-20分鐘,隨後以蒸餾水清洗並且布溫度 180-200° F中乾燥20-30分鐘。第三種方法偽實施超音 波清潔浴,隨後在蒸皤水中清洗且於至溫下乾燥。 就一陶瓷罩而言,吾人建議之處理方法係蒸氣除脂 ,以200號砂纸磨光,且以真空或空氣噴霧清洗。釉之 表面處理必須自與粘合劑接觸之表面徹底除去以得到極 大強度。 如果罩偽鋁質,較佳之處理方法像用於結構上之钻 -9 - 本紙張尺度遑用中S Η家櫺準(CNS)T4規格(210x297公龙) (請先閲讀背而之注意事項#填寫本頁) 裝· 線- Λ 6 Β6
五、發明説明(8) 經濟部屮央櫺準局员工消费合作社印¾ 公grt培合之IS表而理(SS酴陽極處理).其被(美國 試驗材料學會,American Society for Testing and Materials)稱為 D3933-80(ASTM 標準之年编,第 22部)。 此方法略述於下: 1.除脂步驟,使用1,1,1三氛乙垸10-15分鐘,9〇 + /-510 〇 2·驗性清洗,使用Oakite 164號,10-15分鐘, 60-72T: 〇 . 3 .水洗,使用蒸餾水,超過5分鐘,大於43 1C。 4.去氣(森林産品實驗室[Forest Products’ Laboratories]之方法),使用重銘酸納/硫酸,10-15分 篷,65-72C。 5 .二次水洗,使用蒸蹓水,超過5分鐘,25 C 6. 磷酸陽極處理,利用55酸(753:)/水,20-25分鐘 ,15 + /-1 伏持。 7. 水洗,利蒸餾水,10-15分鐘,25 °C。 3.乾燥,利用熱空氣,45分鐘,75 t(最大 9.檢査,使用具有光學镉光濾光器之水銀蒸氣燈。 10 .粘合劑底膠塗佈。 a. 噴底瘳,例如美國氡胺BR-127厚度0.001-0.0 0 3 吋。 b. 空氣乾燥,超過30分鐘,25 eC。 -10 - (請先閲讀背而之注意事項Λ-填寫本頁) 裝< _ 線. 本紙張尺度边用中a圉家標準(CNS)肀4規怙(210x297公龙) 211όύ3 ---- η β__ 五、發明説明(9 ) c.爐式乾燥,30分鐘,112-12110。 其他各種金靥之表面處理可參見用於拈合_培会夕 金名稱為 D2651-79,於 1984年重新認 可),其偽併於此處供作參考。 如圖4所示,本發明亦掲示一新穎之方法其在清洗 及裝配步驟完成後將空腔封裝予以密封。於圖4中,封 裝10置於一壓機(P「ess)50中。如箭頭51所示,壓機 50在封装10乏頂部及底部兩處施加壓力。壓機50可為一 單開口或多開口之壓機。 在封装10之頂部及底部兩處,介於封裝10與壓機 50之間設置一堅硬之金屬板52 ,其為不銹鋼等材料。介 於堅硬金屬板52與壓塾56之間設置一釋放薄膜,較佳偽 Pacothane (tm)材料,3 ® 塾 56 較佳係 δ夕橡膠(silicone rubber)材料,例如C0HRlastic(R>3320。 此密封方法將壓力均勻地分佈在壓機5〇中之整個封 装10上。特別之平台設計以及預先規剷之熱型式應用至 整®密封過程造成可靠之密封。 於封装10以及上述有關之密封設備置於壓機50中後 ,在一預定之溫度下施加一預定之壓力至封裝10經過一 段持定之時間3該壓力及溫度可隨一預定型式而變,或 者其中之一或兩皆可為常數。 例如:毎封装施加50 + /-5psi之壓力,處理溫度保 -11 - 本紙张尺度边用中困困家標準(CNS)T4規怙(210x297公ΐ) (請先閲讀背而之注意事項#塥寫本頁) 裝< 線· 經濟部中央標準局Εζ工消疗合作杜印製 Λ 6 Π 6 2ΐ1ό〇3 五、發明説明(19 持在175t:經60分鐘,其具有75分鐘之週期時間。在封 装過程期間適當之溫度控制有其重要性,因粘合劑之流/ 動持性可依加熱程度而定,其會影鎏接合線之厚度。 在密封過程期間,介於壓墊56與封裝10間之密封非 常重要,因内部壓力會於封裝1〇中展開。由壓機50施加 至封装10之壓力應將封装10中之内部壓力平衡以便産生 最大之接合線密度從而可防止發生枯合劑流出之現象。 如果發生流,出現象,接合線不會壓緊而會産生空隙,其 會造成不合標準之接合。使用矽酮(silicone)壓墊56 對於防止漏出有所助益。且.因封装10内部之壓力有效 地壓緊接合線,所以矽酮亦可用於阻止粘合劑流至封装 10之外部表面上,其偽一可見之封装缺陷。 於施加溫度及壓力經過一段適當時間後,開始一冷 卻週期,於此控制之冷卻期間壓力繼缠保持。某些粘合 劑霈要將壓力繼缅保持直至粘合劑凝固或成凝膠狀。於 此較佳實施例中,將壓力除去之溫度大.约為200° F。 装配一積體電路及一空腔封装元件之裝配流程可包 含下列步驟: 1 .將罩作表面處理,如上述之各種使用材料之處理。 2.將粘合劑塗佈至罩上。 a. 將粘合剤塗佈至整個罩上而預先成型。 b. 將粘合削以”窗框(window frame)”方式 -12 - 本紙張尺度边用中a困家樣準(CNS) T4規格(210x29’/公放) (請先閲讀背而之注意事項#塡寫本頁) 裝- 線- 經濟部屮央櫺準局β工消仲合作杜印¾.
五、發明説明(A1 塗佈而預先成型。 經濟部中央榀準扃β工消仲合作杜印5i 3 ·將鑄造之環狀部分以電漿處理。 4. 將罩裝配至鑄造之環狀部分中。 5. 將熱撒播器(heatspreader)装配至鑄造之環狀 部分中。 a .將與模相同或類似之銀填充材料附箸至钻合劑 上。 b.將罩密封粘合削覆蓋整個姝撤播器且熱附著係 自動實施。 6. 罩密封步驟。 雖然本發明己經描述供一空腔封裝罩密封增強使用 之封装方法,但上述方法可有利的用於淸洗任何徹電子封 装表面,例如在以符號表示之前去脂。該方法亦可供金 屬空腔封装、塑膠封装、高功率産品、混合堆叠記億器 或多晶片産品使用。 -13 - 本紙尺度遑用中國a家標毕(CNS) Ή規格(210X297公¢) (請先閲讀背而之注意事項再墦寫本頁) 丁 %

Claims (1)

  1. 六、申請專利苑圍 A IC: D: 專利申請案第81100260號 ROC Patent Appln. Ho. 81100260 修正之申請專利範圍中文本-附件一 Amended Claims in Chinese - Enel. I (民國82年6月曰送呈) (Submitted on June. (〇 , 1993) 經 濟 部 + 央 標 準 局 % 工 消 合 作 社 印 製 1. 一用M處理粘合醱之方法*其包含步驟: 將拈合體置於一電漿反應器中使得粘合體係位於諸電極 間; 在電漿反應器中產生電漿;Μ及 自氦氣及氬氣群中之一氣體產生電漿。 2. —用以增強介於塑膠空腔封裝罩與塑膠空腔封装本體間 之接合之方法,包含步驟: 將罩及本體置於一電漿反應器中; 在電漿反應器中產生電漿; 將反應氣體導入反應器中;Μ及 激勵該反應氣體。 3. 如申請專利範圍第2項之方法,其中擻勵該反應氣體之 步驟包含施加射頻功率至電漿室之步驟;以及 將電漿室中之壓力滅少至低於760托爾(Torr>。 4. 一用Μ密封空腔封裝之方法,包含步驟: 於一預定時間内施加壓力至空腔封裝;Μ及 在施加壓力步驟之期間將空腔封裝加熱至一預定溫度。 5. 如申請專莉範圍第4項之'方法•其中施加懸力之步驟包 -14 - 93-9ti.584-C {請先閱讀背面之注意事項再填寫本頁) .装·' •訂. •線. 本紙張尺度逍用中國國家標準(C N S) f 4規格(210 X 2 9 7公釐) 經 濟 部 中 央 標 準 局 Μ 工 消 fr 合 社 印 製 AT B7 C7 __ D7 六、申請專利範園 含將封裝置於一壓機中之步费ί ; 於施加壓力至封裝之前在壓機舆封装之間安置一墊;Μ 及 將封裝冷郤至低於一預定溫度但保持封裝於一氣壓下。 6.—用Μ裝配一空腔封裝之方法•該空腔具有一本體Κ及 至少一罩•包含步揉: 將罩與本體置於一霉漿室中; 在電漿室中產生電漿; 將粘合劑塗佈至罩或本體上; 將罩安置於本體上;以及 將罩與本醱密封。 7. 如申請專利範圍第6項之方法•其中密封\之步驟復包含 步驟: 將封裝加熱至一預定溫度; 於一預定時間内施加均勻之壓力至封裝;以及 將封装冷卻至一預定溫度但保持均勻之壓力。 8. —封裝積體電路之方法•該封裝具—形成為圍繞積體 電路之環狀部分Μ及至少一罩*包含步驟: 處理罩之表面; 將粘合劑塗佈於罩上; 處理環狀部分; 將罩置於環狀部分中; 將熱撤播器置於環狀部分中;以及 將罩與環狀部分密封。 9. 如申詨専利範Ε第3項之方法*其中芘理箄之步菸復包 含步S : -15 - 、本紙張尺度適用中國國家標準(CNS)甲4規格(210x297公釐) .............................................;…:.............................打…:.....................綠 (請先閲讀背面之注意事項再填寫本頁) ό A 7 B7 C7 D7 六、申請專利範® 淸洗罩之表面; 將罩之表面去脂; 將罩之表面去氧; 將罩之表面陽極處理;以及 將粘合劑底膠塗佈於罩之表面上。 10.如申請專利範圍第8項之方法·其中處理罩之步驟復 包含步驟: 將罩之表面去脂; 將罩浸於硫酸浴中; 將罩於蒸餾水中水洗;Μ及 將罩予Μ乾燥。 Π.如申請專利範圍第8項之方法•復包含步驟: 將罩與本體置於一壓機中; 於一預定時間內施加一預定壓力至罩與本體上; 於施加壓力步费[之期間按照一預定型式保持罩與本體 之溫度;以及 當罩與本體冷卻至一預定溫度時保持一預定之壓力, 其中施加一預定壓力之步驟包含保持壓力使得該壓力 遵循一預定之型式L (靖先閲碛背面之注意事項再填寫本頁) _汶- _訂· 經濟部中央標準局員二消費合作社印製 .線· i:,e k ^ zf, X? ;A rs tli an ge^ ^>4^ -/t rrvc\ ^
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