TWI364793B - Package structure for integrated circuit device and method of the same - Google Patents

Package structure for integrated circuit device and method of the same Download PDF

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Publication number
TWI364793B
TWI364793B TW096116302A TW96116302A TWI364793B TW I364793 B TWI364793 B TW I364793B TW 096116302 A TW096116302 A TW 096116302A TW 96116302 A TW96116302 A TW 96116302A TW I364793 B TWI364793 B TW I364793B
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TW
Taiwan
Prior art keywords
metal
conductive bump
package structure
combination
integrated circuit
Prior art date
Application number
TW096116302A
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English (en)
Other versions
TW200845201A (en
Inventor
Lu Chen Hwan
yu lin Ma
P C Chen
Original Assignee
Mutual Pak Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Mutual Pak Technology Co Ltd filed Critical Mutual Pak Technology Co Ltd
Priority to TW096116302A priority Critical patent/TWI364793B/zh
Priority to US12/116,152 priority patent/US7772698B2/en
Priority to JP2008121686A priority patent/JP2008288583A/ja
Publication of TW200845201A publication Critical patent/TW200845201A/zh
Priority to US12/826,510 priority patent/US20100267204A1/en
Application granted granted Critical
Publication of TWI364793B publication Critical patent/TWI364793B/zh
Priority to JP2012004517U priority patent/JP3178881U/ja

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Description

13,64793 九、發明說明： 【發明所屬之技術領域】 本發«路元件封裝結觀其方法 體地關於晶圓級的積體電路元件封裝結構及其方法 叫更具 【先前技術】 -般晶圓級封裝結構之封裝材料、形成於積體電路元件上 方。則當聽完成，_成烟⑼時，碰電 無封裝材料舰。 j3til 方法，能使積體電 因此需要-種積體電路元件封裳結構及並 路元件側邊也受到保護。 ” 【發明内容】 鑑於上述需求 結構及其方㈣ 本發明之一面向提供一種封 51 ^伐、構，包含具複數個積體電路 兀件之-晶圓、至少-槽1伸金屬塾、—第—導電= 一絕緣層。至少一槽位於晶圓中， ^ 接觸至少-複數個積體電路元件。第：日日圓。延伸金屬塾電性 上。而絕緣層位於複數個積體電路元件上雜至少 1塾 絕緣層覆蓋至少-複數個積體電路元件之—側壁。θ 。、中
4MUTPAK/07002TW 1364793 前述延伸金屬墊之一材料可為鈦（Ti)、鈦鎢合金（Tiw)、鉻 (Cr)、銅（〇〇、或其組合。前述絕緣層之一材料可為環氧樹脂 (epoxy)、聚亞醯胺（polyimide)、笨并環丁烷 butane)、液晶高分子（liquid crystai p〇lymer)、或其組合。 絕緣層可藉印刷形成。 前述封裝結構可更包含一第二導電凸塊位於第—導電凸塊 上’以及-表面金屬層位於第二導電凸塊上。前述第—導電凸塊 與第二導電凸塊之至少-可包含複數個金屬顆粒與一高分子化人 物。複數個金屬顆粒可為銅⑽、錄（Νι)、銀㈤ 顆：=合。複數個金屬顆粒之一尺寸可於i至1〇微米以 •糾⑽蝴她旨（epQxy)、鳩 crystal p〇lymer )、戎 A q 之-體狐可仏少85ri5m個金__高分子化合物 印刷形成。表面金屬層之—材：導&電凸塊與第二導電凸塊可為藉 層之材料可為鎳、金、或其組合。 前述封裝結構也可更包含 金屬壁之-材料可為鎳、H或其組合於P導電凸塊上。 刖述封裝結構亦可更包含 金屬塾’位於至少—複數個積體
4MUTPAK/07002TW 6 電路元件與延伸金間，供延伸金屬墊電性接觸至少一複數個 積體電路元件。其巾延伸金屬墊之—面積A於金胁之一面積。 封震結構可更包含-保護層（passivatiQn layer)，位於至少一 複數個積體電路元件與延伸金屬墊I金屬塾之—材料可為紹 (A1)。保護層之-材料可為氮氧化石夕（SiN〇)。 本發明之ϋ向提供—種封裝結構，供封裝—晶圓所具複 _積體電路树之至少―。封裝結構包含—延伸金屬塾、一第 :導電凸塊、與―絕緣層。延伸金輕紐接觸至少—複數個積 _電路几件。第—導電凸塊位於延伸金屬墊上。而絕緣層位於至 少-複數個频元件之上轉—麵上。 、 前述延伸金屬塾之—材料可為鈦、鈦鶴合金、鉻、銅 二絕緣層之-材料可為環氧樹脂、聚亞醯胺、笨并射 液阳㈣子、或其組合。絕緣層可藉印刷形成。 前述封裝結構可更包含—第二導電凸塊位於第 上，以及—表面金屬層位於第二導電凸塊上 與第二導電凸塊之至少-可包含複數個金屬顆粒與—高 物^數個金屬顆粒可為鋼、鎮、銀、金顆粒 ι 個金細w柯於Ww⑽為=
4MUTPAK/07002TW 二液㈣分子、或其組合。複數個金屬顆粒與高分子化人物 B -體積比可為至少85:15。第一導電凸塊與第二導電凸塊可二 P刷形成。表面金屬層之一材料可為鎳、金、或其組合。‘”猎 前述封裝結構也可更包含-金屬壁，位於第— 金屬壁之一材料可為鎳、銅、金、或其組合。 。 釗述封裝結構亦可更包含一金屬塾 電路元件與延伸金屬，供延伸 細固積體 穑㈣枚4轉觸至少—複數個 積體電路轉。其巾延伸金屬墊之—面積A於金屬塾之一 封襄結構可更包含__保護層，位於 M A Α β 设数個積體電路元件盥 、伸金屬墊間。金屬墊之一材料可為 /、 氧切。 ⑽保麟之—材料可m 本發明之又一面向提供一種形成一封裝結構的方法此封 、.、。構供封H騎具複數個频電路元件之至少—包含下; :驟。形成至少一槽於晶圓中，供切割晶圓。形成一延伸金屬墊 電性接觸至少-概個频f路元件。形成—第—導電凸塊約 伸金屬墊上·。形成-絕緣層於複數個顏電路元件上方與至少_
槽中。以及_至少-槽切割晶圓，以形成複數個已封襄晶片。 其中絕緣層覆蓋至少-複數個積體電路元件之一側壁。 4MUTPAK/07002TW 8 13.64793 前述形成縣結構的方法可更包含組裝至少-複數個已封裝 曰a片於|板’基板具-互聯結構。前述互聯結構之一材料可為 銲材（solder)、_ (Ag paste)、或其組合。前述基板可為二 撓性印刷電路板（flexible printed circuit，Fpc)、印刷電路 板（pHrltei circuit board，PCB)、或陶£ (cerates)基板。 前述組裝步料包含藉表㈣著㈣（―職nt η麵y ’ ®)接合至少—複數個已·“與互聯結構。 前述延伸金屬塾之-材料可為鈦、鈦鶴合金、鉻、銅、或其 組合。=絕緣層之-材料可為環氧樹脂、聚亞酿胺、苯并環丁 =:子或其組合。别獅成絕緣層於複數個積體電路 兀件上方與至槽中之步驟，可包含印刷形成—絕 個積體電路元件上方與至少一槽中。 纖 前述形紐裝結構的方法，可更包含下列步驟。形成一第二 凸第—導電凸塊上。以及形成—表面金屬層於第二導電 -第二—第r導電凸塊於延伸金料上之步驟與形成 導電凸塊且巷::第—導電凸塊上之步驟之至少-可包含形成- 金屬她與-高分子化合物。概個金屬顆粒 可於1㈣細ΓΛ、或其组合。複數個金屬顆粒之一尺寸 ”—子化合物可為環氧樹脂、液晶高分子、
4MUTPAK/07002TW 二二二複數個金屬·與高分子化合物之—體積比可為至少 -莫、成第—導電凸塊於延伸金屬墊上之步驟，與形成第 '電凸塊於第—導電凸塊上之步驟，分別可包含印刷形成第一 電凸塊於科金屬塾上，以及印卿料二導電凸塊於第一導 _凸塊上°表面金屬層之—材料可為鎳、金、或其組合。 導電成封储構的方法’也可更包含形成—金屬壁於第— 金屬壁之-材料可域、銅、金、或其組合。 一—剛述形成封裝結構的方法，亦可更包含形成—金屬塾於至小 複數個積體電路疋件與延伸金屬塾間，供延伸金屬塾電性 =少-複數個積體電路元件。其中延伸金屬墊之—面積大 t 一面積。此形成_構的方法可更包含形成—保護層於= ^複數個積體電路元件與延伸金屬細。金屬墊之 鋁。保護層之-材料可為氮氧化石夕。 广w為 說明 一為使本發明之目的與特徵更為明顯，配合所附圖式詳細 貫施例於下。 【實施方式】 構1〇〇 圖- A至1ί _面圖，麻根據本發明之軸 姓 4义、、、含
4MUTPAK/07002TW 1364793 的方法之一實施例，以及其所形成之封裝結構100。封裝結構1〇〇 供封裝一晶圓102所具複數個積體電路元件104之至少一。 首先參照圖一 A ’晶圓102具複數個積體電路元件、以及 形成其上的金屬墊108與保護層110。文後以一個積體電路元件 說明，然不限於此。此實施例包含形成至少一槽1〇6於晶圓 中此例中’槽106即劃刻線（scribe line)，供之後切割晶圓 為個別晶片。 請參照圖一 B，接著形成一延伸金屬墊112，電性接觸積體電 路π件104。此實施例中，延伸金屬墊112係藉金屬墊1〇8接觸積 體電路树104’且延伸金 Π2之-面積大於金屬墊灌之一 面積’然不限於此。延伸金屬整112之一材料可為鈦、鈦鎮合金、 鉻、銅、或其級合，或任何其他可電性接觸積體電路元件⑽之 材料金屬塾1G8之-材料可為銘，或任何其他可供延伸金屬塾 112電性接觸積體電路元件104之材料。保護層110之一材料可為 氛氧化梦’雜何其他可供保護積體電路元件之材料。 々圖:c巾’形成一第—導電凸塊114於延伸金屬整112上。 第導電凸塊114可選擇性地包含複數個金屬顆粒與一高分子化 合物。複數個金屬難可為銅、錄、銀、金齡、或其組合，然
4MUTPAK/07002TW 4793 不限於此。複數個金屬顆粒之一尺寸可於丨至微米間。高分子 化合物可為環氧細旨、液晶高分子、或其組合，然不限於此。複 數個金屬顆粒與高分子化合物之一體積比可為至少85:15。形成第 -導電凸塊114於延伸金屬墊112上之步驟可為藉印刷形成。 此實施例還可選擇性地包含形成一金屬壁116於第一導電凸 塊114上。金屬壁116可增加第一導電凸塊114之導電性。金屬 壁116之-材料可為鎳、銅、金、或其組合，然不限於此。 參照圖-D’接著形成-絕緣層118 _體電路元件1〇4之上 方與槽106中。此例中，絕緣層118還形成在選擇性覆有金屬壁 116的第一導電凸塊114側邊與延伸金屬墊112上。由於槽106 鄰接積體電路元件1G4，狀後晶圓切贼_晶片時，分布於槽 106中的、絕緣層118覆蓋積體電路元件1〇4的側壁，給積體電路元 件104更全面的保護。絕緣層U8之一材料可為環氧樹脂、聚亞 醯胺、本并環丁烧、液晶高分子、或其組合，或任何其他可供保 護積體電路元件舰之材料。形成絕緣層118之步驟，可藉印刷 形成。 曰 參照圖-E，本實施例可包含移除一部份絕緣層ιΐ8，而露出 第-導電凸塊114。參照圖—F，接著形成—第二導電凸塊12:於 4MUTPAK/〇7〇〇2Xw 12 U64793 第:導電凸塊114上。以及選雜地形成一表面金屬層122於第 導电凸塊120上，而形成一封裝結構實施例1〇〇。第二 1 2Π ^ ^ 、擇性地包含複數個金屬顆粒與一高分子化合物。複數個金 屬顆粒可袖、鎳、銀、金馳、或其組合，鮮限於此 個麯顆粒之-尺寸可於i至1〇微米間。高分子化合物可為環氧 古八液日日呵刀子、或其組合’然不限於此。複數個金屬顆粒與 二子化合物之—體積比可為至少85形成第二導電凸塊⑽ 、—導電凸塊114上之步驟’可為藉印刷形成。表面金屬層⑵ =Γ為錄、金、或其組合’或任何其他可幫助物仙〇 /、其他裝置接合的材料。 如圖-G，上述封裝結_形成後，可移除至少_部份晶
°而可侧⑽__朗娜，咖沿虛線L :。而分⑽⑽巾的_118縣频槪件谢的 側壁，給積體電路元件104更全面的保護。 接著參照圖—H’已封裝晶片可組裝至—基板1基板⑽ 一互聯結構226與導線228。我們可冉4 .、t立$α 1 了再-人庄思到絕緣層118覆蓋積 體電路轉m _，給_路元件 聯結構226之-姑料可a抑 叫保》隻互 〜材 '轉、或其齡，雜何其他可 選擇性覆編細122 n㈣m與⑽
4MUTPAK/07002TW 1^64793 〇的材料。絲224可為-撓性印刷電路板、印刷電路板、或陶 究基板。^此，崎步驟可藉表面鮮技術接合已健晶片與互聯 結構226。 以上所賴為本發明之健實_，鱗㈣限定本發明之 申請專利細。凡其妹麟本料·示之精狀等效改變或 修飾，均應包含於所附申請專利範圍内。 【圓式簡單說明】 圖一 Α至Η係剖面圖，例示根據本發明之形 方法之一實施例，以及其所形成之封裝結構 成一封裝結構的 【主要元件符號說明】 100封裝結構 104積體電路元件 108金屬墊 112延伸金屬塾 116金屬壁 120第二導電凸塊 224基板 228導線 102晶圓 106槽 110保護層 114第一導電凸塊 118絕緣層 122表面金屬層 226互聯結構
4MUTPAK/07002TW

Claims (1)

  1. 曰修正本 '申請專利範圍： 案號：96116302 月29日修正-替換頁 一種封裝結構，包含·· —晶圓’具複數個積體電路元件； 至少—槽，位於該晶圓中，供切割該晶圓； 延伸金屬墊，電性接觸至少一該複數個積體電路元件； —第一導電凸塊，位於該延伸金屬墊上； 一第二導電凸塊，位於該第一導電凸塊上； 中； 一表面金屬層，位於該第二導電凸塊上；以及 -絕緣層，位於該複數個積體電路元件上方與該至少一槽 ”中該絕緣層覆蓋該至少—該複數個積體電路元件之一侧 導電凸塊與該第二導電凸塊之至少—包含複數個 金屬顆粒與一高分子化合物。 2. 如請求項1所述之封裝結構，更包含： 一金屬壁，位於該第—導電凸塊上。 3. 如請求項1所述之封裝結構，更包含： 一金屬塾，位於該至少— 屬塾間’供該延伸金屬塾電==個積體電路元件與該延伸金 件； 接觸邊至少一該複數個積體電路元 15 1364793 案號：96116302 其中該延伸金屬塾之-面積大於該金屬塾 100年7月29日修正-替換頁 之一面積。 4.如請求項3所述之封裝結構，更包含： -保護層’位於該至少-該複數個積體電路元件與該延伸金 屬墊間。 5.如請求項1所述之封料構，其巾該複數個金屬顆粒係銅、 錄、銀、金顆粒、或其、纟且合。 6.如明求項1所述之封裂結構，其中該複數個金屬顆粒之—尺寸 係於1至10微米間。 、 7.如請柄1所述之封裝結構，其巾該高分子化合物係環氧樹 脂、液晶高分子、或其組合。 8.如請求項1所述之封裝結構，其中該複數個金屬職與該言八 子化合物之一體積比係至少85:15。 门刀 第二導 9.如凊求項1所述之封裝結構，其中該第一導電凸塊與該 電凸塊係藉印刷形成。 ^ 1〇·如請求項1所述之封裝結構，其中該延伸金屬墊之1料係 16 案號：96116302 100年7月29曰修正-替換頁 鈦、鈦鎢合金、鉻、銅、或其組合。 U.如請求項1所述之封裳結構，其中該絕緣層之一材料係環氧樹 脂、聚亞醒胺、苯并環丁燒、液晶高分子、或其組合。 如》月求項11所述之封裝結構，其中該絕緣層係藉印刷形成。 13.如明求項1所述之封裝結構，其中該表面金屬層之一材料係 錄、金、或其組合。 K如叫求項2所述之封裝結構，其中該金屬壁之一材料係錄、 銅、金、或其組合。 • 15.如請求項3所述之封震結構，其中該金屬墊之-材料係链。 :。如請求項4所述之聰結構，其中該倾層之—材料係氮氧化 〜種封裝結構，供封裝一晶圓所具複數個積體電路元 〜結構包含： ^ 一^伸金屬塾，紐接觸該至少—該複數個積體電路元件； 第一導電凸塊，位於該延伸金屬墊上； 17 1364793 案號：96116302 年7月29曰修正-替換頁 電凸塊上； 凸塊上；以及 一第二導電凸塊，位於該第一導 一表面金屬層，位於該第二導電 一絕緣層，位於該至少一該複數個積體電路元件之上方盘一 側壁上，其中該第—導電凸塊無第二導電凸塊之至少—包含複 數個金屬顆粒與一高分子化合物。 18. 如請求項π所述之封裝結構，更包含： 一金屬壁，位於該第一導電凸塊上。 19. 如請求項π所述之封裝結構，更包含： 一金屬墊，位於該至少—該複數個碰電路元件與該延伸金 屬墊間’供該延伸金屬墊電性接觸該至少—該複數個積體電路元 件； 其中該延伸金屬墊之一面積大於該金屬墊之一面積。 2〇‘如請求項π所述之封裝結構，更包含： 一保護層，位於該至少一該複數個積體電路元件與該延伸金 屬墊間。 21.如請求項丨7所述之封裝結構，其中該複數個金屬顆粒係銅、 鎳、銀、金顆粒、或其組合。 18 1364793 案號：96116302 100年7月29曰修正-替換頁 22. 如請求項17所述之封裝結構，其中該複數個金屬 顆粒之一尺 寸係於1至1〇微米間。 23. 如請求項17所述之輯結構，其中該高分子化合物係環氧樹 脂、液晶高分子、或其組合。 八子17所奴塊結構，其愧複數個金_粒與該高 刀子化合物之一體積比係至少85:15。 门 =·如請求項Π所述之嶋構，其中該第一導電凸塊 導電凸塊係藉印刷形成。 第一 材料係 27.如明求項17所述之封裝結構，射 樹脂、聚亞醯胺、苯并環 、二、’曰之-材料係環氧 伙日日円分子、或其組合。 說如請求項丨7所述之封裝結構， 射該絕料係騎刷形成 19 〇π 茱號：9611630: 29·如請求項17所述之封 丨〇〇年7月29日修正-替換頁 鎳、金、或其組合。I。構，其帽表面金屬層之—材料係 其令該金屬壁之一材料係鎳、 如》月求項丨8所述之封裝結構， 銅、金、或其組合。 月求項I9所述之封裝結構，其中該金屬墊之一材料係紹。 月求項2〇所述之封裝結構，其中該保護層之一材料係氮氧 化石々。 種域封裝結構的方法，該封裝結構供封裝一晶圓所具複 數個積體電路元件之至少…該方法包含： 形成至少一槽於該晶圓中，供切割該晶圓； 形成延伸金屬整，電性接觸該至少一該複數麵體電路元 件； 形成一第一導電凸塊於該延伸金屬墊上； 形成一弟一導電凸塊於該第一導電凸塊上； 形成一表面金屬層於該第二導電凸塊上； 形成一絕緣層於該複數個積體電路元件上方與該至少一槽 中；以及 20 1364793 案號：96116302 100年7月29曰修正-替換頁 用該至少一槽切割該晶圓，以形成複數個已封裝晶片； 其中該絕緣層覆蓋該至少一該複數個積體電路元件之一側 璧，以及其中該形成一第一導電凸塊於該延伸金屬墊上之步驟與 該形成-第二導電凸塊於該第一導電凸塊上之步驟之至少一包含 形成一導電凸塊具複數個金屬顆粒與一高分子化合物。 34. 如請求項33所述之方法，更包含： • 、组裝至少-該複數個已封裝晶片於一基板，該基板具一互聯 結構。 35. 如請求項34所述之方法，其中該互聯結構之一材料係鲜材、 銀朦、或其組合。 36. 如胃$項34所述之方法’其♦該基板係—撓性印刷電路板、 參印刷電路板、或陶瓷基板。 τ接八7項34所述之方法’其_输裝步驟包麵表面黏著技 術接合5亥至少一該複數個已封裝晶片與該互聯結構。 38.如請求項33所述之方法，更包含： 形成一金屬壁於該第一導電凸塊上。 21 1364793 索號：96116302 100年7月29曰修正-替換頁 39. 如请求項33所述之方法，更包含·· 形成-销駐少—該減個親魏元件與該延仲金 屬/間’供觀_她_卿-碰輸電路元 件； 其中該延伸金屬墊之一面積大於該金屬墊之-面積。 40. 如請求項39所述之方法，更包含： 減保㈣於駐少—該複脑髓電路元件與該延 屬墊間。 ' 如明求項33所述之方法，其中該複數個金屬麵係銅、錄、 銀、金顆粒、或其紐_合。 如-月求項33所述之方法，其中該複數個金屬顆粒之 於Ϊ至1〇微米間。 /求項33所述之方法’其巾該高分子化合物係環氧樹脂、 液晶尚分子、或其組合。 ’如明求項33所述之方法’其中該複數個金屬顆粒與該高分子 22 1364793 1n 案號·· 96116302 10〇年7月29日修正-替換頁 化合物之一體積比係至少85.15 45.如請求項33所述之方法 伸金屬塾上之步鄉，與 上之步騾，八別勺人，〃苐-導電凸塊於該第-導電凸塊 上之步驟刀別包含印刷形成該第一導電 上’以及印刷形成該第二導電凸塊於該第-導電凸：。 Γ^Π33Γ述之方法，其中該延伸金屬塾之—材料係欽、 鈦鎢CT金、鉻、銅、或其組合。 π如π求項33所述之方法，其中該絕緣層之—材 脂、聚亞醜胺、苯并環丁院、液晶高分子、或其組合。_ n/m其中r成—絕緣層於該複數個積 …千上方與赶槽中之步驟，包含印刷形成—絕緣舞 於》亥複數個積體電路元件上方與該至少一槽中。 49·如請求項33所述之方法，其中該表面金屬層之-材料係鎳、 金、或其組合。 ” 见如請求項38所述之方法，其中該金屬壁之一材料係錄、鋼 23 1364793 案號：96116302 100年7月29日修正-替換頁 金、或其組合。 51. 如請求項39所述之方法，其中該金屬墊之一材料係鋁。 52. 如請求項40所述之方法，其中該保護層之一材料係氮氧化矽。
    24
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JP2008121686A JP2008288583A (ja) 2007-05-08 2008-05-07 集積回路素子パッケージ構造及びその製造方法
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