US20100267204A1 - Package structure for integrated circuit device and method of the same - Google Patents

Package structure for integrated circuit device and method of the same Download PDF

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Publication number
US20100267204A1
US20100267204A1 US12/826,510 US82651010A US2010267204A1 US 20100267204 A1 US20100267204 A1 US 20100267204A1 US 82651010 A US82651010 A US 82651010A US 2010267204 A1 US2010267204 A1 US 2010267204A1
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Prior art keywords
forming
conductive bump
metal pad
circuit devices
insulator layer
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US12/826,510
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Lu-Chen Hwan
Yu-Lin Ma
P.C. Chen
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Mutual Pak Technology Co Ltd
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Mutual Pak Technology Co Ltd
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Priority to US12/826,510 priority Critical patent/US20100267204A1/en
Assigned to MUTUAL-PAK TECHNOLOGY CO., LTD. reassignment MUTUAL-PAK TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, P.C., HWAN, LU-CHEN, MA, Yu-lin
Publication of US20100267204A1 publication Critical patent/US20100267204A1/en
Abandoned legal-status Critical Current

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Definitions

  • This invention relates to a package structure for intergraded circuit devices and a method of the same, and more particularly, relates to a wafer level package structure for intergraded circuit devices and a method of the same.
  • package materials are only applied on the top of the wafer. After the packaging step, the wafer is cut into multiple chips and therefore the sidewall of each chip is exposed without being protected by the package materials.
  • the package structure includes a wafer having a plurality of intergraded circuit devices, at least one groove, an extension metal pad, a first conductive bump, and an insulator layer.
  • the at least one groove is in the wafer for cutting the wafer.
  • the extension metal pad electrically contacts at least one of the plurality of intergraded circuit devices.
  • the first conductive bump is on the extension metal pad.
  • the insulator layer is over the at least one of the plurality of intergraded circuit devices and in the at least one groove. The insulator layer covers a sidewall of the at least one of the plurality of intergraded circuit devices.
  • Materials for the extension metal pad may be titanium (Ti), an alloy of titanium and tungsten (TiW), chromium (Cr), copper (Cu), or combinations thereof.
  • Materials for the insulator layer pad may be epoxy, polyimide, benzocycle butane, a liquid crystal polymer, or combinations thereof.
  • the insulator layer may be formed by a printing process.
  • the package structure may further include a second conductive bump on the first conductive bump, and a surface metal layer on the second conductive bump.
  • At least one of the first conductive bump and the second conductive bump may include a plurality of metal particles and a polymer compound, or pure metal.
  • the plurality of metal particles may be made of copper, nickel, silver, gold, or combinations thereof.
  • a size of each metal particle may be in a range of 1 to 10 micrometers ( ⁇ m).
  • Polymer compound can be epoxy, a liquid crystal polymer, or combinations thereof.
  • a volume ratio of the plurality metal particles to the polymer compound is greater than 85:15.
  • the first conductive bump and the second conductive bump may be formed by a printing process. Materials for the surface metal layer may be nickel, gold, or combinations thereof.
  • the package structure further includes a metal wall on the first conductive bump.
  • Materials for the metal wall may include nickel, copper, gold, or combinations thereof.
  • the package structure may further include a metal pad between the at least one of the plurality of integrated circuit devices and the extension metal pad.
  • the metal pad can electrically connects the extension metal pad and the at least one of the plurality of the integrated circuit devices.
  • An area of the extension metal pad is bigger than an area of the metal pad.
  • the package structure may further include a passivation layer between the at least one of the plurality of integrated circuit devices and the extension metal pad.
  • a material of the metal pad may be aluminum (Al).
  • the passivation layer may be made of silicon oxynitride (SiNO).
  • Another aspect of the present invention is to provide a package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer.
  • the package structure includes an extension metal pad, a first conductive bump, and an insulator layer.
  • the extension metal pad electrically contacts the at least one of the plurality of intergraded circuit devices.
  • the first conductive bump is on the extension metal pad.
  • the insulator layer is over the at least one of the plurality of intergraded circuit devices and on a sidewall of the at least one of the plurality of intergraded circuit devices.
  • a material of the extension metal pad may include titanium, an alloy of titanium and tungsten, chromium, copper, or combinations thereof.
  • Materials for the insulator layer may include epoxy, polyimide, benzocycle butane, a liquid crystal polymer, or combinations thereof.
  • the insulator layer may be formed by a printing process.
  • the package structure may further include a second conductive bump on the first extension metal pad, and a surface metal layer on the second conductive bump.
  • At least one of the first conductive bump and the second conductive bump may include a plurality of metal particles and a polymer compound.
  • the plurality of metal particles may be made of copper, nickel, silver, gold, or combinations thereof.
  • a size of each metal particle may be in a range of 1 to 10 micrometers.
  • Polymer compound can be epoxy, a liquid crystal polymer, or combinations thereof.
  • a volume ratio of the plurality metal particles to the polymer compound is greater than 85:15.
  • the first conductive bump and the second conductive bump may be formed by a printing process.
  • a material of the surface metal layer may include nickel, gold, or combinations thereof.
  • the package structure may further include a metal wall on the first conductive bump.
  • Materials for the metal wall may include nickel, copper, gold, or combinations thereof.
  • the package structure may further include a metal pad between the at least one of the plurality of integrated circuit devices and the extension metal pad.
  • the metal pad can electrically connects the extension metal pad and the at least one of the plurality of the integrated circuit devices. Furthermore, an area of the extension metal pad is bigger than an area of the metal pad.
  • the package structure may further include a passivation layer between the at least one of the plurality of integrated circuit devices and the extension metal pad.
  • a material of the metal pad may include aluminum (Al).
  • the passivation layer may be made of silicon oxynitride (SiNO).
  • Another aspect of the present invention is to provide a method of forming a package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer.
  • the method includes forming at least one groove in the wafer; forming an extension metal pad electrically contacting the at least one of the plurality of intergraded circuit devices; forming a first conductive bump on the extension metal pad; and forming an insulator layer over the plurality of intergraded circuit devices and in the at least one groove.
  • the wafer is cut at the at least one groove to obtain a plurality of packaged chips, wherein the insulator layer covers a sidewall of the at least one of the plurality of intergraded circuit devices.
  • the foregoing method of forming the package structure may further include assembling at least one of the plurality of packaged chips to a substrate having an interconnect structure.
  • Materials for the interconnect structure may include a solder, a silver paste, or combinations thereof.
  • the substrate may be a flexible printed circuit (FPC), a printed circuit board (PCB), or a ceramics.
  • the step of assembling may include bonding the at least one of plurality of packaged chips on the interconnect structure by a surface mounting technique (SMT).
  • SMT surface mounting technique
  • Materials for the extension metal pad may be titanium, an alloy of titanium and tungsten, chromium, copper, or combinations thereof.
  • Materials for the insulator layer may include epoxy, polyimide, benzocycle butane, a liquid crystal polymer, or combinations thereof.
  • the step of forming the insulator layer over the plurality of intergraded circuit devices and in the at least one groove may include printing an insulator layer over the plurality of intergraded circuit devices and in the at least one groove.
  • the foregoing method of forming the package structure may further include forming a second conductive bump on the first conductive bump, and forming a surface metal layer on the second conductive bump.
  • At least one of the step of forming the first conductive bump on the extension metal pad and the step of forming the second conductive bump on the first conductive bump may include forming a conductive bump having a plurality of metal particles and a polymer compound.
  • the plurality of metal particles may be copper, nickel, silver, gold, or combinations thereof.
  • a size of each metal particle may be in a range of 1 to 10 micrometers.
  • the polymer compound may be made of epoxy, a liquid crystal polymer, or combinations thereof.
  • a volume ratio of the plurality metal particles to the polymer compound may be greater than 85:15.
  • the step of forming the first conductive bump on the extension metal pad and the step of forming the second conductive bump on the first conductive bump may include printing the first conductive bump on the extension metal pad and printing the second conductive bump on the first conductive bump, respectively.
  • Materials for the surface metal layer may be nickel, gold, or combinations thereof.
  • the foregoing method of forming the package structure may further include forming a metal wall on the first conductive bump.
  • Materials for the metal wall may include nickel, copper, gold, or combinations thereof.
  • the foregoing method of forming the package structure may further include forming a metal pad between the at least one of the plurality of integrated circuit devices and the extension metal pad.
  • the metal pad can electrically connects the extension metal pad and the at least one of the plurality of the integrated circuit devices.
  • an area of the extension metal pad is bigger than an area of the metal pad.
  • the foregoing method of forming the package structure may further include forming a passivation layer between the at least one of the plurality of integrated circuit devices and the extension metal pad.
  • a material of the metal pad may be aluminum (Al).
  • Materials for the passivation layer may be silicon oxynitride (SiNO).
  • FIG. 1A to FIG. 1H are cross-sectional views illustrating a method of forming a package structure in accordance with an embodiment of the present invention.
  • FIG. 1A to FIG. 1H are cross-sectional views illustrating a method of forming a package structure 100 in accordance with an embodiment of the present invention, and the package structure 100 formed by the method.
  • the package structure 100 is for packaging at least one of a plurality of intergraded circuit devices of a wafer.
  • the wafer 102 has a plurality of the integrated circuit devices 104 , a metal pad 108 and a passivation layer 110 .
  • the metal pad 108 and the passivation layer 110 are formed on the plurality of the integrated circuit devices 104 .
  • the present invention is described below by one integrated device 104 , but not limited thereto.
  • the method includes forming at least one groove 106 in the wafer 102 .
  • the groove 106 namely a scribe line, is used to divide the wafer into multiple chips.
  • an extension metal pad 112 is formed to electrically contact the integrated circuit device 104 .
  • the extension metal pad 112 is connected to the integrated circuit device 104 via the metal pad 108 , and an area of the extension metal pad 112 is bigger than that of the metal pad 108 .
  • the extension metal pad 112 may be made of titanium, an alloy of titanium and tungsten, chromium, copper, or combinations thereof, or any material which can electrically contact the integrated circuit devices 104 .
  • the metal pad 108 may be made of aluminum, or any material which can electrically connect the extension metal pad 112 to the integrated circuit device 104 .
  • the passivation layer 110 is made of silicon oxynitride (SiNO), or any materials for protecting the integrated circuit device 104 .
  • a first conductive bump 114 is formed on the extension metal pad 112 .
  • the first conductive bump 114 may optionally include a plurality of metal particles and a polymer compound, or pure metal.
  • the plurality of metal particles may be made of copper, nickel, silver, gold, or combinations thereof, but not limited thereto.
  • a size of each metal particle may be in a range of 1 to 10 micrometers.
  • the polymer compound may be made of epoxy, a liquid crystal polymer, or combinations thereof, but not limited thereto.
  • a volume ratio of the plurality metal particles to the polymer compound is greater than 85:15.
  • the step of forming the first conductive bump 114 on the extension metal pad 112 may be formed by a printing process.
  • the method may also include optionally forming a metal wall 116 on the first conductive bump 114 .
  • the metal wall 116 can enhance the conductivity of the first conductive bump 114 .
  • Materials for the metal wall 116 may include nickel, copper, gold, or combinations thereof.
  • an insulator layer 118 is formed over the intergraded circuit device 104 and in the groove 106 .
  • the insulator layer 118 may also be formed over the sidewall of the first conductive bump 114 optionally covered with metal wall 116 and the extension metal pad 112 . Because the groove 106 is adjacent to the intergraded circuit device 104 , the insulator layer 118 filled in the groove will 106 will cover the sidewall of the intergraded circuit device 104 after the wafer is divided to multiple chips, such that the integrated circuit device 104 is entirely protected.
  • the insulator layer 118 may be made of epoxy, polyimide, benzocycle butane, a liquid crystal polymer, or combinations thereof, or any material for protecting the integrated circuit device 104 .
  • the insulator layer 118 may be formed by a printing process.
  • the method may include removing a portion of the insulator layer 118 to expose the first conductive bump 114 .
  • a second conductive bump 120 is formed on the first conductive bump 114 , and a surface metal layer 122 is optionally formed on the second conductive layer 120 , so that an exemplary packaged structure 100 is obtained.
  • the second conductive bump 120 may optionally include a plurality of metal particles and a polymer compound.
  • the plurality of metal particles can be made of copper, nickel, silver, gold, or combinations thereof.
  • a size of each metal particle may be in a range of 1 to 10 micrometers ( ⁇ m).
  • Polymer compound can be epoxy, a liquid crystal polymer, or combinations thereof.
  • a volume ratio of the plurality metal particles to the polymer compound is greater than 85:15.
  • the step of forming the second conductive bump 120 on the first conductive bump 114 may be conducted by a printing process.
  • the surface metal layer 122 may be made of nickel, gold, or combinations thereof, or any material which can facilitate the connections of the package structure 100 with other devices.
  • the wafer 102 is removed. Then, the wafer 102 is cut at the groove 106 to obtain a plurality of packaged chips. For example, the plurality of the packaged chips are separated along the dotted line L. Thus, the insulator layer 108 filled in the groove 106 covers the sidewall of the integrated circuit devices 104 , such that the integrated circuit device 104 is more entirely protected.
  • the packaged chip may assemble to a substrate 224 .
  • the substrate 224 is formed with an interconnect structure 226 and a conductive wire 228 .
  • Materials for the interconnect structure 226 may be a solder, a silver paste, or combinations thereof, or any material, which can optionally cover the second conductive bump 120 and the surface metal layer 122 as well as connecting with the substrate 224 .
  • the substrate 24 may be a flexible printed circuit (FPC), a printed circuit board (PCB), or a ceramics substrate.
  • the assembling step is conducted by bonding the packaged chips with the interconnect structure 226 using a surface mounting technique (SMT).
  • SMT surface mounting technique

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of intergraded circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of intergraded circuit devices and on a sidewall of it.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 12/116,152 entitled “PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE” filed on May 6, 2008, which application claims the right of priority based on Taiwan Patent Application No. 96116302 entitled “Package Structure for Integrated Circuit Device and Method of the Same,” filed on May 8, 2007, which are incorporated herein by reference and assigned to the assignee herein.
    • FIELD OF THE INVENTION
  • This invention relates to a package structure for intergraded circuit devices and a method of the same, and more particularly, relates to a wafer level package structure for intergraded circuit devices and a method of the same.
    • BACKGROUND OF THE INVENTION
  • In a conventional wafer level package process, package materials are only applied on the top of the wafer. After the packaging step, the wafer is cut into multiple chips and therefore the sidewall of each chip is exposed without being protected by the package materials.
  • Accordingly, it is desired to provide a package structure for intergraded circuit device and a method of forming the same, in which the sidewall of the integrated circuit device is protected.
    • SUMMARY OF THE INVENTION
  • In light of the foregoing, it is one object of the present invention to provide package structures for integrated circuit devices and a method of the same in which the sidewalls of the integrated circuit devices is protected.
  • One aspect of the present invention is to provide a package structure. The package structure includes a wafer having a plurality of intergraded circuit devices, at least one groove, an extension metal pad, a first conductive bump, and an insulator layer. The at least one groove is in the wafer for cutting the wafer. The extension metal pad electrically contacts at least one of the plurality of intergraded circuit devices. The first conductive bump is on the extension metal pad. The insulator layer is over the at least one of the plurality of intergraded circuit devices and in the at least one groove. The insulator layer covers a sidewall of the at least one of the plurality of intergraded circuit devices.
  • Materials for the extension metal pad may be titanium (Ti), an alloy of titanium and tungsten (TiW), chromium (Cr), copper (Cu), or combinations thereof. Materials for the insulator layer pad may be epoxy, polyimide, benzocycle butane, a liquid crystal polymer, or combinations thereof. The insulator layer may be formed by a printing process.
  • The package structure may further include a second conductive bump on the first conductive bump, and a surface metal layer on the second conductive bump. At least one of the first conductive bump and the second conductive bump may include a plurality of metal particles and a polymer compound, or pure metal. The plurality of metal particles may be made of copper, nickel, silver, gold, or combinations thereof. A size of each metal particle may be in a range of 1 to 10 micrometers (μm). Polymer compound can be epoxy, a liquid crystal polymer, or combinations thereof. A volume ratio of the plurality metal particles to the polymer compound is greater than 85:15. The first conductive bump and the second conductive bump may be formed by a printing process. Materials for the surface metal layer may be nickel, gold, or combinations thereof.
  • The package structure further includes a metal wall on the first conductive bump. Materials for the metal wall may include nickel, copper, gold, or combinations thereof.
  • The package structure may further include a metal pad between the at least one of the plurality of integrated circuit devices and the extension metal pad. The metal pad can electrically connects the extension metal pad and the at least one of the plurality of the integrated circuit devices. An area of the extension metal pad is bigger than an area of the metal pad. The package structure may further include a passivation layer between the at least one of the plurality of integrated circuit devices and the extension metal pad. A material of the metal pad may be aluminum (Al). The passivation layer may be made of silicon oxynitride (SiNO).
  • Another aspect of the present invention is to provide a package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer. The package structure includes an extension metal pad, a first conductive bump, and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of intergraded circuit devices. The first conductive bump is on the extension metal pad. The insulator layer is over the at least one of the plurality of intergraded circuit devices and on a sidewall of the at least one of the plurality of intergraded circuit devices.
  • A material of the extension metal pad may include titanium, an alloy of titanium and tungsten, chromium, copper, or combinations thereof. Materials for the insulator layer may include epoxy, polyimide, benzocycle butane, a liquid crystal polymer, or combinations thereof. The insulator layer may be formed by a printing process.
  • The package structure may further include a second conductive bump on the first extension metal pad, and a surface metal layer on the second conductive bump. At least one of the first conductive bump and the second conductive bump may include a plurality of metal particles and a polymer compound. The plurality of metal particles may be made of copper, nickel, silver, gold, or combinations thereof. A size of each metal particle may be in a range of 1 to 10 micrometers. Polymer compound can be epoxy, a liquid crystal polymer, or combinations thereof. A volume ratio of the plurality metal particles to the polymer compound is greater than 85:15. The first conductive bump and the second conductive bump may be formed by a printing process. A material of the surface metal layer may include nickel, gold, or combinations thereof.
  • The package structure may further include a metal wall on the first conductive bump. Materials for the metal wall may include nickel, copper, gold, or combinations thereof.
  • The package structure may further include a metal pad between the at least one of the plurality of integrated circuit devices and the extension metal pad. The metal pad can electrically connects the extension metal pad and the at least one of the plurality of the integrated circuit devices. Furthermore, an area of the extension metal pad is bigger than an area of the metal pad. The package structure may further include a passivation layer between the at least one of the plurality of integrated circuit devices and the extension metal pad. A material of the metal pad may include aluminum (Al). The passivation layer may be made of silicon oxynitride (SiNO).
  • Another aspect of the present invention is to provide a method of forming a package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer. The method includes forming at least one groove in the wafer; forming an extension metal pad electrically contacting the at least one of the plurality of intergraded circuit devices; forming a first conductive bump on the extension metal pad; and forming an insulator layer over the plurality of intergraded circuit devices and in the at least one groove. Subsequently, the wafer is cut at the at least one groove to obtain a plurality of packaged chips, wherein the insulator layer covers a sidewall of the at least one of the plurality of intergraded circuit devices.
  • The foregoing method of forming the package structure may further include assembling at least one of the plurality of packaged chips to a substrate having an interconnect structure. Materials for the interconnect structure may include a solder, a silver paste, or combinations thereof. The substrate may be a flexible printed circuit (FPC), a printed circuit board (PCB), or a ceramics. The step of assembling may include bonding the at least one of plurality of packaged chips on the interconnect structure by a surface mounting technique (SMT).
  • Materials for the extension metal pad may be titanium, an alloy of titanium and tungsten, chromium, copper, or combinations thereof. Materials for the insulator layer may include epoxy, polyimide, benzocycle butane, a liquid crystal polymer, or combinations thereof. The step of forming the insulator layer over the plurality of intergraded circuit devices and in the at least one groove may include printing an insulator layer over the plurality of intergraded circuit devices and in the at least one groove.
  • Alternatively, the foregoing method of forming the package structure may further include forming a second conductive bump on the first conductive bump, and forming a surface metal layer on the second conductive bump. At least one of the step of forming the first conductive bump on the extension metal pad and the step of forming the second conductive bump on the first conductive bump may include forming a conductive bump having a plurality of metal particles and a polymer compound. The plurality of metal particles may be copper, nickel, silver, gold, or combinations thereof. A size of each metal particle may be in a range of 1 to 10 micrometers. The polymer compound may be made of epoxy, a liquid crystal polymer, or combinations thereof. A volume ratio of the plurality metal particles to the polymer compound may be greater than 85:15. The step of forming the first conductive bump on the extension metal pad and the step of forming the second conductive bump on the first conductive bump may include printing the first conductive bump on the extension metal pad and printing the second conductive bump on the first conductive bump, respectively. Materials for the surface metal layer may be nickel, gold, or combinations thereof.
  • The foregoing method of forming the package structure may further include forming a metal wall on the first conductive bump. Materials for the metal wall may include nickel, copper, gold, or combinations thereof.
  • The foregoing method of forming the package structure may further include forming a metal pad between the at least one of the plurality of integrated circuit devices and the extension metal pad. The metal pad can electrically connects the extension metal pad and the at least one of the plurality of the integrated circuit devices. Moreover, an area of the extension metal pad is bigger than an area of the metal pad. Additionally, the foregoing method of forming the package structure may further include forming a passivation layer between the at least one of the plurality of integrated circuit devices and the extension metal pad. A material of the metal pad may be aluminum (Al). Materials for the passivation layer may be silicon oxynitride (SiNO).
  • The objects and the features of the present invention may best be understood by reference to the detailed description with the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A to FIG. 1H are cross-sectional views illustrating a method of forming a package structure in accordance with an embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1A to FIG. 1H are cross-sectional views illustrating a method of forming a package structure 100 in accordance with an embodiment of the present invention, and the package structure 100 formed by the method. The package structure 100 is for packaging at least one of a plurality of intergraded circuit devices of a wafer.
  • First, referring to FIG. 1A, the wafer 102 has a plurality of the integrated circuit devices 104, a metal pad 108 and a passivation layer 110. The metal pad 108 and the passivation layer 110 are formed on the plurality of the integrated circuit devices 104. The present invention is described below by one integrated device 104, but not limited thereto. In the embodiment, the method includes forming at least one groove 106 in the wafer 102. In this embodiment, the groove 106, namely a scribe line, is used to divide the wafer into multiple chips.
  • Subsequently, referring to FIG. 1B, an extension metal pad 112 is formed to electrically contact the integrated circuit device 104. In this embodiment, the extension metal pad 112 is connected to the integrated circuit device 104 via the metal pad 108, and an area of the extension metal pad 112 is bigger than that of the metal pad 108. The extension metal pad 112 may be made of titanium, an alloy of titanium and tungsten, chromium, copper, or combinations thereof, or any material which can electrically contact the integrated circuit devices 104. The metal pad 108 may be made of aluminum, or any material which can electrically connect the extension metal pad 112 to the integrated circuit device 104. The passivation layer 110 is made of silicon oxynitride (SiNO), or any materials for protecting the integrated circuit device 104.
  • In FIG. 1C, a first conductive bump 114 is formed on the extension metal pad 112. The first conductive bump 114 may optionally include a plurality of metal particles and a polymer compound, or pure metal. The plurality of metal particles may be made of copper, nickel, silver, gold, or combinations thereof, but not limited thereto. A size of each metal particle may be in a range of 1 to 10 micrometers. The polymer compound may be made of epoxy, a liquid crystal polymer, or combinations thereof, but not limited thereto. A volume ratio of the plurality metal particles to the polymer compound is greater than 85:15. The step of forming the first conductive bump 114 on the extension metal pad 112 may be formed by a printing process.
  • In an embodiment, the method may also include optionally forming a metal wall 116 on the first conductive bump 114. The metal wall 116 can enhance the conductivity of the first conductive bump 114. Materials for the metal wall 116 may include nickel, copper, gold, or combinations thereof.
  • Then, referring to FIG. 1D, an insulator layer 118 is formed over the intergraded circuit device 104 and in the groove 106. In this embodiment, the insulator layer 118 may also be formed over the sidewall of the first conductive bump 114 optionally covered with metal wall 116 and the extension metal pad 112. Because the groove 106 is adjacent to the intergraded circuit device 104, the insulator layer 118 filled in the groove will 106 will cover the sidewall of the intergraded circuit device 104 after the wafer is divided to multiple chips, such that the integrated circuit device 104 is entirely protected. The insulator layer 118 may be made of epoxy, polyimide, benzocycle butane, a liquid crystal polymer, or combinations thereof, or any material for protecting the integrated circuit device 104. The insulator layer 118 may be formed by a printing process.
  • Referring to FIG. 1E, in the embodiment, the method may include removing a portion of the insulator layer 118 to expose the first conductive bump 114. Referring to FIG. 1F, subsequently, a second conductive bump 120 is formed on the first conductive bump 114, and a surface metal layer 122 is optionally formed on the second conductive layer 120, so that an exemplary packaged structure 100 is obtained. The second conductive bump 120 may optionally include a plurality of metal particles and a polymer compound. The plurality of metal particles can be made of copper, nickel, silver, gold, or combinations thereof. A size of each metal particle may be in a range of 1 to 10 micrometers (μm). Polymer compound can be epoxy, a liquid crystal polymer, or combinations thereof. A volume ratio of the plurality metal particles to the polymer compound is greater than 85:15. The step of forming the second conductive bump 120 on the first conductive bump 114 may be conducted by a printing process. The surface metal layer 122 may be made of nickel, gold, or combinations thereof, or any material which can facilitate the connections of the package structure 100 with other devices.
  • Referring to FIG. 1G, after the package structure 100 is formed, at least one portion of the wafer 102 can be removed. Then, the wafer 102 is cut at the groove 106 to obtain a plurality of packaged chips. For example, the plurality of the packaged chips are separated along the dotted line L. Thus, the insulator layer 108 filled in the groove 106 covers the sidewall of the integrated circuit devices 104, such that the integrated circuit device 104 is more entirely protected.
  • Subsequently, referring to FIG. 1H, the packaged chip may assemble to a substrate 224. The substrate 224 is formed with an interconnect structure 226 and a conductive wire 228. Note that the sidewall of the integrated circuit device 104 is covered by the insulator layer 118, such that the integrated circuit device 114 is more entirely protected. Materials for the interconnect structure 226 may be a solder, a silver paste, or combinations thereof, or any material, which can optionally cover the second conductive bump 120 and the surface metal layer 122 as well as connecting with the substrate 224. The substrate 24 may be a flexible printed circuit (FPC), a printed circuit board (PCB), or a ceramics substrate. Moreover, the assembling step is conducted by bonding the packaged chips with the interconnect structure 226 using a surface mounting technique (SMT).
  • Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims.

Claims (10)

1. A method of forming a package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer, the method comprising:
forming at least one groove in the wafer;
forming an extension metal pad electrically contacting the at least one of the plurality of intergraded circuit devices;
forming a first conductive bump on the extension metal pad;
forming an insulator layer over the plurality of intergraded circuit devices and in the at least one groove; and
cutting the wafer at the at least one groove to obtain a plurality of packaged chips;
wherein the insulator layer covers a sidewall of the at least one of the plurality of intergraded circuit devices.
2. The method of claim 1, further comprising:
assembling at least one of the plurality of packaged chips to a substrate having an interconnect structure.
3. The method of claim 1, further comprising:
forming a second conductive bump on the first conductive bump; and
forming a surface metal layer on the second conductive bump.
4. The method of claim 1, further comprising:
forming a metal wall on the first conductive bump.
5. The method of claim 1, further comprising:
forming a metal pad between the at least one of the plurality of integrated circuit devices and the extension metal pad, so that the extension metal pad electrically contacts the at least one of the plurality of the integrated circuit devices;
wherein an area of the extension metal pad is bigger than an area of the metal pad.
6. The method of claim 5, further comprising:
forming a passivation layer between the at least one of the plurality of integrated circuit devices and the extension metal pad.
7. The method of claim 3, wherein at least one of the step of forming the first conductive bump on the extension metal pad and the step of forming the second conductive bump on the first conductive bump comprises forming a conductive bump having a plurality of metal particles and a polymer compound.
8. The method of claim 1, wherein the step of forming the insulator layer over the plurality of intergraded circuit devices and in the at least one groove comprises printing an insulator layer over the plurality of intergraded circuit devices and in the at least one groove.
9. The method of claim 8, wherein a volume ratio of the plurality metal particles to the polymer compound is greater than 85:15.
10. The method of claim 1, wherein the step of forming the insulator layer over the plurality of intergraded circuit devices and in the at least one groove comprises:
covering the first conductive bump by the insulator layer; and
removing a portion of the insulator layer to expose the first conductive bump.
US12/826,510 2007-05-08 2010-06-29 Package structure for integrated circuit device and method of the same Abandoned US20100267204A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110291273A1 (en) * 2010-05-26 2011-12-01 Chipmos Technologies Inc. Chip bump structure and method for forming the same
US20170265841A1 (en) * 2012-12-28 2017-09-21 Volcano Corporation Intravascular ultrasound imaging apparatus, interface architecture, and method of manufacturing

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6273884B1 (en) 1997-05-15 2001-08-14 Palomar Medical Technologies, Inc. Method and apparatus for dermatology treatment
TWI364793B (en) * 2007-05-08 2012-05-21 Mutual Pak Technology Co Ltd Package structure for integrated circuit device and method of the same
US9142533B2 (en) * 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8829676B2 (en) * 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
US9041198B2 (en) * 2013-10-22 2015-05-26 Applied Materials, Inc. Maskless hybrid laser scribing and plasma etching wafer dicing process
CN105097566A (en) * 2015-07-01 2015-11-25 华进半导体封装先导技术研发中心有限公司 Fabrication method for wafer-level fan-out package
US10522505B2 (en) 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same

Citations (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034345A (en) * 1989-08-21 1991-07-23 Fuji Electric Co., Ltd. Method of fabricating a bump electrode for an integrated circuit device
US6107164A (en) * 1998-08-18 2000-08-22 Oki Electric Industry Co., Ltd. Using grooves as alignment marks when dicing an encapsulated semiconductor wafer
US6153448A (en) * 1997-05-14 2000-11-28 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US6316952B1 (en) * 1999-05-12 2001-11-13 Micron Technology, Inc. Flexible conductive structures and method
US6379999B1 (en) * 1999-09-10 2002-04-30 Oki Electric Industry Co., Ltd. Semiconductor device and method of manufacturing the same
US6534387B1 (en) * 1999-12-21 2003-03-18 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US6590257B2 (en) * 2000-10-04 2003-07-08 Oki Electric Industry Co., Ltd. Semiconductor device and method for manufacturing the same, semiconductor wafer and semiconductor device manufactured thereby
US6593658B2 (en) * 1999-09-09 2003-07-15 Siliconware Precision Industries, Co., Ltd. Chip package capable of reducing moisture penetration
US6607970B1 (en) * 1999-11-11 2003-08-19 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US6649445B1 (en) * 2002-09-11 2003-11-18 Motorola, Inc. Wafer coating and singulation method
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US20040155352A1 (en) * 2000-09-13 2004-08-12 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US20040169286A1 (en) * 2000-07-17 2004-09-02 Kazutaka Shibata Semiconductor device and method for manufacturing the same
US6818475B2 (en) * 2001-10-22 2004-11-16 Wen-Kun Yang Wafer level package and the process of the same
US6844957B2 (en) * 2000-11-29 2005-01-18 International Business Machines Corporation Three level stacked reflective display
US20050077619A1 (en) * 2003-10-08 2005-04-14 Shriram Ramanathan Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US20050156297A1 (en) * 1997-10-31 2005-07-21 Farnworth Warren M. Semiconductor package including flex circuit, interconnects and dense array external contacts
US20050242426A1 (en) * 2004-04-30 2005-11-03 Samsung Electronics Co., Ltd. Semiconductor package having a first conductive bump and a second conductive bump and methods for manufacturing the same
US20060079025A1 (en) * 2004-10-12 2006-04-13 Agency For Science, Technology And Research Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices
US20070246819A1 (en) * 2006-04-24 2007-10-25 Micron Technology, Inc. Semiconductor components and systems having encapsulated through wire interconnects (TWI) and wafer level methods of fabrication
US20070296068A1 (en) * 2006-06-26 2007-12-27 Hamilton Sundstrand Corporation In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit
US20080197480A1 (en) * 2007-02-16 2008-08-21 Advanced Chip Engineering Technology Inc. Semiconductor device package with multi-chips and method of the same
US20080197474A1 (en) * 2007-02-16 2008-08-21 Advanced Chip Engineering Technology Inc. Semiconductor device package with multi-chips and method of the same
US20080213976A1 (en) * 2007-03-02 2008-09-04 Micron Technology,Inc. Methods for fabricating semiconductor components and packaged semiconductor components
US7442878B2 (en) * 2004-08-31 2008-10-28 International Business Machines Corporation Low stress conductive polymer bump
US20080315424A1 (en) * 2001-03-30 2008-12-25 Megica Corporation Structure and manufactruing method of chip scale package
US7473582B2 (en) * 2002-08-29 2009-01-06 Micron Technology, Inc. Method for fabricating semiconductor component with thinned substrate having pin contacts
US20090200651A1 (en) * 2003-07-24 2009-08-13 Via Technologies, Inc Multi-chip package
US7586185B2 (en) * 2005-03-28 2009-09-08 Fujitsu Microelectronics Limited Semiconductor device having a functional surface
US7626269B2 (en) * 2006-07-06 2009-12-01 Micron Technology, Inc. Semiconductor constructions and assemblies, and electronic systems
US7713861B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
US7727875B2 (en) * 2007-06-21 2010-06-01 Stats Chippac, Ltd. Grooving bumped wafer pre-underfill system
US7772698B2 (en) * 2007-05-08 2010-08-10 Mutual-Pak Technology Co., Ltd. Package structure for integrated circuit device
US7838424B2 (en) * 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US20110003433A1 (en) * 2009-07-01 2011-01-06 Shinko Electric Industries Co., Ltd. Manufacturing method of semiconductor device
US7888238B2 (en) * 2007-12-12 2011-02-15 Casio Computer Co., Ltd. Method of manufacturing semiconductor device having semiconductor formation regions of different planar sizes
US7935568B2 (en) * 2006-10-31 2011-05-03 Tessera Technologies Ireland Limited Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US20110169159A1 (en) * 2010-01-13 2011-07-14 Chia-Sheng Lin Chip package and fabrication method thereof
US8105856B2 (en) * 2002-04-23 2012-01-31 Semiconductor Components Industries, Llc Method of manufacturing semiconductor device with wiring on side surface thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06151438A (en) * 1992-11-12 1994-05-31 Tanaka Kikinzoku Kogyo Kk Formation of bump with photosensitive conductive paste
JP3660275B2 (en) * 2001-06-14 2005-06-15 シャープ株式会社 Semiconductor device and manufacturing method thereof
JP3951845B2 (en) * 2002-07-24 2007-08-01 カシオ計算機株式会社 Manufacturing method of semiconductor device
JP2005340655A (en) * 2004-05-28 2005-12-08 Shinko Electric Ind Co Ltd Method for manufacturing semiconductor device, and structure for supporting semiconductor substrate
JP4607531B2 (en) * 2004-09-29 2011-01-05 カシオマイクロニクス株式会社 Manufacturing method of semiconductor device

Patent Citations (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034345A (en) * 1989-08-21 1991-07-23 Fuji Electric Co., Ltd. Method of fabricating a bump electrode for an integrated circuit device
US6153448A (en) * 1997-05-14 2000-11-28 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US20050156297A1 (en) * 1997-10-31 2005-07-21 Farnworth Warren M. Semiconductor package including flex circuit, interconnects and dense array external contacts
US6107164A (en) * 1998-08-18 2000-08-22 Oki Electric Industry Co., Ltd. Using grooves as alignment marks when dicing an encapsulated semiconductor wafer
US6316952B1 (en) * 1999-05-12 2001-11-13 Micron Technology, Inc. Flexible conductive structures and method
US6593658B2 (en) * 1999-09-09 2003-07-15 Siliconware Precision Industries, Co., Ltd. Chip package capable of reducing moisture penetration
US6379999B1 (en) * 1999-09-10 2002-04-30 Oki Electric Industry Co., Ltd. Semiconductor device and method of manufacturing the same
US6607970B1 (en) * 1999-11-11 2003-08-19 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US6534387B1 (en) * 1999-12-21 2003-03-18 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US7183191B2 (en) * 2000-06-02 2007-02-27 Micron Technology, Inc. Method for fabricating a chip scale package using wafer level processing
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US20040169286A1 (en) * 2000-07-17 2004-09-02 Kazutaka Shibata Semiconductor device and method for manufacturing the same
US20040155352A1 (en) * 2000-09-13 2004-08-12 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6590257B2 (en) * 2000-10-04 2003-07-08 Oki Electric Industry Co., Ltd. Semiconductor device and method for manufacturing the same, semiconductor wafer and semiconductor device manufactured thereby
US6844957B2 (en) * 2000-11-29 2005-01-18 International Business Machines Corporation Three level stacked reflective display
US20090008778A1 (en) * 2001-03-30 2009-01-08 Megica Corporation Structure and manufactruing method of chip scale package
US20090011542A1 (en) * 2001-03-30 2009-01-08 Megica Corporation Structure and manufactruing method of chip scale package
US20080315424A1 (en) * 2001-03-30 2008-12-25 Megica Corporation Structure and manufactruing method of chip scale package
US6818475B2 (en) * 2001-10-22 2004-11-16 Wen-Kun Yang Wafer level package and the process of the same
US7482702B2 (en) * 2002-03-06 2009-01-27 Micron Technology, Inc. Semiconductor component sealed on five sides by polymer sealing layer
US7221059B2 (en) * 2002-03-06 2007-05-22 Micron Technology, Inc. Wafer level semiconductor component having thinned, encapsulated dice and polymer dam
US7382060B2 (en) * 2002-03-06 2008-06-03 Micron Technology, Inc. Semiconductor component having thinned die, polymer layers, contacts on opposing sides, and conductive vias connecting the contacts
US20060275949A1 (en) * 2002-03-06 2006-12-07 Farnworth Warren M Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors
US7417325B2 (en) * 2002-03-06 2008-08-26 Micron Technology, Inc. Semiconductor component having thinned die with conductive vias configured as conductive pin terminal contacts
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US7432604B2 (en) * 2002-03-06 2008-10-07 Micron Technology, Inc. Semiconductor component and system having thinned, encapsulated dice
US8105856B2 (en) * 2002-04-23 2012-01-31 Semiconductor Components Industries, Llc Method of manufacturing semiconductor device with wiring on side surface thereof
US7473582B2 (en) * 2002-08-29 2009-01-06 Micron Technology, Inc. Method for fabricating semiconductor component with thinned substrate having pin contacts
US6649445B1 (en) * 2002-09-11 2003-11-18 Motorola, Inc. Wafer coating and singulation method
US20090200651A1 (en) * 2003-07-24 2009-08-13 Via Technologies, Inc Multi-chip package
US20050077619A1 (en) * 2003-10-08 2005-04-14 Shriram Ramanathan Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same
US20050242426A1 (en) * 2004-04-30 2005-11-03 Samsung Electronics Co., Ltd. Semiconductor package having a first conductive bump and a second conductive bump and methods for manufacturing the same
US7442878B2 (en) * 2004-08-31 2008-10-28 International Business Machines Corporation Low stress conductive polymer bump
US20060079025A1 (en) * 2004-10-12 2006-04-13 Agency For Science, Technology And Research Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices
US7586185B2 (en) * 2005-03-28 2009-09-08 Fujitsu Microelectronics Limited Semiconductor device having a functional surface
US20070246819A1 (en) * 2006-04-24 2007-10-25 Micron Technology, Inc. Semiconductor components and systems having encapsulated through wire interconnects (TWI) and wafer level methods of fabrication
US20070296068A1 (en) * 2006-06-26 2007-12-27 Hamilton Sundstrand Corporation In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit
US7626269B2 (en) * 2006-07-06 2009-12-01 Micron Technology, Inc. Semiconductor constructions and assemblies, and electronic systems
US7935568B2 (en) * 2006-10-31 2011-05-03 Tessera Technologies Ireland Limited Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US20080197474A1 (en) * 2007-02-16 2008-08-21 Advanced Chip Engineering Technology Inc. Semiconductor device package with multi-chips and method of the same
US20080197480A1 (en) * 2007-02-16 2008-08-21 Advanced Chip Engineering Technology Inc. Semiconductor device package with multi-chips and method of the same
US20080213976A1 (en) * 2007-03-02 2008-09-04 Micron Technology,Inc. Methods for fabricating semiconductor components and packaged semiconductor components
US7772698B2 (en) * 2007-05-08 2010-08-10 Mutual-Pak Technology Co., Ltd. Package structure for integrated circuit device
US7727875B2 (en) * 2007-06-21 2010-06-01 Stats Chippac, Ltd. Grooving bumped wafer pre-underfill system
US7838424B2 (en) * 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US7713861B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
US7888238B2 (en) * 2007-12-12 2011-02-15 Casio Computer Co., Ltd. Method of manufacturing semiconductor device having semiconductor formation regions of different planar sizes
US20110003433A1 (en) * 2009-07-01 2011-01-06 Shinko Electric Industries Co., Ltd. Manufacturing method of semiconductor device
US8129259B2 (en) * 2009-07-01 2012-03-06 Shinko Electric Industries Co., Ltd. Manufacturing method of preparing a substrate with forming and removing the check patterns in scribing regions before dicing to form semiconductor device
US20110169159A1 (en) * 2010-01-13 2011-07-14 Chia-Sheng Lin Chip package and fabrication method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110291273A1 (en) * 2010-05-26 2011-12-01 Chipmos Technologies Inc. Chip bump structure and method for forming the same
US8274150B2 (en) * 2010-05-26 2012-09-25 Chipmos Technologies Inc. Chip bump structure and method for forming the same
US20170265841A1 (en) * 2012-12-28 2017-09-21 Volcano Corporation Intravascular ultrasound imaging apparatus, interface architecture, and method of manufacturing
US10674996B2 (en) * 2012-12-28 2020-06-09 Philips Image Guided Therapy Corporation Intravascular ultrasound imaging apparatus, interface architecture, and method of manufacturing

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TWI364793B (en) 2012-05-21
US20080277785A1 (en) 2008-11-13

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