JP2005101129A - Semiconductor device, its manufacturing method, method of manufacturing semiconductor chip, circuit board, and electronic equipment - Google Patents

Semiconductor device, its manufacturing method, method of manufacturing semiconductor chip, circuit board, and electronic equipment Download PDF

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JP2005101129A
JP2005101129A JP2003331000A JP2003331000A JP2005101129A JP 2005101129 A JP2005101129 A JP 2005101129A JP 2003331000 A JP2003331000 A JP 2003331000A JP 2003331000 A JP2003331000 A JP 2003331000A JP 2005101129 A JP2005101129 A JP 2005101129A
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semiconductor chip
semiconductor device
semiconductor
resin portion
resin
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JP2003331000A
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Japanese (ja)
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Takuya Takahashi
卓也 高橋
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Seiko Epson Corp
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Seiko Epson Corp
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    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the edge of a semiconductor chip and a wire, etc., from coming into contact with each other. <P>SOLUTION: A semiconductor device comprises the semiconductor chip 10 in which an integrated circuit 12 is formed and which contains electrically connected electrodes 14, resins 30 provided in the peripheral edge of the surface of the semiconductor chip 10 on which the electrodes 14 are arranged, and wiring 32 which is joined to the electrodes 14 and formed to get out of the semiconductor chip 10 through the upper sides of the resin sections 30. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法、半導体チップの製造方法、回路基板並びに電子機器に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, a manufacturing method of a semiconductor chip, a circuit board, and an electronic device.

従来、半導体チップの電極に接続されるワイヤは、半導体チップのエッジとの接触を防止するため、ループを描いて設けられていた。近年、半導体装置の薄型化の要求から、ループを低くする必要があり、その場合、ワイヤと半導体チップのエッジとの接触を防止することが難しかった。
特開２００３−１２４４３３号公報 Conventionally, a wire connected to an electrode of a semiconductor chip is provided in a loop in order to prevent contact with the edge of the semiconductor chip. In recent years, it has been necessary to reduce the loop due to the demand for thinner semiconductor devices. In this case, it has been difficult to prevent contact between the wire and the edge of the semiconductor chip.
JP 2003-124433 A

本発明の目的は、半導体チップのエッジとワイヤ等との接触を防止することにある。   An object of the present invention is to prevent contact between an edge of a semiconductor chip and a wire or the like.

（１）本発明に係る半導体装置は、集積回路が形成され、内部に電気的に接続された電極を有する半導体チップと、
前記半導体チップの前記電極が配置された面の周縁部に設けられた樹脂部と、
前記電極に接合されて前記樹脂部の上方を通って前記半導体チップの外側に出るように形成されてなる配線と、
を含む。本発明によれば、樹脂部によって、半導体チップのエッジと配線との接触を防止することができる。
（２）この半導体装置において、
前記半導体チップの前記電極が配置された前記面は、パッシベーション膜の表面であり、
前記樹脂部は、前記パッシベーション膜の前記表面よりも高くなるように形成されていてもよい。
（３）この半導体装置において、
前記電極は、バンプを含み、
前記樹脂部は、前記バンプの高さを超えないように形成されていてもよい。
（４）この半導体装置において、
前記樹脂部は、前記半導体チップの側面に至るように形成されていてもよい。
（５）この半導体装置において、
前記樹脂部は、前記半導体チップの側面に至らないように形成されていてもよい。
（６）この半導体装置において、
前記樹脂部は、前記半導体チップの前記周縁部全体に連続的に形成されていてもよい。
（７）この半導体装置において、
前記配線は、前記樹脂部に接触していてもよい。
（８）本発明に係る回路基板は、上記半導体装置が実装されてなる。
（９）本発明に係る電子機器は、上記半導体装置を有する。
（１０）本発明に係る半導体装置の製造方法は、集積回路が形成された半導体チップの、内部に電気的に接続された電極が配置された面の周縁部に、樹脂部を設けること、及び、
配線を、前記樹脂部の上方を通って、前記半導体チップの外側から前記電極上に至るように設けること、
を含む。本発明によれば、樹脂部によって、半導体チップのエッジと配線との接触を防止することができる。
（１１）本発明に係る半導体チップの製造方法は、複数の集積回路が形成された半導体ウエハに樹脂部を設けること、及び、
前記半導体ウエハを切断すること、
を含み、
前記樹脂部を、前記半導体ウエハの切断ライン上に設け、
前記半導体ウエハを前記樹脂部とともに切断する。本発明によれば、樹脂部によって、半導体チップのエッジとワイヤ等との接触を防止することができる。
（１２）本発明に係る半導体チップの製造方法は、複数の集積回路が形成された半導体ウエハに樹脂部を設けること、及び、
前記半導体ウエハを、切溝を形成しながら切断すること、
を含み、
前記樹脂部を、前記半導体ウエハの前記切溝を形成する領域に一部が入るように、かつ、前記半導体ウエハの切断ラインを避けるように設け、
前記半導体ウエハを切断するときに、前記樹脂部を側方から切削する。本発明によれば、樹脂部によって、半導体チップのエッジとワイヤ等との接触を防止することができる。また、樹脂部をその上面から切断しないので、切断工程を円滑に行うことができる。 (1) A semiconductor device according to the present invention includes a semiconductor chip in which an integrated circuit is formed and having an electrode electrically connected to the inside;
A resin portion provided on a peripheral portion of a surface on which the electrode of the semiconductor chip is disposed;
A wiring formed so as to be bonded to the electrode and to go out of the semiconductor chip through the resin part;
including. According to the present invention, the resin portion can prevent contact between the edge of the semiconductor chip and the wiring.
(2) In this semiconductor device,
The surface on which the electrode of the semiconductor chip is disposed is a surface of a passivation film,
The resin portion may be formed to be higher than the surface of the passivation film.
(3) In this semiconductor device,
The electrode includes a bump,
The resin portion may be formed so as not to exceed the height of the bump.
(4) In this semiconductor device,
The resin portion may be formed so as to reach a side surface of the semiconductor chip.
(5) In this semiconductor device,
The resin portion may be formed so as not to reach the side surface of the semiconductor chip.
(6) In this semiconductor device,
The resin portion may be continuously formed over the entire peripheral portion of the semiconductor chip.
(7) In this semiconductor device,
The wiring may be in contact with the resin portion.
(8) A circuit board according to the present invention has the semiconductor device mounted thereon.
(9) An electronic apparatus according to the present invention includes the semiconductor device.
(10) A method of manufacturing a semiconductor device according to the present invention includes providing a resin portion at a peripheral portion of a surface of an electrode electrically connected to an inside of a semiconductor chip on which an integrated circuit is formed; and ,
Wiring is provided so as to pass over the resin part and reach the electrode from the outside of the semiconductor chip;
including. According to the present invention, the resin portion can prevent contact between the edge of the semiconductor chip and the wiring.
(11) A method of manufacturing a semiconductor chip according to the present invention includes providing a resin portion on a semiconductor wafer on which a plurality of integrated circuits are formed, and
Cutting the semiconductor wafer;
Including
Providing the resin part on a cutting line of the semiconductor wafer;
The semiconductor wafer is cut together with the resin portion. According to the present invention, the resin portion can prevent contact between the edge of the semiconductor chip and the wire or the like.
(12) A semiconductor chip manufacturing method according to the present invention includes providing a resin portion on a semiconductor wafer on which a plurality of integrated circuits are formed, and
Cutting the semiconductor wafer while forming a kerf;
Including
The resin portion is provided so that a part thereof enters a region of the semiconductor wafer where the cut groove is formed, and so as to avoid a cutting line of the semiconductor wafer,
When the semiconductor wafer is cut, the resin portion is cut from the side. According to the present invention, the resin portion can prevent contact between the edge of the semiconductor chip and the wire or the like. Further, since the resin portion is not cut from the upper surface, the cutting process can be performed smoothly.

以下、本発明の実施の形態を、図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の実施の形態に係る半導体装置を説明する図である。半導体装置は、半導体チップ１０を有する。半導体チップ１０には、集積回路１２が形成されている。半導体チップ１０は、内部に電気的に接続された複数の電極１４を有する。複数の電極１４は、集積回路１２に電気的に接続された電極を含む。複数の電極１４は、電気的に、集積回路１２に接続されずに半導体チップ１０の内部に接続された電極を含んでもよい。電極１４は、図１に示すように、バンプ１６を含んでもよい。   FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment of the present invention. The semiconductor device has a semiconductor chip 10. An integrated circuit 12 is formed on the semiconductor chip 10. The semiconductor chip 10 has a plurality of electrodes 14 electrically connected therein. The plurality of electrodes 14 include electrodes that are electrically connected to the integrated circuit 12. The plurality of electrodes 14 may include electrodes that are electrically connected to the inside of the semiconductor chip 10 without being connected to the integrated circuit 12. The electrode 14 may include a bump 16 as shown in FIG.

半導体チップ１０は、パッシベーション膜１８を有していてもよい。パッシベーション膜１８は、無機材料からなる膜（シリコン酸化膜、シリコン窒化膜等）であってもよい。パッシベーション膜１８は、シリコン酸化膜のように透明であってもよいし、不透明であってもよい。パッシベーション膜１８は、各電極１４の一部（例えば中央部のみ）を除いて形成されていてもよい。電極１４が配置された面は、パッシベーション膜１８の表面である。   The semiconductor chip 10 may have a passivation film 18. The passivation film 18 may be a film made of an inorganic material (such as a silicon oxide film or a silicon nitride film). The passivation film 18 may be transparent like a silicon oxide film or may be opaque. The passivation film 18 may be formed excluding a part of each electrode 14 (for example, only the central part). The surface on which the electrode 14 is disposed is the surface of the passivation film 18.

半導体装置は、基板２０を含んでもよい。基板２０は、ポリイミド樹脂等の樹脂から形成されていてもよい。基板２０に半導体チップ１０が搭載されている。例えば、半導体チップ１０の電極１４が配置された面（パッシベーション膜１８の表面）とは反対側の面を、基板２０に接着する。基板２０には、配線パターン２２が形成されている。配線パターン２２が形成された面に半導体チップ１０が搭載されている。   The semiconductor device may include a substrate 20. The substrate 20 may be formed from a resin such as a polyimide resin. The semiconductor chip 10 is mounted on the substrate 20. For example, the surface opposite to the surface on which the electrode 14 of the semiconductor chip 10 is disposed (the surface of the passivation film 18) is bonded to the substrate 20. A wiring pattern 22 is formed on the substrate 20. The semiconductor chip 10 is mounted on the surface on which the wiring pattern 22 is formed.

半導体チップ１０には樹脂部３０が設けられている。樹脂部３０は、電極１４が配置された面の周縁部に設けられている。樹脂部３０は、周縁部全体に連続的に形成されていてもよいし、周縁部に部分的に形成されていてもよい。樹脂部３０は、半導体チップ１０の側面に至るように（例えば側面全体を覆うように）形成してもよいし、さらに、基板２０上に至るように形成してもよい。樹脂部３０は、パッシベーション膜１８の表面よりも高くなるように形成されてもよい。樹脂部３０は、バンプ１６の高さを超えないように形成されてもよい。   The semiconductor chip 10 is provided with a resin portion 30. The resin part 30 is provided at the peripheral edge of the surface on which the electrode 14 is disposed. The resin part 30 may be continuously formed on the entire peripheral part, or may be partially formed on the peripheral part. The resin portion 30 may be formed so as to reach the side surface of the semiconductor chip 10 (for example, so as to cover the entire side surface), or may be formed so as to reach the substrate 20. The resin portion 30 may be formed to be higher than the surface of the passivation film 18. The resin portion 30 may be formed so as not to exceed the height of the bump 16.

樹脂部３０は、電気的絶縁部である。樹脂部３０は、導電性粒子を含まない。樹脂部３０は、応力緩和機能を有してもよい。樹脂部３０は、ポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）等で形成されてもよい。   The resin part 30 is an electrically insulating part. The resin part 30 does not contain conductive particles. The resin part 30 may have a stress relaxation function. The resin portion 30 may be formed of polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like.

半導体装置は、複数の配線３２を有する。本実施の形態では、配線３２は、ワイヤ（金線）である。各配線３２は、いずれかの電極１４（例えばバンプ１６）に接合されている。配線３２は、樹脂部３０の上方を通るように配置されており、樹脂部３０に接触していてもよい。配線３２は、樹脂部３０にめり込むように配置されていてもよい。配線３２は、半導体チップ１０の外側に出るように配置されている。配線３２は、基板２０に形成された配線パターン２２に電気的に接続（例えば接合）されている。本実施の形態によれば、樹脂部３０によって、半導体チップ１０のエッジと配線３２との接触を防止することができる。   The semiconductor device has a plurality of wirings 32. In the present embodiment, the wiring 32 is a wire (gold wire). Each wiring 32 is joined to one of the electrodes 14 (for example, the bump 16). The wiring 32 is disposed so as to pass above the resin portion 30 and may be in contact with the resin portion 30. The wiring 32 may be disposed so as to be embedded in the resin portion 30. The wiring 32 is arranged so as to go outside the semiconductor chip 10. The wiring 32 is electrically connected (for example, joined) to the wiring pattern 22 formed on the substrate 20. According to the present embodiment, the resin portion 30 can prevent contact between the edge of the semiconductor chip 10 and the wiring 32.

半導体装置は、第２の半導体チップ４０を有してもよい。第２の半導体チップ４０には、上述した半導体チップ１０の内容が該当する。第２の半導体チップ４０は、半導体チップ（第１の半導体チップともいう。）１０にスタックされてもよい。第１の半導体チップ１０の電極１４が形成された面の上方（さらに配線３２の上方）に、第２の半導体チップ４０が配置されてもよい。その場合、第１及び第２の半導体チップ１０，４０の間に、スペーサ３４が介在してもよい。スペーサ３４は、第１の半導体チップ１０の電極１４を避けた領域（例えば、電極１４よりも内側の領域）に設けられてもよい。第２の半導体チップ４０は、配線３２と接触しないように配置される。   The semiconductor device may have a second semiconductor chip 40. The contents of the semiconductor chip 10 described above correspond to the second semiconductor chip 40. The second semiconductor chip 40 may be stacked on a semiconductor chip (also referred to as a first semiconductor chip) 10. The second semiconductor chip 40 may be disposed above the surface of the first semiconductor chip 10 where the electrode 14 is formed (further above the wiring 32). In that case, a spacer 34 may be interposed between the first and second semiconductor chips 10 and 40. The spacer 34 may be provided in a region where the electrode 14 of the first semiconductor chip 10 is avoided (for example, a region inside the electrode 14). The second semiconductor chip 40 is disposed so as not to contact the wiring 32.

第２の半導体チップ４０には樹脂部（第２の樹脂部ともいう。）４２が設けられている。第２の樹脂部４２は、第２の半導体チップ４０の側面に至らないように形成されている。それ以外の構成について、第２の樹脂部４２には、樹脂部（第１の樹脂部ともいう。）３０の内容が該当する。   The second semiconductor chip 40 is provided with a resin portion (also referred to as a second resin portion) 42. The second resin portion 42 is formed so as not to reach the side surface of the second semiconductor chip 40. Regarding the other configuration, the content of the resin portion (also referred to as the first resin portion) 30 corresponds to the second resin portion 42.

第２の半導体チップ４０の電極１４（バンプ１６）には、配線（第２の配線ともいう。）４４が接合されている。配線４４は、ワイヤ（金線）である。配線４４は、第２の樹脂部４２の上方を通るように配置されており、第２の樹脂部４２に接触していてもよい。配線４４は、第２の樹脂部４２にめり込むように配置されていてもよい。配線４４は、第２の半導体チップ４０の外側に出るように配置されている。配線４４は、基板２０に形成された配線パターン２２に電気的に接続（例えば接合）されている。   A wiring (also referred to as second wiring) 44 is bonded to the electrode 14 (bump 16) of the second semiconductor chip 40. The wiring 44 is a wire (gold wire). The wiring 44 is disposed so as to pass above the second resin portion 42, and may be in contact with the second resin portion 42. The wiring 44 may be disposed so as to be embedded in the second resin portion 42. The wiring 44 is disposed so as to come out of the second semiconductor chip 40. The wiring 44 is electrically connected (for example, joined) to the wiring pattern 22 formed on the substrate 20.

半導体装置は、封止部５０を含んでもよい。封止部５０は、第１及び第２の半導体チップ１０，４０の配線３２，４４との接合部、配線３２，４４、配線パターン２２の配線３２，４４との接合部のうち少なくともいずれかの箇所を封止している。   The semiconductor device may include a sealing unit 50. The sealing portion 50 is at least one of a junction between the first and second semiconductor chips 10 and 40 and the wirings 32 and 44, a wiring 32 and 44, and a junction between the wiring pattern 22 and the wirings 32 and 44. The part is sealed.

半導体装置は、複数の外部端子（例えばハンダボール）５２を含んでもよい。外部端子５２は、基板２０によって支持されるように設けられており、基板２０に形成されたスルーホール（図示せず）によって、配線パターン２２と電気的に接続されてもよい。外部端子５２は、ランド２４上に設けてもよい。外部端子５２は、基板２０の配線パターン２２が形成された面とは反対側に設けられてもよい。外部端子５２は、軟ろう（soft solder）又は硬ろう（hard solder）のいずれで形成してもよい。軟ろうとして、鉛を含まないハンダ（以下、鉛フリーハンダという。）を使用してもよい。鉛フリーハンダとして、スズ−銀（Ｓｎ−Ａｇ）系、スズ−ビスマス（Ｓｎ−Ｂｉ）系、スズ−亜鉛（Ｓｎ−Ｚｎ）系、あるいはスズ−銅（Ｓｎ−Ｃｕ）系の合金を使用してもよいし、これらの合金に、さらに銀、ビスマス、亜鉛、銅のうち少なくとも１つを添加してもよい。   The semiconductor device may include a plurality of external terminals (for example, solder balls) 52. The external terminal 52 is provided so as to be supported by the substrate 20, and may be electrically connected to the wiring pattern 22 through a through hole (not shown) formed in the substrate 20. The external terminal 52 may be provided on the land 24. The external terminal 52 may be provided on the side opposite to the surface on which the wiring pattern 22 of the substrate 20 is formed. The external terminal 52 may be formed of either soft solder or hard solder. As the soft solder, solder containing no lead (hereinafter referred to as lead-free solder) may be used. As lead-free solder, tin-silver (Sn-Ag), tin-bismuth (Sn-Bi), tin-zinc (Sn-Zn), or tin-copper (Sn-Cu) alloys are used. Alternatively, at least one of silver, bismuth, zinc, and copper may be added to these alloys.

次に、本実施の形態に係る半導体装置の製造方法を説明する。本実施の形態では、図２に示すように、半導体チップ１０を基板２０に搭載し、両者を接着剤等で固定してもよい。また、半導体チップ１０の電極１４が配置された面の周縁部に樹脂部３０を設ける。樹脂部３０は、樹脂ペーストで形成してもよい。その形成方法は、ポッティング法、インクジェット等の吐出法、スクリーン印刷等の印刷法、塗布法などのいずれであってもよい。樹脂部３０の形状及び配置については、上述した通りである。   Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. In the present embodiment, as shown in FIG. 2, the semiconductor chip 10 may be mounted on the substrate 20 and both may be fixed with an adhesive or the like. In addition, the resin portion 30 is provided on the peripheral portion of the surface on which the electrode 14 of the semiconductor chip 10 is disposed. The resin part 30 may be formed of a resin paste. The forming method may be any of a potting method, a discharge method such as inkjet, a printing method such as screen printing, and a coating method. The shape and arrangement of the resin part 30 are as described above.

図３に示すように、配線３２を樹脂部３０の上方を通るように設ける。配線３２は、半導体チップ１０の外側から電極１４至るように設ける。本実施の形態では、配線３２を、電極１４及び配線パターン２２に接合する。配線３２としてワイヤを使用し、ワイヤを配線パターン２２に先にボンディング（ファーストボンディング）した後に、電極１４にボンディング（セカンドボンディング）する。ワイヤボンディングでは、ファーストボンディング後に、ワイヤを上方に引き出すことが必要であるが、セカンドボンディングは、ワイヤを横方向に引き出して行うことができる。配線パターン２２が電極１４よりも低い位置にあるため、配線パターン２２に対してファーストボンディングを行い、高い位置にある電極１４に対してセカンドボンディングを行うことで、ワイヤループの高さを低くすることができる。これにより、半導体装置の薄型化が可能である。   As shown in FIG. 3, the wiring 32 is provided so as to pass above the resin portion 30. The wiring 32 is provided so as to reach the electrode 14 from the outside of the semiconductor chip 10. In the present embodiment, the wiring 32 is bonded to the electrode 14 and the wiring pattern 22. A wire is used as the wiring 32, and the wire is first bonded to the wiring pattern 22 (first bonding) and then bonded to the electrode 14 (second bonding). In wire bonding, it is necessary to pull out the wire upward after the first bonding, but second bonding can be performed by pulling out the wire in the lateral direction. Since the wiring pattern 22 is at a position lower than the electrode 14, first bonding is performed on the wiring pattern 22, and second bonding is performed on the electrode 14 at a higher position, thereby reducing the height of the wire loop. Can do. Thereby, the semiconductor device can be thinned.

図４（Ａ）〜図４（Ｃ）は、本実施の形態に係る半導体装置の製造方法の変形例を説明する図である。上述したのは、個々の半導体装置の一部となる個片の基板２０を使用したプロセスであるが、複数の基板２０が一体化した基板を使用して、複数の半導体装置を同時に製造してもよい。例えば、図４（Ａ）に示すように、基板６０に複数の半導体チップ１０を搭載する。図４（Ｂ）に示すように、半導体チップ１０に樹脂部３０を設ける。スクリーン印刷を適用すれば、複数の樹脂部３０を同時に設けることができる。図４（Ｃ）に示すように、配線３２を設ける。基板６０は、その後、一点鎖線で示すラインで切断されて個々の半導体装置が得られる。   4A to 4C are diagrams for explaining a modification of the method for manufacturing the semiconductor device according to the present embodiment. The above-described process is a process using individual substrates 20 that are part of individual semiconductor devices, but a plurality of semiconductor devices are manufactured simultaneously using a substrate in which a plurality of substrates 20 are integrated. Also good. For example, as shown in FIG. 4A, a plurality of semiconductor chips 10 are mounted on a substrate 60. As shown in FIG. 4B, the resin portion 30 is provided on the semiconductor chip 10. If screen printing is applied, a plurality of resin parts 30 can be provided simultaneously. As shown in FIG. 4C, a wiring 32 is provided. Thereafter, the substrate 60 is cut along a line indicated by a one-dot chain line to obtain individual semiconductor devices.

次に、図１に示すように、第２の半導体チップ４０を第１の半導体チップ１０上にスタックしてもよい。第１及び第２の半導体チップ１０，４０の間に、スペーサ３４を介在させてもよい。第２の半導体チップ４０の電極１４が配置された面の周縁部に第２の樹脂部４２を設ける。第２の樹脂部４２は、第１の半導体チップ１０上に第２の半導体チップ４０をスタックした後に設けてもよい。あるいは、予め、第２の樹脂部４２が設けられた第２の半導体チップ４０を用意してもよい。   Next, as shown in FIG. 1, the second semiconductor chip 40 may be stacked on the first semiconductor chip 10. A spacer 34 may be interposed between the first and second semiconductor chips 10 and 40. A second resin portion 42 is provided on the periphery of the surface on which the electrode 14 of the second semiconductor chip 40 is disposed. The second resin portion 42 may be provided after stacking the second semiconductor chip 40 on the first semiconductor chip 10. Or you may prepare the 2nd semiconductor chip 40 in which the 2nd resin part 42 was provided previously.

図５（Ａ）及び図５（Ｂ）は、樹脂部が設けられた半導体チップの第１の製造方法を説明する図である。図５（Ａ）に示すように、複数の集積回路１２が形成された半導体ウエハ７０に樹脂部７２を設ける。樹脂部７２は、半導体ウエハ７０の切断ライン上に設ける。そして、半導体ウエハ７０を樹脂部７２とともに切断する。切断にはカッタ７４を使用してもよい。こうして、図５（Ｂ）に示すように、第２の樹脂部４２が設けられた第２の半導体チップ４０を製造することができる。   FIG. 5A and FIG. 5B are views for explaining a first method for manufacturing a semiconductor chip provided with a resin portion. As shown in FIG. 5A, a resin portion 72 is provided on a semiconductor wafer 70 on which a plurality of integrated circuits 12 are formed. The resin part 72 is provided on the cutting line of the semiconductor wafer 70. Then, the semiconductor wafer 70 is cut together with the resin portion 72. A cutter 74 may be used for cutting. Thus, as shown in FIG. 5B, the second semiconductor chip 40 provided with the second resin portion 42 can be manufactured.

図６（Ａ）〜図６（Ｃ）は、樹脂部が設けられた半導体チップの第２の製造方法を説明する図である。図６（Ａ）に示すように、複数の集積回路１２が形成された半導体ウエハ７０に樹脂部７６を設ける。樹脂部７６は、半導体ウエハ７０を切断するときの切溝７８（図６（Ｂ）参照）を形成する領域に一部が入るように形成する。また、樹脂部７６は、半導体ウエハ７０の切断ラインを避けるように設ける。そして、図６（Ｂ）に示すように、半導体ウエハ７０を、切溝７８を形成しながら切断する。半導体ウエハ７０を切断するときに、樹脂部７６を側方から切削する。こうして、図６（Ｃ）に示すように、樹脂部８２を有する半導体チップ８０を製造することができる。半導体チップ８０は、側面が傾斜していてもよい。   FIGS. 6A to 6C are diagrams illustrating a second method for manufacturing a semiconductor chip provided with a resin portion. As shown in FIG. 6A, a resin portion 76 is provided on a semiconductor wafer 70 on which a plurality of integrated circuits 12 are formed. The resin portion 76 is formed so as to partially enter a region where a kerf 78 (see FIG. 6B) for cutting the semiconductor wafer 70 is formed. The resin portion 76 is provided so as to avoid the cutting line of the semiconductor wafer 70. Then, as shown in FIG. 6B, the semiconductor wafer 70 is cut while forming a kerf 78. When the semiconductor wafer 70 is cut, the resin portion 76 is cut from the side. Thus, as shown in FIG. 6C, the semiconductor chip 80 having the resin portion 82 can be manufactured. The semiconductor chip 80 may have an inclined side surface.

次に、図１に示すように、配線４４を、第２の半導体チップ４０の電極１４及び配線パターン２２に接合する。その詳細は、配線３２に関する内容が該当する。また、必要に応じて、封止部５０を形成し、外部端子５２を設ける。その詳細は上述した通りである。本実施の形態に係る半導体装置の製造方法は、上述した半導体装置の構成から自明な内容を含む。本実施の形態によれば、樹脂部３０，４２によって、半導体チップ１０，４０のエッジと配線３２，４４との接触を防止することができる。   Next, as shown in FIG. 1, the wiring 44 is bonded to the electrode 14 and the wiring pattern 22 of the second semiconductor chip 40. The details correspond to the contents related to the wiring 32. Moreover, the sealing part 50 is formed and the external terminal 52 is provided as needed. The details are as described above. The manufacturing method of the semiconductor device according to the present embodiment includes self-evident content from the configuration of the semiconductor device described above. According to the present embodiment, the resin portions 30 and 42 can prevent contact between the edges of the semiconductor chips 10 and 40 and the wirings 32 and 44.

図７〜図１０は、本発明の実施の形態に係る半導体装置の変形例を説明する図である。   7-10 is a figure explaining the modification of the semiconductor device which concerns on embodiment of this invention.

図７に示す半導体装置は、１つの半導体チップ１０に他の半導体チップがスタックされない形態であり、第２の樹脂部４２及び配線４４も有しない。その他の詳細は、図１に示す半導体装置の内容が該当する。   The semiconductor device shown in FIG. 7 has a configuration in which no other semiconductor chip is stacked on one semiconductor chip 10 and does not have the second resin portion 42 and the wiring 44. The other details correspond to the contents of the semiconductor device shown in FIG.

図８に示す半導体装置は、図７に示す例で、樹脂部３０の代わりに樹脂部４２を設けてある。その他の詳細は、図１に示す半導体装置の内容が該当する。   The semiconductor device shown in FIG. 8 is the example shown in FIG. 7, and a resin portion 42 is provided instead of the resin portion 30. The other details correspond to the contents of the semiconductor device shown in FIG.

図９に示す半導体装置は、デバイスホール９２が形成された基板９０と、デバイスホイール９２内に一部が突出するように基板９０に形成された配線（リード）９４と、半導体チップ４０と、を有する。そして、配線９４と電極１４（バンプ１６）が接合されている。半導体チップ４０には、樹脂部４２が設けられている。この半導体装置の製造には、ＴＡＢ（Tape Automated Bonding）技術を適用することができる。その他の詳細は、図１に示す半導体装置の内容が該当する。   The semiconductor device shown in FIG. 9 includes a substrate 90 on which a device hole 92 is formed, wirings (leads) 94 formed on the substrate 90 so as to partially protrude into the device wheel 92, and a semiconductor chip 40. Have. The wiring 94 and the electrode 14 (bump 16) are joined. The semiconductor chip 40 is provided with a resin portion 42. A TAB (Tape Automated Bonding) technique can be applied to the manufacture of this semiconductor device. The other details correspond to the contents of the semiconductor device shown in FIG.

図１０に示す半導体装置は、配線（リード（例えばインナーリード））９６と、半導体チップ４０と、を有する。そして、配線９６と電極１４（バンプ１６）が接合されている。この半導体装置の製造には、リードフレームを使用してもよい。その場合、リードフレームの一部が配線（リード）９６となる。半導体チップ４０には、樹脂部４２が設けられている。その他の詳細は、図１に示す半導体装置の内容が該当する。   The semiconductor device shown in FIG. 10 includes wiring (leads (for example, inner leads)) 96 and a semiconductor chip 40. And the wiring 96 and the electrode 14 (bump 16) are joined. A lead frame may be used for manufacturing the semiconductor device. In that case, a part of the lead frame becomes a wiring (lead) 96. The semiconductor chip 40 is provided with a resin portion 42. The other details correspond to the contents of the semiconductor device shown in FIG.

図１１には、上述した実施の形態で説明した半導体装置１が実装された回路基板１０００が示されている。この半導体装置を有する電子機器として、図１２にはノート型パーソナルコンピュータ２０００が示され、図１３には携帯電話３０００が示されている。   FIG. 11 shows a circuit board 1000 on which the semiconductor device 1 described in the above embodiment is mounted. As an electronic apparatus having this semiconductor device, a notebook personal computer 2000 is shown in FIG. 12, and a mobile phone 3000 is shown in FIG.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。さらに、本発明は、実施の形態で説明した技術的事項のいずれかを限定的に除外した内容を含む。あるいは、本発明は、上述した実施の形態から公知技術を限定的に除外した内容を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment. Furthermore, the present invention includes contents that exclude any of the technical matters described in the embodiments in a limited manner. Or this invention includes the content which excluded the well-known technique limitedly from embodiment mentioned above.

図１は、本発明の実施の形態に係る半導体装置を説明する図である。FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment of the present invention. 図２は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 図３は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。FIG. 3 is a diagram for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. 図４（Ａ）〜図４（Ｃ）は、半導体装置の製造方法の変形例を説明する図である。4A to 4C are diagrams illustrating a modification of the method for manufacturing a semiconductor device. 図５（Ａ）〜図５（Ｂ）は、本発明の実施の形態に係る半導体チップの第１の製造方法を説明する図である。FIGS. 5A to 5B are views for explaining a first method for manufacturing a semiconductor chip according to the embodiment of the present invention. 図６（Ａ）〜図６（Ｃ）は、本発明の実施の形態に係る半導体チップの第２の製造方法を説明する図である。FIG. 6A to FIG. 6C are diagrams for explaining a second method for manufacturing a semiconductor chip according to the embodiment of the present invention. 図７は、半導体装置の変形例を説明する図である。FIG. 7 is a diagram illustrating a modification of the semiconductor device. 図８は、半導体装置の変形例を説明する図である。FIG. 8 is a diagram illustrating a modification of the semiconductor device. 図９は、半導体装置の変形例を説明する図である。FIG. 9 is a diagram illustrating a modification of the semiconductor device. 図１０は、半導体装置の変形例を説明する図である。FIG. 10 is a diagram illustrating a modification of the semiconductor device. 図１１は、本実施の形態に係る半導体装置が実装された回路基板を示す図である。FIG. 11 is a diagram showing a circuit board on which the semiconductor device according to the present embodiment is mounted. 図１２は、本実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 12 illustrates an electronic device having the semiconductor device according to this embodiment. 図１３は、本実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 13 is a diagram illustrating an electronic apparatus including the semiconductor device according to this embodiment.

符号の説明Explanation of symbols

１０…半導体チップ １２…集積回路 １４…電極 １６…バンプ １８…パッシベーション膜 ２０…基板 ２２…配線パターン ３０…樹脂部 ３２…配線 ３４…スペーサ ４０…第２の半導体チップ ４２…第２の樹脂部 ４４…配線 ５０…封止部 ５２…外部端子 ６０…基板 ７０…半導体ウエハ ７２…樹脂部 ７４…カッタ ７６…樹脂部 ７８…切溝 ８０…半導体チップ ８２…樹脂部 ９０…基板 ９２…デバイスホール ９４…配線 ９６…配線   DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip 12 ... Integrated circuit 14 ... Electrode 16 ... Bump 18 ... Passivation film 20 ... Substrate 22 ... Wiring pattern 30 ... Resin part 32 ... Wiring 34 ... Spacer 40 ... Second semiconductor chip 42 ... Second resin part 44 ... Wiring 50 ... Sealing part 52 ... External terminal 60 ... Substrate 70 ... Semiconductor wafer 72 ... Resin part 74 ... Cutter 76 ... Resin part 78 ... Cut groove 80 ... Semiconductor chip 82 ... Resin part 90 ... Substrate 92 ... Device hole 94 ... Wiring 96 ... wiring

Claims (12)

集積回路が形成され、内部に電気的に接続された電極を有する半導体チップと、
前記半導体チップの前記電極が配置された面の周縁部に設けられた樹脂部と、
前記電極に接合されて前記樹脂部の上方を通って前記半導体チップの外側に出るように形成されてなる配線と、
を含む半導体装置。 A semiconductor chip in which an integrated circuit is formed and having an electrode electrically connected to the inside;
A resin portion provided on a peripheral portion of a surface on which the electrode of the semiconductor chip is disposed;
A wiring formed so as to be bonded to the electrode and to go out of the semiconductor chip through the resin part;
A semiconductor device including: 請求項１記載の半導体装置において、
前記半導体チップの前記電極が配置された前記面は、パッシベーション膜の表面であり、
前記樹脂部は、前記パッシベーション膜の前記表面よりも高くなるように形成されてなる半導体装置。 The semiconductor device according to claim 1,
The surface on which the electrode of the semiconductor chip is disposed is a surface of a passivation film,
The semiconductor device, wherein the resin portion is formed to be higher than the surface of the passivation film. 請求項１又は請求項２記載の半導体装置において、
前記電極は、バンプを含み、
前記樹脂部は、前記バンプの高さを超えないように形成されてなる半導体装置。 The semiconductor device according to claim 1 or 2,
The electrode includes a bump,
The resin part is a semiconductor device formed so as not to exceed the height of the bump. 請求項１から請求項３のいずれかに記載の半導体装置において、
前記樹脂部は、前記半導体チップの側面に至るように形成されてなる半導体装置。 The semiconductor device according to any one of claims 1 to 3,
The resin part is a semiconductor device formed so as to reach a side surface of the semiconductor chip. 請求項１から請求項３のいずれかに記載の半導体装置において、
前記樹脂部は、前記半導体チップの側面に至らないように形成されてなる半導体装置。 The semiconductor device according to any one of claims 1 to 3,
The semiconductor device is formed such that the resin portion does not reach the side surface of the semiconductor chip. 請求項１から請求項５のいずれかに記載の半導体装置において、
前記樹脂部は、前記半導体チップの前記周縁部全体に連続的に形成されてなる半導体装置。 The semiconductor device according to any one of claims 1 to 5,
The said resin part is a semiconductor device formed continuously in the said peripheral part of the said semiconductor chip. 請求項１から請求項６のいずれかに記載の半導体装置において、
前記配線は、前記樹脂部に接触してなる半導体装置。 The semiconductor device according to any one of claims 1 to 6,
The wiring is a semiconductor device in contact with the resin portion. 請求項１から請求項７のいずれかに記載の半導体装置が実装されてなる回路基板。   A circuit board on which the semiconductor device according to claim 1 is mounted. 請求項１から請求項７のいずれかに記載の半導体装置を有する電子機器。   An electronic apparatus comprising the semiconductor device according to claim 1. 集積回路が形成された半導体チップの、内部に電気的に接続された電極が配置された面の周縁部に、樹脂部を設けること、及び、
配線を、前記樹脂部の上方を通って、前記半導体チップの外側から前記電極上に至るように設けること、
を含む半導体装置の製造方法。 Providing a resin portion on the periphery of the surface of the semiconductor chip on which the integrated circuit is formed, on which the electrically connected electrodes are disposed; and
Wiring is provided so as to pass over the resin part and reach the electrode from the outside of the semiconductor chip;
A method of manufacturing a semiconductor device including: 複数の集積回路が形成された半導体ウエハに樹脂部を設けること、及び、
前記半導体ウエハを切断すること、
を含み、
前記樹脂部を、前記半導体ウエハの切断ライン上に設け、
前記半導体ウエハを前記樹脂部とともに切断する半導体チップの製造方法。 Providing a resin portion on a semiconductor wafer on which a plurality of integrated circuits are formed; and
Cutting the semiconductor wafer;
Including
Providing the resin part on a cutting line of the semiconductor wafer;
A method of manufacturing a semiconductor chip, wherein the semiconductor wafer is cut together with the resin portion. 複数の集積回路が形成された半導体ウエハに樹脂部を設けること、及び、
前記半導体ウエハを、切溝を形成しながら切断すること、
を含み、
前記樹脂部を、前記半導体ウエハの前記切溝を形成する領域に一部が入るように、かつ、前記半導体ウエハの切断ラインを避けるように設け、
前記半導体ウエハを切断するときに、前記樹脂部を側方から切削する半導体チップの製造方法。 Providing a resin portion on a semiconductor wafer on which a plurality of integrated circuits are formed; and
Cutting the semiconductor wafer while forming a kerf;
Including
The resin portion is provided so that a part thereof enters a region of the semiconductor wafer where the cut groove is formed, and so as to avoid a cutting line of the semiconductor wafer,
A method for manufacturing a semiconductor chip, wherein the resin part is cut from a side when the semiconductor wafer is cut.
JP2003331000A 2003-09-24 2003-09-24 Semiconductor device, its manufacturing method, method of manufacturing semiconductor chip, circuit board, and electronic equipment Withdrawn JP2005101129A (en)

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