TWI364082B - Method for testing a semiconductor wafer prior to performing a flip chip bumping process and an interface assembly for said semiconductor wafer - Google Patents

Method for testing a semiconductor wafer prior to performing a flip chip bumping process and an interface assembly for said semiconductor wafer Download PDF

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Publication number
TWI364082B
TWI364082B TW094132327A TW94132327A TWI364082B TW I364082 B TWI364082 B TW I364082B TW 094132327 A TW094132327 A TW 094132327A TW 94132327 A TW94132327 A TW 94132327A TW I364082 B TWI364082 B TW I364082B
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TW
Taiwan
Prior art keywords
pad
test
redistribution layer
adhesive
metal
Prior art date
Application number
TW094132327A
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English (en)
Other versions
TW200633102A (en
Inventor
Mark Bachman
Daniel Patrick Chesire
Taeho Kook
Sailesh Mansinh Merchant
Original Assignee
Agere Systems Inc
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Application filed by Agere Systems Inc filed Critical Agere Systems Inc
Publication of TW200633102A publication Critical patent/TW200633102A/zh
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

1364082 (1) 九、發明說明 【發明所屬之技術領域】 本發明關係於晶圓裝置，更明確地說，關係於用以在 覆晶組件中，執行接合製程前，完成晶圓級測試的結構與 技術。 【先前技術】 於背景中，覆晶微電子組件大致表示以在晶片黏著墊 上之導電凸塊，將朝下（以此爲”反覆"）的電子元件直接電 連接至基板、電路板或載板。比較下，打線璋合技術一般 使用朝上晶片，並對每一墊有線連接。覆晶技術尤其具有 致能實質輸入/輸出（I/O)連接彈性。例如，打線接合連接 大致被限制至晶粒的圓周，當連接數增加，則驅動晶粒尺 寸增加。例如區域陣列凸塊的覆晶連接法可以使用晶粒的 整個區域，以容納在較小晶粒上之更多連接》 第1圖爲半導體裝置之金屬接合墊8(例如鋁或銅接 合墊）的俯視代表圖，其包含一凸塊區1〇，在該金屬接合 墊8上。第1圖用以顯示在先前技術中所遭受的困難。凸 塊區10可以爲在鈍化層中之鈍化開口 12加以定義，該鈍 化層包圍該接合墊，該凸塊區中被執行一接合製程，以建 立用於該覆晶組件的導電凸塊（例如焊錫凸塊）》 已知對於使用覆晶技術的半導體裝置中，大致並不想 要在執行接合製程前，經由金屬接合墊’以執行晶圓級測 試，而來驗證電路功能。例如’一被放置與接合墊接觸之 -5- (2) ' 1364082 測試探棒可能挖開金屬墊表面。在接合墊上之表面不規 則，對於在一或更多金屬層上建立及維持強力黏著會造成 困難，該等金屬層係在凸塊形成時加以沉積。例如，在凸 塊形成前，稱爲凸塊底層金屬（UBM)允許製造一阻障金 屬，以防止金屬墊與焊錫凸塊間之相互作用。UBM結構 包含"黏著層”，其對黏著墊金屬及周圍之鈍化層都作良好 黏著，以提供強力低應力之電機連接。同樣地，可以沉積 # 一 "擴散阻障_'層，以限制焊錫之擴散入下層之材料中》 針對前述事項的已知嘗試涉及週邊測試墊的結構，該 等測試墊係實體分開，但藉由內連線電連接至黏著墊。此 等結構在本技藝中被稱爲"重分佈層（RDL)。已經看到此等 RDL內連線可能對測試信號，引入不想要之傳遞延遲，此 等延遲可能造成較低之裝置速度。於銅黏著墊中，在最上 層使用鋁合金RDL可能造成額外的成本，因爲鋁RDL的 製造需要沉積、圖型化及蝕刻之額外製程步驟。再者，使 # 用鋁RDL·可能造成較低之裝置良率，因爲增加了製程步 驟’而增加了不想要微粒的或然率，因此，限制了良率。 對於涉及覆晶連接之半導體的少用的提議以用於打線 接合連接之方法被LoisYoung等人所描述於2003年5月 之IEEE公告"電子元件及技術會議”的第1 3 23至1 3 29頁 中。此方法大致需要將至少兩實際不同金屬墊彼此相互堆 疊’以形成一探測區，其係與打線接合區分開。更明確地 說’此提議方法需要堆疊加大鋁蓋層之一部份至在鋁蓋層 下之銅塾上。加大鋁蓋層的剩餘部份（例如測試區所在）係 -6 - (3) 1364082 安排在介電材料上，此配置因爲探棒可能在測試區上施加 相當大之力量，而可能在介電層中，造成破裂。再者，在 銅墊上之鋁"蓋墊"的特定要求並不是一設計考量，因爲對 銅執行打線接合對於一涉及打線接合連接的生產環境係很 困難。並無此等考量可應用至覆晶連接。 另一已知嘗試涉及在接合製程執行後，測試晶圓。爲 了不同考量，此嘗試也未能提供完全滿意的解答。例如， • 此接合後測試技術可能造成成本之增加，因爲有可能該接 合程序（已花用大量時間及資源）已經在故障晶圓中執行， 該故障晶圓應在繼續此凸塊製程前如以丟棄。再者，吾人 可能不能指出可能在接合製程本身發生的誤處理步驟，除 非診斷分區硏究在該晶圓上被執行。 因此，吾人想要提供結構與技術，以在一接合製程 前，允許半導體裝置或晶圓被測試，使得可以在不犧牲金 屬接合墊的整體性及不對用於測試目的之信號造成延遲情 _ 形下，採用晶圓級測試。 【發明內容及實施方式】 第2圖爲實施例本發明態樣之例示覆晶介面組件20 的俯視圖》更明確地說，第2圖例示一導電測試墊22， 與一導電黏著墊24建構爲一體。此配置至少提供以下優 點：導電測試墊22提供個別之測試區26，其中可以放置一 探棒尖端，用以例如執行晶圓級測試。黏著墊24包含~ 凸塊區28’其不再受到探棒尖端的機械接觸，及所造成 (4) 1364082 之表面不規則。可以想到因爲測試墊及黏著墊包含 結構，所以，其也不再需要內連線並避免或實質降 其間之測試信號的傳遞延遲。實施本發明態樣的介 應造成更可靠及正確之測試結果。 第2圖更顯示分別於測試區26及凸塊區28的 化開口 30及32。應了解的是，金屬黏著墊24的 不限定於多角形，因爲其他幾何形狀也可以等效地 # 屬黏著墊。例如，第4圖例示用於金屬黏著墊44 形狀。 同樣地，測試墊22的形狀並不限定於正方形 爲其他幾何形狀，例如，矩形、三角形等也可以等 作。同時，測試墊22的相對於黏著墊24之定位並 於特定取向。例如，第2圖顯示一例示配置，其中 墊22係定位於六點鐘位置，而第3圖示出另一 置，其測試墊22係位在三點鐘位置。因此，可以 •.試墊可以沿著黏著墊的週邊一體建構。 第5圖例示一例示實施例，其中，實施例本發 的介面組件5 0可以組合一或多數金屬再分佈層， 屬再分佈層52及54，用以連接金屬黏著墊24至 屬配線或內連線，或其他墊，不論是直接或經由導 如導孔56。於一例示實施例中，金屬再分佈層52 黏著墊24及測試墊22共平面，及藉由導孔56電 至金屬再分佈層52的金屬再分佈層54可以定位在 黏著墊24與測試墊22不同的位準。可以了解，這 有一體 低通過 面組件 個別鈍 形狀並 用於金 的圓形 狀，因 效地動 不限定 ，測試 例示配 了解測 明態樣 例如金 例如金 孔，例 可以與 氣連接 相對於 些再分 -8- (5) (5)1364082 佈層52及54可以用以連接黏著墊至晶片的其他區域，不 全然是於先前技術中及後述之連接至週邊黏著墊。 雖然本發明的較佳實施例已經顯示及說明，但可以了 解的是，此等實施例係只提供作例子用。各種變化、改變 及替換將爲熟習於本技藝者在不脫離本發明的範圍下加以 完成。因此’本發明只爲隨附之申請專利範圍及精神所限 制。 【圖式簡單說明】 第1圖爲具有用以接合及測試半導體晶圓之共同區之 先前技術金屬覆晶接合墊的俯視圖。 第2圖爲實施本發明態樣之例示覆晶介面組件之俯視 圖。 第3及4圖爲被一體建構有黏著墊之黏著墊及/或測 試墊之例示配置圖。 第5圖爲一例示實施例，其中可以有可以實施例本發 明態樣的介面組件，可以用以組合一或多數金屬再分佈 層。 【主要元件符號說明】 10 凸塊區 12 鈍化開口 20 覆晶介面組件 22 導電測試墊 -9 - 1364082
(6) 24 導 電 黏 著 墊 26 測 試 28 凸 塊 lop 30 純 化 開 P 32 純 化 開 □ 50 介 面 組 件 52 金 屬 再 分 佈 層 54 金 屬 再 分 佈 層 56 導 孔 8 金 屬 黏 著 墊
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Claims (1)

1364082 附件5A:第094132327號專利申請案中文申請專利範圍修正本 民國100年12月26日修正 十、申請專利範圍 K 一種用於半導體晶圓的介面組件，該介面組件包含： —覆晶黏著墊包含一區域，用以執行接合製程； 一測試墊，與該黏著墊架構爲一體，形成一整合導電 結構’使得來自該測試墊至該黏著墊的分開互連測試線並 φ 未出現在該整合導電結構中，該測試墊係相對於該覆晶黏 著墊呈共平面並包含一測試區，用以在執行該接合製程 前’執行晶圓級測試； 一第一金屬再分佈層電氣連接至該黏著墊及測試墊， 並彼此與該第一金屬再分佈層共平面；以及 該第一金屬再分佈層係電氣連接至該黏著墊及測試 墊’並彼此共平面，該第一金屬再分佈層係經由一導孔電 連接至一第二再分佈層，該第二再分佈層被安排在與第一 φ 金屬再分佈層不同的平面上。 2 .如申請專利範圍第1項所述之介面組件，其中該測 試墊可以安置在沿著該黏著墊週邊的任意處。 3 .如申請專利範圍第1項所述之介面組件，其中該黏 著墊包含由多角形、及圓形所構成之群組所選出之形狀。 4.如申請專利範圍第1項所述之介面組件，其中該測 試墊包含由多角形、及圓形所構成之群組所選出之形狀。 5 .如申請專利範圍第1項所述之介面組件，其中該予 以被接合之區域係被在鈍化層中之第一開口所定義。 1364082 6 ·如申請專利範圍第5項所述之介面組件，其中該測 試區係由在該鈍化層中之第二開口所定義，及該第一及第 二開口係彼此分隔開。 7.—種在執行覆晶接合製程之前測試半導體晶圓的方 法，包含步驟： 提供一覆晶黏著墊，其具有一區域，用以執行該接合 製程‘； 與該黏著墊爲一體地建構一測試墊，以形成整合導電 結構，使得由該測試墊至該黏著墊的分開互連測試線並未 出現在該整合導電結構中，該測試墊係相對於該覆晶黏著 墊爲共平面，並包含一測試區，用以在執行該接合製程 前’執行該晶圓級測試； 形成一第一金屬再分佈層電氣連接至該黏著墊及測試 墊，並彼此與該第一金屬再分佈層共平面；以及 形成該第一金屬再分佈層電氣連接至該黏著墊及該測 試墊，並彼此共平面，該第一金屬再分佈層經由一導孔電 連接至一第二再分佈層，該第二再分佈層係被安排在與第 一金屬再分佈層不同的平面上。
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Families Citing this family (11)

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Publication number Priority date Publication date Assignee Title
JP2008177422A (ja) * 2007-01-19 2008-07-31 Toshiba Corp プリント回路板及び電子機器
US8987014B2 (en) * 2008-05-21 2015-03-24 Stats Chippac, Ltd. Semiconductor wafer and method of forming sacrificial bump pad for wafer probing during wafer sort test
WO2013010512A2 (en) * 2012-10-22 2013-01-24 Spreadtrum Communications (Shanghai) Co., Ltd. Apparatus and method of electrical testing for flip chip
CN103779250B (zh) * 2012-10-22 2017-02-15 展讯通信（上海）有限公司 用于倒装芯片的电学测试的装置和方法
US9207275B2 (en) 2012-12-14 2015-12-08 International Business Machines Corporation Interconnect solder bumps for die testing
CN105593981B (zh) * 2013-09-23 2018-06-05 展讯通信（上海）有限公司 一种倒装芯片的扇出装置和方法
JP6215755B2 (ja) 2014-04-14 2017-10-18 ルネサスエレクトロニクス株式会社 半導体装置
KR102372355B1 (ko) 2015-08-26 2022-03-11 삼성전자주식회사 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지
US10199318B2 (en) * 2016-05-19 2019-02-05 Mediatek Inc. Semiconductor package assembly
JP6767789B2 (ja) * 2016-06-29 2020-10-14 ローム株式会社 半導体装置
BR102019017782A2 (pt) * 2019-08-27 2022-03-03 Ceitec - Centro Nacional De Tecnologia Eletrônica Avançada S.A. Método de montagem de chip com pads de teste expostos e chip com pads de teste expostos

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JPH07201865A (ja) * 1993-12-31 1995-08-04 Casio Comput Co Ltd バンプを備えた半導体装置
TW396480B (en) * 1994-12-19 2000-07-01 Matsushita Electric Ind Co Ltd Semiconductor chip and semiconductor wafer with power pads used for probing test
JPH10116834A (ja) * 1996-10-11 1998-05-06 Toshiba Corp 半導体装置の製造方法
JP2002090422A (ja) * 2000-09-13 2002-03-27 Toshiba Corp 半導体装置及びその製造方法
US6359342B1 (en) * 2000-12-05 2002-03-19 Siliconware Precision Industries Co., Ltd. Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same
TW546804B (en) * 2001-11-16 2003-08-11 Advanced Semiconductor Eng Electric testing method for bumps
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