CN105593981B - 一种倒装芯片的扇出装置和方法 - Google Patents
一种倒装芯片的扇出装置和方法 Download PDFInfo
- Publication number
- CN105593981B CN105593981B CN201380079765.2A CN201380079765A CN105593981B CN 105593981 B CN105593981 B CN 105593981B CN 201380079765 A CN201380079765 A CN 201380079765A CN 105593981 B CN105593981 B CN 105593981B
- Authority
- CN
- China
- Prior art keywords
- detecting
- instruction
- bump pad
- fanned out
- convex block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2013/083970 WO2015039339A1 (en) | 2013-09-23 | 2013-09-23 | Apparatus and method for fanout of flip chip |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105593981A CN105593981A (zh) | 2016-05-18 |
CN105593981B true CN105593981B (zh) | 2018-06-05 |
Family
ID=52688127
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201380079765.2A Active CN105593981B (zh) | 2013-09-23 | 2013-09-23 | 一种倒装芯片的扇出装置和方法 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN105593981B (zh) |
WO (1) | WO2015039339A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10381278B2 (en) | 2017-09-14 | 2019-08-13 | Powertech Technology Inc. | Testing method of packaging process and packaging structure |
BR102019017782A2 (pt) * | 2019-08-27 | 2022-03-03 | Ceitec - Centro Nacional De Tecnologia Eletrônica Avançada S.A. | Método de montagem de chip com pads de teste expostos e chip com pads de teste expostos |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6359342B1 (en) * | 2000-12-05 | 2002-03-19 | Siliconware Precision Industries Co., Ltd. | Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same |
CN101556899A (zh) * | 2008-04-10 | 2009-10-14 | 中芯国际集成电路制造(上海)有限公司 | 一种晶圆制造工艺的标记方法与系统 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7221173B2 (en) * | 2004-09-29 | 2007-05-22 | Agere Systems, Inc. | Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process |
-
2013
- 2013-09-23 CN CN201380079765.2A patent/CN105593981B/zh active Active
- 2013-09-23 WO PCT/CN2013/083970 patent/WO2015039339A1/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6359342B1 (en) * | 2000-12-05 | 2002-03-19 | Siliconware Precision Industries Co., Ltd. | Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same |
CN101556899A (zh) * | 2008-04-10 | 2009-10-14 | 中芯国际集成电路制造(上海)有限公司 | 一种晶圆制造工艺的标记方法与系统 |
Also Published As
Publication number | Publication date |
---|---|
WO2015039339A1 (en) | 2015-03-26 |
CN105593981A (zh) | 2016-05-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20190314 Address after: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee after: Xin Xin finance leasing (Beijing) Co.,Ltd. Address before: 201203 Building 1, exhibition hall, 2288 lane, 2288 Chong, road, Zhangjiang hi tech park, Shanghai Patentee before: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. |
|
TR01 | Transfer of patent right | ||
EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20160518 Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Assignor: Xin Xin finance leasing (Beijing) Co.,Ltd. Contract record no.: X2021110000008 Denomination of invention: A flip chip fan out device and method Granted publication date: 20180605 License type: Exclusive License Record date: 20210317 |
|
EE01 | Entry into force of recordation of patent licensing contract | ||
TR01 | Transfer of patent right |
Effective date of registration: 20221031 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288 Patentee after: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Address before: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee before: Xin Xin finance leasing (Beijing) Co.,Ltd. |
|
TR01 | Transfer of patent right |