WO2015039339A1

WO2015039339A1 - Apparatus and method for fanout of flip chip

Info

Publication number: WO2015039339A1
Application number: PCT/CN2013/083970
Authority: WO
Inventors: Xuhai GUO
Original assignee: Spreadtrum Communications (Shanghai) Co., Ltd.
Priority date: 2013-09-23
Filing date: 2013-09-23
Publication date: 2015-03-26
Also published as: CN105593981B; CN105593981A

Abstract

The present invention relates to apparatus and method for fanout of flip chip. If a bump pad on the flip chip is determined to comprise a test portion for electrical test, an indication of the test portion may be generated in a profile associated with the bump pad, such that the test portion is excluded from being used in the fanout. In this way, it is possible to avoid performing the fanout on the test portion where the probe marks might be left by the probe tips. Accordingly, reliability and accuracy of the bumping process and any other subsequent processes can be significantly improved.

Description

APPARATUS AND METHOD FOR FANOUT OF FLIP CHIP

FIELD OF THE INVENTION

[0001] Embodiments of the present invention generally relate to the field of flip chips, and more particularly, to a method, system, and computer program product for fanout of flip chips.

BACKGROUND OF THE INVENTION

[0002] In general, a semiconductor device is produced through a series of processes such as manufacturing, electrical die sorting (EDS) and packaging. Electrical test like the EDS process is used to test various electrical characteristics of the semiconductor wafer. During the EDS process, the chips with and without defects may be separated from each other. If the defects may be repaired or fixed, the chips will go through a repair procedure for later use. On the other hand, for those chips on which the defects cannot be fixed, the wafer's units will be discarded. The test process may use various probe devices, like probe cards, to test the electrical characteristics of the chips.

[0003] A probe card is equipped with one or more tips for contacting the bump pads on a chip to detect any defects. Typically, probe cards can be classified into the cantilever type and the vertical type. The cantilever probe cards have excellent performances, for example, for those chips on which the pads are located proximate to the edges. The vertical probe card is generally applicable to a wafer where the pads may be located at any positions on the dies. The vertical probe card may have flat tips or point tips. The vertical probe card with flat tips is usually more cost effective than the one with point tips because the flat tips usually have longer life time. [0004] With the integrated circuits becoming smaller in size and higher in speed, it is sometimes difficult to apply wire bonding technology in packaging chips with a great number of input/output (I/O) pads. Accordingly, attention has been drawn to the flip chip packaging technology. As known, a flip chip may include bumps in the form of solders or copper pillar. When using a probe card to test the electrical characteristics, the probe will inevitably leave some marks on the contact areas on the pads during operation, and these marks in turn degrade the performance and/or reliability of the chips. For example, for solder bumps, the probe marks may cause one or more voids between the bumps and the UBM, which will weaken the coupling strength and make the bumps displace or even drop during solder reflow procedure. For copper pillars, the strong stress in the UBM plating process is very likely to crash the copper pillars down or cause crakes in the passivation layer.

[0005] In order to address the above problem, there has been proposed a kind of pad for use on flip chips on which at least two separate portions are arranged. A test portion is dedicated to the electrical test while a bump portion is used for bumping without any contact with the probe tips during test. Alternatively, the test pads may be integrally constructed with the bumping pads. However, such kind of pads is not suitable for the traditional fanout. As used in the context of the present application, the term "fanout" refers to a procedure for fanning out routing traces, for example, on the redistribution layer ( DL) of the pad. Specifically, for each bump pad, a routing trace(s) may be fanned out from an I/O cell pad to a certain point on the bump pad, for example. Traditional fanout cannot recognize the different portions on a bump pad. More specifically, the routing traces will always be fanned out from/to the center point of the whole bump pad. The fanout point therefore may be located in the test portion on which there might be probe marks and/or surface irregularities left by the probe tips during the test period. As a result, reliability and accuracy of subsequent bumping or other processes may be decreased.

[0006] In view of foregoing, there is a need in the art for a solution for fanout for those flip chip pads with dedicated test portion.

SUMMARY OF THE INVENTION

[0007] To solve the above and other potential problems in the prior art chip probe, embodiments of the present invention provide new solutions for fanout for pads of flip chips.

[0008] In a first aspect, there is provided a method for fanout for a pad of a flip chip. The method comprises: determining whether the pad comprises a test portion for electrical test; and responsive to determining that the pad comprises the test portion, generating an indication of the test portion in a profile associated with the pad, such that the test portion is excluded from being used in the fanout. Other embodiments in this aspect include a system and computer program product configured to carry out the method.

[0009] In a second aspect, there is provided an apparatus for fanout for a pad of a flip chip. The apparatus comprises: a pad determining unit configured to determine whether the pad comprises a test portion for electrical test; and an indication generating unit configured to generate, responsive to determining that the pad comprises the test portion, an indication of the test portion in a profile associated with the pad, such that the test portion is excluded from being used in the fanout. [0010] In a third aspect, there is provided a method for fanout for a pad of a flip chip. The method comprises: determining whether a profile associated with the pad contains an indication of a test portion on the pad; and responsive to determining that the profile contains the indication of the test portion, excluding the test portion from being used in the fanout. Other embodiments in this aspect include a system and computer program product configured to carry out the method.

[0011] In a fourth aspect, there is provided an apparatus for fanout for a pad of a flip chip. The apparatus comprises: a profile determining unit configured to determine whether a profile associated with the pad contains an indication of a test portion on the pad; and a fanout protecting unit configured to exclude, responsive to determining that the profile contains the indication of the test portion, the test portion from being used in the fanout.

[0012] As summarized above and detailed below, in accordance with embodiments of the present invention, the fanout may distinguish the test portion from any another portion on any pad of the flip chip. As a result, it is possible to avoid performing the fanout from the test portion where the probe marks might be left by the probe tips. In this way, reliability and accuracy of subsequent processes like bumping can be significantly improved. Other features and advantages of embodiments of the present invention will also be understood from the following description of specific exemplary embodiments when read in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments of the invention will be presented in the sense of examples and their advantages are explained in greater detail below, with reference to the accompanying drawings, wherein: [0014] FIG. 1 shows the schematic top view of a bump pad on a flip chip for which exemplary embodiments of the present invention may be implemented;

[0015] FIG. 2 shows a flowchart of a method for fanout for a bump pad on a flip chip in accordance with exemplary embodiments of the present invention;

[0016] FIG. 3 shows a schematic diagram of a profile associated with a bump pad in accordance with exemplary embodiments of the present invention;

[0017] FIG. 4 shows a block diagram of an apparatus for fanout for a bump pad on a flip chip in accordance with exemplary embodiments of the present invention;

[0018] FIG. 5 shows a flowchart of a method for fanout for a bump pad on a flip chip in accordance with exemplary embodiments of the present invention; [0019] FIG. 6 shows a top view of the bump pad on which the fanout has been performed in accordance with exemplary embodiments of the present invention;

[0020] FIG. 7 shows a block diagram of an apparatus for fanout for a bump pad on a flip chip in accordance with exemplary embodiments of the present invention; and

[0021] FIG. 8 shows a block diagram of a computing system that is suitable for implementing exemplary embodiments of the present invention.

[0022] Throughout the figures, same or similar reference numbers indicates same or similar elements.

DETAILED DESCRIPTION OF EMBODIMENTS [0023] As briefed above, in order to avoid probe marks left behind the probe tips on the bumping portion, there has been proposed to divide the bump pad into at least two separate portions where one portion is used for contact with the tips of the probe cards during the electrical test while the other portion is used for bumping without contact with the probe tips. In this way, the bumping portion on the bump pad may be free of probe marks, thereby avoiding those problems caused by the probe marks. It should be noted that although embodiments of the present invention will be described with reference to the bump pads, inventive idea of the present invention is applicable to any other kinds of pads on which the fanout may be performed.

[0024] As an example, FIG. 1 shows the top view of a pad such as a bump pad for use on flip chips. As shown, the bump pad 100 is divided into two portions, namely, a test portion 101 and a bumping portion 102. The test portion 101 is dedicated to the electrical test while the bumping portion 102 is only used for bumping and any other subsequent processes. During the test, no probe tip will touch the bumping portion 102. It should be noted that the example shown in FIG. 1 is only for the purpose of illustration. For example, in addition to the test portion and the bumping portion, the bump pad 100 may contain other portions for other processes.

[0025] By use of such bump pad, the bumping portion may be free of probe marks, thereby avoiding any problems caused by the probe marks. However, such bump pad cannot work well in connection with traditional fanout. Typically, the fanout considers the whole area of the bump pad as the bumping portion. As a result, the fanout is performed with respect to the center of the whole bump pad. That is, the routing trace is fanned out from/to the center of the bump pad. However, depending on different arrangement of the test and bumping portions, the center point of the bump pad is likely to be located in the test portion. In this event, the probe marks left on the test portion would probably affect the reliability and/or accuracy of the bumping process.

[0026] In order to address the above problem, embodiments of the present invention make use of the profile associated with the bump pad to realize the customized fanout. More specifically, reference is now made to FIG. 2, where the flowchart of a method 200 for fanout for a bump pad of a flip chip is shown. The method 200 may be carried out by the designer, manufacturer and/or provider of the bump pads/chips or any other appropriate entities.

[0027] At step S201, it is determined whether the bump pad comprises a test portion for electrical test. Such determination may be made, for example, base on a configuration file describing the characteristics of the bump pad. Such configuration file may be produced and provided by the designer, manufacturer, or provider of the bump pads. Alternatively or additionally, the user may explicitly indicate whether or not the bump pad to be processed contains a dedicated test portion.

[0028] If it is determined at step S201 that the bump pad does not comprise a test portion (i.e., the bump pad is a traditional bump pad, for example, of a standard octagon shape), then the profile associated with the bump pad may be generated as usual, which will not be detailed here. On the other hand, if it is determined at step S201 that the bump pad comprises a test portion, then at step S202, an indication of the test portion is generated in the profile associated with the bump pad, such that the test portion will excluded from being used in the subsequent fanout, as detailed below. As used herein, excluding the test portion means that the routing traces will not be fanned out from/to a point inside the test portion. However, the routing trace is allowed to pass through the test portion.

[0029] According to embodiments of the present invention, the profile associated with the bump pad may be a library exchange format (LEF) file. As known, a LEF file may contain library information for a class of designs. Library data may include layer, via, placement site type, macro cell definitions, and so forth. The LEF file may be an ASCII representation using the syntax conventions, for example. In such embodiments, the indication of the test portion may be implemented as a section of the LEF file. For example, FIG. 3 shows a schematic diagram of a portion of a LEF file 300. Within the LEF definition of the bump cell, the section 301 defines a standard octagon bump pad. Responsive to determining that the bump pad contains a test portion, the section 302 may be generated in the LEF file to indicate the test portion on the bump pad which is to be excluded from the fanout. Only for the purpose of illustration, the test portion is shown to be indicated by the "OBS" tag in FIG. 3.

[0030] It is also seen from FIG. 3 that in some embodiments, the indication of the test portion may comprise coordinates of vertices of the test portion, as shown in the section 302. It should be noted that this example is only for the purpose of illustration and the indication of the test portion can be implemented in many other possible ways. For example, as discussed above, the bump pad to be processed may be divided into the test portion and the bumping portion. In these embodiments, instead of or in addition to directly indicating the test portion to be blocked in the fanout, it is possible to indicate the bumping portion from which the fanout is to be performed. In other word, in the context of the present invention, the indication of the bumping portion is a kind of indication of the test portion. Like the test portion, the bumping portion may be represented by coordinates of the vertices thereof. Alternatively or additionally, in some embodiments, the indication in the profile may be even a point outside the test portion such that the traces may be routed from/to the indicated point in the fanout. Any other appropriate manners capable of indicating the test portion can be used in connection with embodiments of the present invention and the scope is not limited in this regard.

[0031] It should be noted that the profile associated with the bump pad is not limited to the LEF file. In some alternative embodiments, the profile may be a plaintext file, an Extensible Markup Language (XML) file, a database file, and so forth. The scope of the present invention is not limited in this regard. Accordingly, the test portion may be indicated in the profile depending on the form of the profile. For example, in some embodiments, the test portion may be defined in a separate file and the indication contained in the profile is a reference to that file.

[0032] Reference is now made to FIG. 4 where the diagram of an apparatus 400 for fanout for a bump pad of a flip chip is shown. Generally speaking, the apparatus may be configured to carry out the method 200 as describe above with reference to FIG. 2. Specifically, as shown in FIG. 4, the apparatus 400 comprises a bump pad determining unit 401 configured to determine whether the bump pad comprises a test portion for electrical test. The apparatus 400 further comprises an indication generating unit 402 configured to generate, responsive to determining that the bump pad comprises the test portion, an indication of the test portion in a profile associated with the bump pad, such that the test portion is excluded from being used in the fanout. As discussed above, in some embodiments, the profile may be a LEF file and the indication of the test portion may be generated as a section of the LEF file. Alternatively or additionally, the indication of the test portion may comprise coordinates of vertices of the test portion. In those embodiments where the bump pad comprises the test portion and a bumping portion, the indication generating unit may comprise a unit configured to generate an indication of the bumping portion.

[0033] Referring to FIG. 5, the flowchart of a method 500 of fanout for a pad of a flip chip is shown. The method 500 may be carried out by an electronic design automation (EDA) system or any other appropriate entities responsible for carrying out the fanout. At step S501, it is determined whether a profile associated with the bump pad contains an indication of a test portion on the bump pad. For example, in the embodiments where the profile is a LEF file associated with the bump pad as discussed above, it is possible to locate the section defining such test portion, for example, by searching for specific tags like "OBS" in the profile.

[0034] If it is determined at step S501 that there is no indication of a test portion in the profile, then the fanout may be performed as usual. For example, the routing traces may be fanned out from/to the center of the whole bump pad. On the other hand, if it is determined at step S501 that the profile contains the indication of a test portion, then at step S502, the indicated test portion is excluded from being used in the fanout. In other words, in accordance with embodiments of the present invention, the fanout may be performed on the portion other than the indicated test portion. As an example, the routing traces may be fanned out from/to a point outside the indicated test portion. [0035] Specifically, in those embodiments where the bump pad comprises the test portion and the bumping portion, as discussed above, the indication of the test portion contained in the profile may comprise coordinates of vertices of the test portion and/or the bumping portion. Accordingly, excluding the test portion at step S502 may comprise calculating a point inside the bumping portion based on the indication of the test portion, such that the fanout is performed with respect to the calculated point. The point may be the center point or any other suitable point located within the bumping portion.

[0036] FIG. 6 shows an example in this regard. Based on the indication of the test portion 101 and/or the bumping portion 102 in the profile, region of the bumping portion 102 may be determined. Then a point 601, which is the center point of the bumping portion in this case, may be calculated and the fanout may be carried out with respect to the calculated point 601. More specifically, as shown in the figure, a trace(s) 602 is fanned out from/to the calculated center 601. Since the fanout is not performed from the center of the whole bump pad 100, the test portion 101 is efficiently excluded from being used in the fanout. It should be noted that the point 601 is not necessarily the center point of the bumping portion, as discussed above.

[0037] Specifically, in accordance with embodiments of the present invention, since the originating point of the fanout can be determined as described above in the stage of backend design, the subsequent processes such as tapeout may employ traditional LEF file without the indication of the test portion. In this way, embodiments of the present invention may work well with any subsequent processes no matter currently known or developed in the future.

[0038] FIG. 7 shows a diagram of an apparatus 700 of fanout for a bump pad of a flip chip. Generally speaking, the apparatus may be configured to carry out the method 500 as describe above with reference to FIG. 5. Specifically, as shown in FIG. 7, the apparatus 700 comprises a profile determining unit 701 configured to determine whether a profile associated with the bump pad contains an indication of a test portion on the bump pad; and a fanout protecting unit configured to exclude, responsive to determining that the profile contains the indication of the test portion, the test portion from being used in the fanout. As discussed above, the profile may be a LEF file, and the indication of the region may a section of the LEF file. Additionally or alternatively, the indication of the test portion may comprise coordinates of vertices of the test portion. In those embodiments where the bump pad comprises the test portion and the bumping portion, the fanout protecting unit may comprise a calculating unit configured to calculate a point inside the bumping portion based on the indication of the test portion, such that the fanout is performed with respect to the calculated point.

[0039] FIG. 8 shows a computing system 800 suitable for implementing exemplary embodiments of the present invention. As shown, the computer system 800 comprises a central processing unit (CPU) 801 which is capable of performing various processes in accordance with a program stored in a read only memory (ROM) 802 or a program loaded from a storage section 808 to a random access memory (RAM) 803. In the RAM 803, data required when the CPU 801 performs the various processes or the like is also stored as required. The CPU 801 , the ROM 802 and the RAM 803 are connected to one another via a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.

[0040] The following components are connected to the I/O interface 805: an input section 806 including a keyboard, a mouse, or the like; an output section 807 including a display such as a cathode ray tube (CRT), a liquid crystal display (LCD), or the like, and a loudspeaker or the like; the storage section 808 including a hard disk or the like; and a communication section 809 including a network interface card such as a LAN card, a modem, or the like. The communication section 809 performs a communication process via the network such as the internet. A drive 810 is also connected to the I/O interface 805 as required. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like, is mounted on the drive 810 as required, so that a computer program read therefrom is installed into the storage section 808 as required.

[0041] Through the above descriptions, those skilled in the art would readily appreciate that in accordance with embodiments of the present invention, the fanout may distinguish the test portion from any another portion on a bump pad of flip chip. As a result, it is possible to avoid performing the fanout on the test portion where the probe marks might be left by the probe tips. Accordingly, reliability and accuracy of bumping process can be significantly improved.

[0042] For the purpose of illustrating spirit and principle of the present invention, some specific embodiments thereof have been described above. However, it is noted that the described embodiments in no sense limit the scope of the present invention. In general, the various exemplary embodiments may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto. While various aspects of the exemplary embodiments of this invention may be illustrated and described as block diagrams, flowcharts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

[0043] Specifically, various blocks shown in FIGs. 2 and 5 may be viewed as method steps, and/or as operations that result from operation of computer program code, and/or as a plurality of coupled logic circuit elements constructed to carry out the associated function(s). At least some aspects of the exemplary embodiments of the inventions may be practiced in various components such as integrated circuit chips and modules, and that the exemplary embodiments of this invention may be realized in an apparatus that is embodied as an integrated circuit, FPGA or ASIC that is configurable to operate in accordance with the exemplary embodiments of the present invention.

[0044] Furthermore, the method 200 or 500 may be embodied as a non-stationary computer readable medium tangibly encoding a computer program product which contains instructions, when executed by a processor, causing the processor to carry out the method steps. As another example, the present invention may be embodied as a system for fanout for a bump pad of a flip chip. The system at least comprises a processor and a memory operatively coupled to the processor and storing instructions for carrying out the method 200 or 500 when executed by the processor. [0045] While several specific implementation details are contained in the above discussions, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

[0046] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0047] Various modifications, adaptations to the foregoing exemplary embodiments of this invention may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings. Any and all modifications will still fall within the scope of the non-limiting and exemplary embodiments of this invention. Furthermore, other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these embodiments of the invention pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings.

[0048] Therefore, it is to be understood that the embodiments of the invention are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are used herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

WHAT IS CLAIMED IS:

1. A method for fanout for a bump pad of a flip chip, the method comprising: determining whether the bump pad comprises a test portion for electrical test; and responsive to determining that the bump pad comprises the test portion, generating an indication of the test portion in a profile associated with the bump pad, such that the test portion is excluded from being used in the fanout.

2. The method of Claim 1, wherein the profile is a library exchange format (LEF) file.

3. The method of Claim 1, wherein the indication of the test portion comprises coordinates of vertices of the test portion.

4. The method according to Claim 1, wherein the bump pad comprises the test portion and a bumping portion, and wherein generating the indication of the test portion comprises:

generating an indication of the bumping portion.

5. An apparatus for fanout for a bump pad of a flip chip, the apparatus comprising:

a bump pad determining unit configured to determine whether the bump pad comprises a test portion for electrical test; and

an indication generating unit configured to generate, responsive to determining that the bump pad comprises the test portion, an indication of the test portion in a profile associated with the bump pad, such that the test portion is excluded from being used in the fanout.

6. The apparatus of Claim 5, wherein the profile is a library exchange format (LEF) file.

7. The apparatus of Claim 5, wherein the indication of the test portion comprises coordinates of vertices of the test portion.

8. The apparatus according to Claim 5, wherein the bump pad comprises the test portion and a bumping portion, and wherein the indication generating unit comprises: a unit configured to generate an indication of the bumping portion.

9. A system for fanout for a bump pad of a flip chip, the system comprising: a processor; and

a memory operatively coupled to the processor and storing instructions for carrying out the method according to any of Claims 1-4 when executed by the processor.

10. A non-stationary computer readable medium tangibly encoding a computer program product which contains instructions, when executed by a processor, causing the processor to carry out steps of the method according to any of Claims 1-4.

11. A method for fanout for a bump pad of a flip chip, the method comprising: determining whether a profile associated with the bump pad contains an indication of a test portion on the bump pad; and

responsive to determining that the profile contains the indication of the test portion, excluding the test portion from being used in the fanout.

12. The method of Claim 11, wherein the profile is a library exchange format (LEF) file.

13. The method of Claim 11, wherein the indication of the test portion comprises coordinates of vertices of the test portion.

14. The method according to Claim 11, wherein the bump pad comprises the test portion and a bumping portion, and wherein excluding the test portion from being used in the fanout comprises:

calculating a point inside the bumping portion based on the indication of the test portion, such that the fanout is performed with respect to the calculated point.

15. An apparatus for fanout for a bump pad of a flip chip, the apparatus comprising:

a profile determining unit configured to determine whether a profile associated with the bump pad contains an indication of a test portion on the bump pad; and a fanout protecting unit configured to exclude, responsive to determining that the profile contains the indication of the test portion, the test portion from being used in the fanout.

16. The apparatus of Claim 15, wherein the profile is a library exchange format (LEF) file.

17. The apparatus of Claim 15, wherein the indication of the test portion comprises coordinates of vertices of the test portion.

18. The apparatus according to Claim 15, wherein the bump pad comprises the test portion and a bumping portion, and wherein the fanout protecting unit comprises: a calculating unit configured to calculate a point inside the bumping portion based on the indication of the test portion, such that the fanout is performed with respect to the calculated point.

19. A system for fanout for a bump pad of a flip chip, the system comprising: a processor; and

a memory operatively coupled to the processor and storing instructions for carrying out the method according to any of Claims 11-14 when executed by the processor.

20. A non-stationary computer readable medium tangibly encoding a computer program product which contains instructions, when executed by a processor, causing the processor to carry out steps of the method according to any of Claims 11-14.