JP2007129121A - Device for assembling and determining semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To properly conduct an assembly and a check in response to the heights of bonding wires when a package and a chip are connected by the bonding wires having the different heights. <P>SOLUTION: A semiconductor design supporter is constituted with a storage 7 for storing a chip data 21 and a package data 22, and an arithmetic processor 4 for determining whether the semiconductor chip 40 and the package are connected properly on the basis of the chip data 21 and the package data 22. The arithmetic processor 4 computes the lengths L1 to L3 of a plurality of the bonding wires B1 to B3, estimates the heights of a plurality of the bonding wires on the basis of the lengths L1 to L3, and sorts the bonding wires B1 and B3 having estimated heights in the same extent to the same group. The arithmetic processor 4 further determines whether the interval D1 of the bonding wires sorted in the same group are kept within the range of a predetermined value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an assembly determination apparatus that determines whether a semiconductor device including a semiconductor chip and a semiconductor package satisfies a design condition.

As a method for electrically connecting a semiconductor chip constituting an IC (Integrated Circuit) and a package substrate, a wire bonding method has been widely used. A semiconductor device manufactured by wire bonding is manufactured through various processes. In particular, when designing a package substrate on which a semiconductor chip is mounted, a confirmation process for confirming whether the semiconductor chip satisfies the design conditions and can be mounted on the package substrate is essential. In the confirmation process, a technique for automatically determining whether or not the design condition is satisfied is known (for example, see Patent Document 1).
The LSI design support system described in Patent Document 1 includes an LSI chip assembly determination device 101, a keyboard 102, a display 103, and an external storage device 107. The LSI chip assembly determination apparatus 101 is connected to the keyboard 102, the external storage device 107, and the display 103 via the interface unit 106. Further, the LSI chip assembly determination apparatus 101 outputs data such as an LSI chip, an LSI package, a wire, and an error stored in the storage unit 105 to the display 103 via the interface unit 106.

  The chip data input unit 132 registers LSI chip layout data including the chip outline and chip pad coordinates in the storage unit 105 via the interface unit 106. The LSI package input unit 133 is connected via the interface unit 106 to the internal lead shape of the LSI package data, the external pin number connected to the internal lead, the external pin number to be disconnected, and the wire bonder used in the actual assembly. The model and assembly conditions, the material and thickness of the wire used in assembly, and the material of the LSI package are registered in the storage unit 105. The assembly check unit 136 uses the wire position and LSI chip layout data registered in the storage unit 105 and the LSI package data registered by the LSI package input unit 133 to read the internal leads of the chip pad and the LSI package. When actually assembling with wire bonding, items such as whether the wires are short-circuited are checked.

  The initial wire generation unit 134 calculates the direction of the internal lead of the LSI package registered in the storage unit 105, and the wire connected to the chip pad registered in the closest storage unit 105 in that direction is stored in the storage unit 105. Is registered with. The wire adjustment unit 114 checks the wire registered in the storage unit 105 using the assembly check unit 136 by wire bonding. If an assembly error is found, an error is detected in the chip pad to which the wire is connected. The change to the chip pad in the direction to be eliminated is sequentially repeated to change the wire connected to the chip pad that can be assembled to the LSI package internal lead to be connected to all the chip pads registered in the storage unit 105. The result is registered in the storage unit 105.

  The data editing unit 115 selects the data and assembly data of all wires registered in the storage unit 105 in a data format suitable for the wire bonder model from the LSI chip, LSI package, and wire bonder model actually assembled in the storage unit 105. The drawing is automatically edited and data is output via the interface unit 106.

  In this LSI design support system, the assembly condition check of the chip pad and the internal lead combined by the initial wire generation unit 134 is performed using the assembly check unit 136, and if the assembly condition is not met, the combination of the chip pad and the internal lead is performed. Are automatically combined, and all the internal leads to be connected to the chip pads of the LSI package input by the LSI package data input unit 133 are combined with the chip pads that can be assembled.

  The operation of the LSI design support system will be described below with reference to the drawings. FIG. 2 is a flowchart showing the procedure of assembly check processing performed in the LSI design support system having the above-described configuration. As shown in FIG. 2, the conventional LSI design support system reads a data file for a chip name and a package name input from the keyboard. Then, a chip outline and a chip pad are generated from the chip size and chip pad coordinates obtained based on the read file. Similarly, a bonding lead is generated from bonding lead coordinates obtained based on the read file. At the same time, an assembly check rule value (for example, a wire interval of 100 μm) input from the keyboard is stored (step S101).

  Next, the generated chip pad and bonding lead are connected by a line segment in order from the chip corner portion, and the line segment is registered as a bonding wire (step S102). Next, a wire interval that is the shortest distance of the registered bonding wires is calculated, and it is compared whether or not the distance is larger than an assembly check rule value (step S103). Next, if the result is smaller than the assembly check rule, the result is registered as an error content (stitch S104). Finally, if there is an error, the error content is displayed on the display (step S105). In the technique described in Patent Document 1, it is automatically determined by this operation whether the semiconductor device conforms to the design conditions.

  Further, with the increase in the density of ICs accompanying the advancement of semiconductor technology, semiconductor chips having more electrode pads are manufactured, and the electrode pads are often arranged at a high density. As a method for suppressing short-circuiting of bonding wires when they are connected by bonding wires, a technique of arranging them in a staggered manner is known. (For example, refer to Patent Document 2). In the technique of Patent Document 2 (Japanese Patent Laid-Open No. 10-50750), a semiconductor chip mounted on a semiconductor device is arranged inside and outside electrode pads arranged outside as viewed from the center of the semiconductor chip. And an inner electrode pad. In addition, the IC package includes an outer lead electrode disposed on the outer side as viewed from the center of the island and an inner lead electrode disposed on the inner side.

  In the technique described in Patent Document 2, the semiconductor chip and the IC package are connected by wire bonding. A wire used for wire bonding (hereinafter referred to as a bonding wire) is formed in an arch shape having a height in the vertical direction when a semiconductor chip is horizontally arranged. As shown in Patent Document 2, in a conventional semiconductor device, an inner electrode pad and an outer lead electrode are connected, and an outer electrode pad and an inner lead electrode are connected.

  As described above, the bonding wire is formed in an arch shape having a height in the vertical direction. In the technique described in Patent Document 2, the height of the bonding wire when the inner electrode pad and the outer lead electrode are connected is higher than that when the outer electrode pad and the inner lead electrode are connected. By increasing the height, a short circuit between adjacent bonding wires is suppressed.

Japanese Patent No. 2707789 Japanese Patent Laid-Open No. 10-50750

  The technique disclosed in Patent Document 1 inspects the shortest interval between adjacent bonding wires when the bonding wire interval is inspected. However, it is possible to prevent a short circuit between the adjacent bonding wires and the adjacent bonding wires by changing the heights of the adjacent bonding wires and the wires as in Patent Document 2. In such a case, it is necessary to check whether or not there is a possibility that a short circuit between adjacent wires having the same height as the bonding wire may occur rather than a short circuit between adjacent adjacent bonding wires. is there.

  The problem to be solved by the present invention is that in a semiconductor device in which a semiconductor chip and an IC package are connected by wire bonding, the bonding wires used for the connection are composed of a plurality of bonding wires having different heights. Another object of the present invention is to provide an assembly inspection apparatus that can appropriately perform assembly inspection according to the height of the wire.

  The means for solving the problem will be described below using the numbers used in [Best Mode for Carrying Out the Invention]. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

  In order to solve the above problem, a storage unit (7) that stores chip data (21) that is information about the semiconductor chip (40) and package data (22) that is information about a package on which the semiconductor chip (40) is mounted. And an arithmetic processing unit (4) for determining whether the semiconductor chip (40) and the package are properly connected based on the chip data (21) and the package data (22) A semiconductor design support apparatus is provided.

  Here, the arithmetic processing unit (4) generates a pad data generation unit (32) that generates pad data having information on the arrangement positions of the plurality of electrode pads (41 to 43) arranged on the semiconductor chip (40). A lead electrode data generation unit (33) for generating lead electrode data having information on the arrangement positions of the plurality of lead electrodes (51 to 53) arranged in the package, and the pad data and the lead electrode data. Based on this, generation of bonding wire data having information on a plurality of bonding wires (B1 to B3) for connecting the plurality of electrode pads (41 to 43) and the plurality of lead electrodes (51 to 53) in a one-to-one relationship. When the bonding wire data generation unit (34) and the plurality of bonding wires (B1 to B3) are actually formed A wire identification unit (35) that classifies the plurality of bonding wires (B1 to B3) into a group corresponding to the height, and a determination execution unit (36) that performs the determination. It is out.

  And the said wire identification part (35) calculates the length (L1-L3) of these bonding wires (B1-B3) based on the said bonding wire data, and makes it into the said length (L1-L3) Based on this, the height is estimated, and the bonding wires (B1, B3) whose estimated height falls within a predetermined range are classified into the same group. In addition, the determination execution unit (36) determines whether the interval (D1) of the bonding wires classified into the same group is within a predetermined value range, It is determined whether or not the bonding wire is properly formed.

  In a semiconductor device formed by wire bonding, a bonding wire may be deformed due to the influence of resin injected when a package is sealed. At the stage of assembly inspection, it is inspected whether or not the adjacent wires have an interval that does not short-circuit due to deformation of the wires. When the semiconductor chip and the package are connected by bonding wires having different heights, there is a possibility that wires having the same height are short-circuited rather than wires having different heights. As described above, in the inspection stage, bonding wires having the same height are classified into the same group, and assembly inspection within the same group is performed, so that a more accurate inspection result is performed.

  As described above, the conventional LSI design support system calculates the shortest interval between adjacent bonding wires without considering the loop height of the bonding wires when checking the wire interval. For this reason, in the conventional LSI design support system, the interval between bonding wires having the same loop height is not checked, and it may be difficult to obtain an appropriate assembly check result.

  According to the present invention, when a bonding wire of a semiconductor device in which a semiconductor chip and an IC package are connected by wire bonding is composed of a plurality of bonding wires having different heights, the assembly is appropriately performed according to the height of the wire. Inspection can be performed.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. FIG. 3 is a block diagram illustrating the configuration of the semiconductor design support apparatus 10 of this embodiment. The semiconductor design support system 10 of this embodiment includes an information processing device 1, an input device 2, and an output device 3. Referring to FIG. 3, the information processing apparatus 1 includes a CPU (Central Processing Unit) 4, a memory 5, an input / output interface 6, and a mass storage device 7, which are buses. 8 is connected. The mass storage device 7 includes a data storage unit 11 and a program storage unit 12.

  The information processing apparatus 1 is a high-speed arithmetic processing apparatus typified by a personal computer or a workstation. The input device 2 is a man-machine interface having a function of inputting data to the information processing device 1, and representative examples thereof include a keyboard and a mouse. In the following embodiment, the case where the input device 2 is a keyboard will be described as an example. The output device 3 is a man-machine interface having a function of outputting the processing result of the information processing device 1 to the outside. For example, a CRT or a liquid crystal display is representative. In the following embodiment, the case where the output device 3 is a display device will be exemplified, and description will be made assuming that the chip shape, package shape, assembly determination result, and the like are visually displayed.

  The CPU 4 is an arithmetic processing device that controls various devices provided in the semiconductor design support system 10 and processes data input to and output from the information processing device 1. The CPU 4 interprets data received from the input device 2 and performs arithmetic operations. Then, the calculation result is output by the output device 3 or the like. The memory 5 is a storage medium on which data can be written and read, and examples thereof include SDRAM and DDR-SDRAM. The input / output interface 6 is a device that controls data communication executed between the information processing device 1 and the input device 2 or the output device 3 described above. The large-capacity storage device 7 is a device used for recording a large amount of data on a storage medium. For example, an HDD (Hard Disk Drive) is exemplified as a representative example. As shown in FIG. 3, the mass storage device 7 includes a data storage unit 11 and a program storage unit 12.

  The data storage unit 11 indicates a storage area for storing data related to the present embodiment among various data held by the mass storage device 7. Similarly, the program storage unit 12 indicates a storage area for storing a computer program related to the operation of the present embodiment among various data held by the mass storage device 7. Hereinafter, detailed configurations of the data storage unit 11 and the program storage unit 12 will be described with reference to the drawings.

  FIG. 4 is a block diagram illustrating the configuration of the data storage unit 11. Referring to FIG. 4, the data storage unit 11 holds LSI chip data 21 and LSI package data 22.

  The LSI chip data 21 is a description file in which information related to a semiconductor chip, such as chip size and chip pad coordinates, is described in HDL (hardware description language) such as VHDL. The LSI package data 22 is a description file in which information on the bonding position of the bonding lead and the shape of the bonding lead is described in HDL (hardware description language) such as VHDL. The LSI chip data 21 and the LSI package data 22 are read out by an assembly inspection program when the assembly inspection is executed.

  FIG. 5 is a block diagram illustrating the configuration of the program storage unit 12. Referring to FIG. 5, the program storage unit 12 includes an inspection control program 30, a design condition input function unit 31, a chip input function unit 32, a package input function unit 33, a wire generation function unit 34, and a wire identification function. A unit 35, an assembly check function unit 36, and a screen display function unit 37 are provided.

  The design condition input function unit 31 provides a function of registering the chip name, package name, assembly check rule value, and the like input via the input device 2 in the memory 5.

  The chip input function unit 32 provides a function of referring to the chip name registered by the function of the design condition input function unit 31 and reading the LSI chip data 21 of the semiconductor chip corresponding to the chip name from the mass storage device 7. ing. The chip input function unit 32 provides a function of storing data on the chip shape, electrode pad shape, and electrode pad coordinates in the memory 5.

  The package input function unit 33 provides a function of referring to the package name registered by the function of the design condition input function unit 31 and reading the LSI package data 22 of the package name IC package from the mass storage device 7. The package input function unit 33 also provides a function of storing in the memory 5 data on the bonding lead shape and the coordinates of the point to which the bonding wire is connected (hereinafter referred to as bonding lead coordinates).

  The wire generation function unit 34 provides a function of generating data on bonding wires (hereinafter referred to as bonding wire shape data) for connecting electrode pads and bonding leads. The bonding wire shape data is generated based on the electrode pad coordinate data stored in the memory 5 and the bonding lead coordinate data stored in the memory 5. Here, it is preferable that the function provided by the wire generation function unit 34 is to generate bonding wire shape data by connecting in order from the chip corner, and the wire generation function unit 34 generates the generated bonding. A function of storing wire shape data in the memory 5 is provided.

  The wire identification function unit 35 provides a function of calculating difference between adjacent wire lengths based on bonding wire shape data stored in the memory 5 and generating difference data. Further, the wire identification function unit 35 has a function of calculating an average value of each difference based on the difference data, and a height when each wire is wired to an actual device based on the difference data and the average value (hereinafter, Data indicating the group to which the classified bonding wire belongs (hereinafter referred to as a wire attribute), and the bonding wires are classified into groups corresponding to the loop height of each wire. (Referred to as data) is stored in the mass storage device 7.

  In the embodiment described below, a case where bonding wires are classified into two groups, a high loop group with a high loop height and a low loop group with a low loop height, will be described as an example. Also, wire attribute data of bonding wires classified into the high loop group is referred to as high loop attribute data, and wire attribute data of bonding wires classified into the low loop group is referred to as low loop attribute data.

  By the function provided by the wire identification function unit 35, the difference between the wire lengths of adjacent bonding wires and the average value of the differences are calculated. Further, the bonding wires having the maximum wire length are classified into a high loop group. If the difference between the wire length of the wire arranged next to the bonding wire (hereinafter referred to as the adjacent wire) and the maximum wire length is smaller than the threshold value obtained based on the average value, the adjacent wire is changed to the previous wire. Classify into a group (high loop group) with the same attributes as (bonding wire with maximum wire length).

  When the difference is larger than the threshold value, the adjacent wires are classified into a group (low loop group) having an attribute different from that of the previous wire (the bonding wire having the maximum wire length). The semiconductor design support system 10 of the present embodiment repeats this operation, classifies each bonding wire into two types, a high loop group and a low loop group, and stores them in the memory 5.

  The assembly check function unit 36 extracts adjacent wires by bonding wires classified into the same group based on the wire attribute data stored in the memory 5, and the interval between them is registered by the design condition input function unit 31. Provides a function to evaluate whether the assembly check rule value is met. The assembly check function unit 36 provides a function of generating a message including the error content and storing it in the memory 5 when adjacent wires do not conform to the assembly check rule value.

  The screen display function unit 37 provides a function of displaying on the display the chip shape data, package shape data, bonding wire shape data, and a message including error contents stored in the memory 5.

  The operation of the semiconductor design support system 10 of this embodiment will be described below with reference to the drawings. FIG. 6 is a flowchart illustrating the operation of the semiconductor design support system 10 of this embodiment. Referring to FIG. 6, the operation of the assembly check process according to the present embodiment starts when the inspection control program 30 is activated in response to an activation instruction for the assembly inspection control program. In step S01, the information processing apparatus 1 starts the inspection control program 30 in response to the input start command. The inspection control program 30 requests input of the name of the semiconductor chip and the name of the IC package. At this time, in order to specify the semiconductor device to be inspected in the assembly inspection, the user transmits the name of the semiconductor chip constituting the inspection target semiconductor device and the name of the IC package via the input device 2 in response to the request. Enter.

  At this time, an input of an assembly check rule value used as an inspection standard is requested based on an operation procedure provided by the design condition input function unit 31. In response to the request, the user inputs an assembly check rule value (for example, a wire interval of 100 μm). Further, the inspection control program 30 requests input of boundary values for classifying bonding wires into groups. In response to the request, the user enters a boundary value (eg, 200 um). The assembly check rule value and the boundary value are determined based on design conditions. Accordingly, a configuration may be adopted in which these data are automatically generated from design condition data indicating design conditions. The inspection control program 30 stores each input data in the memory 5.

  In step S02, the assembly inspection program reads the LSI chip data 21 based on the name of the semiconductor chip input in step S01 and the operation procedure provided by the chip input function unit 32. The information processing apparatus 1 determines the chip shape and the electrode pad shape and position based on the chip size data and chip pad coordinate data obtained from the LSI chip data 21, and generates a semiconductor chip on the computer. In step S02, the inspection control program 30 reads the LSI package data 22 based on the name of the IC package input in step S01 and the operation procedure provided by the package input function unit 33. The information processing apparatus 1 generates a bonding lead on the computer based on the bonding lead coordinate data obtained from the read LSI package data 22.

  In step S03, the inspection control program 30 connects the electrode pads and bonding leads of the generated semiconductor chip with line segments based on the operation procedure provided by the wire generation function unit 34, and data indicating the line segments (hereinafter referred to as the line segments). , Referred to as bonding wire data) is stored in the memory 5 as a bonding wire on the computer. At this time, it is preferable that the operation of connecting with the line segments is performed with the line segments in the counterclockwise order from the semiconductor chip corner portion.

  In step S04, the inspection control program 30 calculates the difference in length between adjacent bonding wires based on the procedure provided by the wire identification function unit 35, and generates difference data. The inspection control program 30 extracts data indicating the length of the line segment from the line segment data stored in the memory 5 as a bonding wire on the computer, and the length of adjacent bonding wires based on the extracted data. The difference in height is calculated. Specifically, an arbitrary bonding wire is specified as the first wire, and the length thereof is set as the first length L1. Next, the bonding wire arranged next to the first wire is specified as the second wire, and the length thereof is set as the second length L2.

Assuming that the difference between the first length L1 and the second length L2 is the first difference R1, the first difference R1 is expressed by the following equation (1): first difference R1 = | first length L1−second length L2 | (1)
More demanded.

Similarly, a bonding wire that is arranged next to the second wire and has not yet obtained a difference from the second wire is specified as a third wire, and the length thereof is defined as a third length L3. At this time, if the difference between the second length L2 and the third length L3 is the second difference R2, the second difference R2 is expressed by the following equation (2). Second difference R2 = | second length L2−third length Length L3 | (2)
More demanded.

Thereafter, the same operation is repeated from the first wire to the n-th wire.

The difference between the (n-1) th length Ln-1 and the nth length Ln is the n-1th difference R-1, and the difference between the nth length Ln and the first length L1 is the nth difference Rn. , Each difference is
N−1th difference Rn−1 = | n−1 length Ln−1−nth length Ln |
Nth difference Rn = | nth length Ln−first length L1 |
More demanded.

  When the calculation of the difference is completed for all of the adjacent bonding wire groups, the process proceeds to step S05.

  In step S05, the inspection control program 30 calculates the sum of the calculated wire length differences (first difference R1 to nth difference Rn), and calculates the average value of the differences based on the total. The information processing apparatus 1 stores the calculated average value data in the memory 5, and the process proceeds to step S06.

  In step S06, the bonding wire shape data having the longest length is extracted from the bonding wire shape data stored in the memory 5 based on the procedure indicated by the wire identification function unit 35. Here, when the wire corresponding to the bonding wire shape data is actually stretched (when connecting the electrode pad and the lead electrode), the bonding wire having the longest length is formed so as to have a high loop height. Therefore, the inspection control program 30 classifies the corresponding bonding wires into the high loop group based on the extracted bonding wire shape data.

  In step S07, bonding wire shape data corresponding to a bonding wire (hereinafter referred to as an adjacent wire) that is arranged next to a bonding wire (hereinafter referred to as a previous wire) that has been classified and that has not yet been classified is obtained. Extracting and calculating the difference in length from the bonding wire specified in the previous step.

  In step S08, the average value of the differences in wire length calculated in step S05 and stored in the memory 5 and the boundary value stored in step S01 are read, and based on these values, a threshold value for specifying the group to which each bonding wire belongs To decide. The inspection control program 30 compares whether or not the difference between the lengths of adjacent wires obtained in step S07 exceeds the threshold value. As a result of the comparison, if the threshold value is not exceeded, the process proceeds to step S09. If the threshold value is exceeded, the process proceeds to step S10.

  Adjacent wire sets include a wire set with a high loop height and a wire set with a low loop height, a set of wires with a high loop height, and a set of wires with a low loop height. Therefore, the threshold value used for the determination in step S08 is a value smaller than the smallest wire length difference among a plurality of pairs of wires having a high loop height and wires having a low loop height, and wires having a high loop height. Of these, and a plurality of pairs of wires having a low loop height, a value larger than the largest wire length difference is preferable.

  Therefore, for example, when the boundary value is set to 200 um in step S01, when the difference (um) in the wire length calculated in step S07 is smaller than the average value (um) −200 um, the same loop height as that of the previous wire is set. Determine. If the difference in wire length calculated in step S07 exceeds the average value +200 μm, it is determined that the loop height is different from the previous wire. In step S01 described above, by adjusting the value set as the boundary value, it is possible to execute threshold setting suitable for the semiconductor device to be designed.

  In step S09, because the threshold value has not been exceeded, the adjacent wires are classified into the same group as the previous wire, and the corresponding wire attribute data is updated. For example, if the process proceeds to step S09 as a result of comparing the difference between the previous wire classified into the high loop group, its adjacent wire, and the above threshold value, the adjacent wire is classified into the high loop group, Loop attribute data is updated.

  In step S10, because the threshold value has not been exceeded, the adjacent wires are classified into a group different from the previous wire, and the corresponding wire attribute data is updated. For example, when the process proceeds to step S10 as a result of comparing the difference between the previous wire classified into the high loop group and its adjacent wires and the above-described threshold value, the adjacent wire is classified into the low loop group and low. Loop attribute data is updated.

  In step S11, in response to completion of adjacent wire classification, a determination is made as to whether or not all wires have been classified. As described above, the bonding wires are classified in order from the bonding wire having the maximum wire length. If it is determined that the classification of all the wires has not been completed, the process returns, and the process of step S07 is executed with the adjacent wire as a new previous wire. When the classification of all the wires is completed, the process proceeds to step S12.

  In step S12, the inspection control program 30 executes assembly inspection based on the procedure shown in the procedure provided by the assembly check function unit 36. The inspection control program 30 identifies bonding wires belonging to the same group as belonging wires based on the high loop attribute data (or low loop attribute data). Neighboring wires are extracted from the same wire and assembly inspection is executed. For example, when the wire interval is set as the assembly check rule value, the shortest distance between wires of the same loop height is calculated based on the high loop attribute data (or low loop attribute data) and the bonding wire shape data Then, it is compared whether or not the distance is larger than the assembly check rule value. As a result of the comparison, if the distance is larger than the assembly check rule value, the process proceeds to step S14. If the distance is smaller than the assembly check rule value, the process proceeds to step S13.

  If it is smaller than the assembly check rule in step S13, the result is regarded as an error. The inspection control program 30 generates a message including the error content and stores it in the memory 5, and the process proceeds to step S14.

  In step S <b> 14, the inspection control program 30 displays the result of the assembly inspection on the output device 3 based on the function provided by the screen display function unit 37. At this time, if a message including the error content in step S13 is stored in the memory 5, the error content included in the message is displayed on the output device 3 as an assembly inspection result. Further, a design change is performed based on the error contents, and after the assembly inspection of the semiconductor device after the design change is executed, the semiconductor device is manufactured.

  When bonding wires having the same loop height are adjacent to each other, the wire lengths are almost equal. In the present embodiment, it is determined that the loop height is different when the difference between adjacent wire lengths exceeds a certain value due to the configuration and operation described above. Also, the bonding wire with the maximum wire length always has a high loop. Therefore, the loop height is repeatedly determined counterclockwise from the bonding wire as a base point, and then an assembly check is performed in consideration of the loop height.

  As a result, in the present invention, it is possible to execute an assembly check on the LSI package having the staggered bonding leads by distinguishing the bonding wire loop height. By designing a semiconductor device corresponding to this assembly inspection, a failure in which bonding wires are short-circuited can be prevented, and the design time can be shortened.

  Hereinafter, the operation of the present embodiment described above will be described visually with reference to plan views. FIG. 7 is a plan view illustrating the configuration of the semiconductor device on the computer generated by the operation of the assembly inspection apparatus of this embodiment. Here, FIG. 7A illustrates the configuration of the semiconductor device according to the present embodiment. FIG. 7B shows an assembly inspection operation executed by a conventional LSI design support system in order to facilitate understanding of the present invention. Referring to (a) of FIG. 7, the semiconductor chip 40 is a semiconductor chip when the output device 3 displays the shape of the semiconductor chip to be inspected from the chip shape data generated based on the LSI chip data 21. It is a part. Similarly, the first electrode pad 41 to the third electrode pad 43 and the first bonding lead 51 to the third bonding lead 53 have respective external shapes when the electrode pad and the bonding lead on the computer are displayed on the output device 3. Illustrated. As shown in FIG. 7, each electrode pad (41-43) has connection points (P41-P43) to which bonding wires are connected. Similarly, each bonding lead has connection points (P51 to P53) to which bonding wires are connected.

Based on the LSI chip data 21, the coordinates of the bonding wire connection point (for example, the first pad-side connection point P41) are obtained. Also, based on the LSI package data 22, the coordinates of the bonding lead connection point (for example, the first lead-side connection point P51) are obtained. As described in the description of the operation in step S03 shown in the above flowchart, the bonding wire data obtained by connecting the first pad side connection point P41 and the first lead side connection point P51 with a line segment is used as a bonding wire on the computer. Store in the memory 5. Similarly, bonding wires are generated and stored in the memory 5 in the order of the second pad side connection point P42 and the second lead side connection point P52, the third pad side connection point P43 and the third lead side connection point P53.・
In step S04, the length difference between adjacent bonding wires is calculated. As shown in FIG. 7A, the first bonding wire B1 has a length L1, and the second bonding wire B2 has a length L2. Therefore, the length difference (first difference R1) between the first bonding wire B1 and the second bonding wire B2 is obtained from the above equation (1). Similarly, the second difference R2 to the nth difference Rn are obtained.

  Thereafter, calculation of an average value, extraction of the bonding wire with the longest length, and operations for classifying the bonding wire into a high loop group are executed (step 05 and step 06). Here, the case where the longest bonding wire extracted in step S06 is the second bonding wire B2 shown in FIG. 7A will be described as an example.

  In step 07, the third bonding wire B3 is extracted as an adjacent wire of the second bonding wire B2, and the difference between the second bonding wire B2 and the third bonding wire B3 is calculated. In step S08, the calculated difference is compared with a threshold value, and the third bonding wire B3 is classified. Here, it is assumed that the classification of all the bonding wires is completed, and in this case, the third bonding wire B3 is classified into the low loop group, and further, the first bonding wire B1 is also classified into the low loop group. Thereafter, processing following step 09 is executed, and assembly inspection is performed in step S12. At this time, the first bonding wire B1 and the third bonding wire B3 are classified into the same group, and the second bonding wire B2 is classified into a different group. Therefore, the inspection control program 30 performs assembly inspection on the first bonding wire B1, the third bonding wire B3, and the interval D1 based on the procedure shown in the procedure provided by the assembly check function unit 36.

  As shown in FIG. 7 (b), the assembly inspection is based on whether or not the distance (d1, d2) between the bonding wires conventionally arranged at different loop heights conforms to the assembly check rule value. Was running. In the assembly inspection apparatus of this embodiment, bonding wires arranged at the same loop height are grouped by the above-described configuration and operation, and assembly inspection is performed for each group. As a result, a failure in which the bonding wires are short-circuited is prevented, and the design time can be shortened.

  In the above-described embodiment, the case where there are two types of bonding wire heights has been described as an example, but this does not limit the number of classifications in the present invention. In the above-described embodiment, the bonding wire interval is cited as an assembly check item. However, the wire length or the wire incident angle may be used as long as the rule value varies depending on the loop height. In the above-described embodiment, the information processing apparatus 1 constituting the semiconductor design support system 10 operates in accordance with the procedure shown in the computer program held in the program storage unit 12 to perform assembly inspection. Running. Here, it is also possible to configure a circuit that operates in the same procedure as that shown in the computer program and execute the assembly inspection described in the present embodiment.

FIG. 1 is a block diagram showing a configuration of a conventional LSI design support system. FIG. 2 is a flowchart showing the operation of the conventional LSI design support system. FIG. 3 is a block diagram illustrating the configuration of the semiconductor design support system 10 of the present invention. FIG. 4 is a block diagram illustrating the configuration of the data storage unit. FIG. 5 is a block diagram illustrating the configuration of the program storage unit. FIG. 6 is a flowchart illustrating the operation of the semiconductor design support system 10 of the present invention. FIG. 7 is a plan view showing the operation of the semiconductor design support system 10 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor design support system 1 ... Information processing apparatus 2 ... Input device 3 ... Display apparatus 4 ... CPU
5 ... Memory 6 ... I / O interface 7 ... Mass storage device 8 ... Bus 11 ... Data storage unit 12 ... Program storage unit 21 ... LSI chip data 22 ... LSI package data 30 ... Inspection control program 31 ... Design condition input function unit 32 ... chip input function part 33 ... package input function part 34 ... wire generation function part 35 ... wire identification function part 36 ... assembly check function part 37 ... screen display function part 40 ... semiconductor chips 41 to 43 ... electrode pads 51 to 53 ... bonding Leads P41 to P43 ... Wire connection points P51 to P53 ... Wire connection points B1 to B3 ... Bonding wire 101 ... LSI chip assembly determination device 102 ... Keyboard 103 ... Display 105 ... Storage unit 106 ... Interface unit 107 ... External storage device 132 ... Chip Data input unit 133... LSI chip Cage input unit 134 ... initial wire generator 114 ... wire adjusting unit 115 ... data editing unit 136 ... assembly check section

Claims (16)

A storage unit that stores chip data that is information about a semiconductor chip and package data that is information about a package on which the semiconductor chip is mounted;
An arithmetic processing unit that determines whether or not the connection between the semiconductor chip and the package is appropriately performed based on the chip data and the package data;
The arithmetic processing unit includes:
A pad data generation unit that generates pad data having information related to an arrangement position of a plurality of electrode pads arranged on the semiconductor chip;
A lead electrode data generation unit for generating lead electrode data having information on the arrangement positions of a plurality of lead electrodes arranged in the package;
Based on the pad data and the lead electrode data, a bonding wire data generating unit that generates bonding wire data having information on a plurality of bonding wires connecting the plurality of electrode pads and the plurality of lead electrodes;
A wire identifying unit that estimates a height at which the plurality of bonding wires are actually formed, and classifies the plurality of bonding wires into a group corresponding to the height;
A determination execution unit that executes the determination,
The wire identification unit is
Based on the bonding wire data, calculate the length of the plurality of bonding wires, estimate the height based on the length,
Classifying bonding wires whose estimated height is within a predetermined range into the same group;
The determination execution unit
It is determined whether or not the bonding wires are properly formed by determining whether or not the interval between the bonding wires classified into the same group is within a predetermined value range. Semiconductor design support equipment. The semiconductor design support apparatus according to claim 1,
The wire identification unit is
The difference between the lengths of adjacent bonding wires is calculated, and when the difference is smaller than a predetermined threshold, it is estimated that the adjacent bonding wires are formed at the same height, and the adjacent bonding wires are the same. Semiconductor design support equipment classified into groups. The semiconductor design support apparatus according to claim 2,
The wire identification unit is
Identifying one of the plurality of bonding wires as a first wire and classifying the first wire into one group;
When the difference between the first wire and the second wire adjacent to the first wire is smaller than the threshold value, the second wire is classified into the same group as the first wire, and the second wire is newly set. Identified as the first wire
When the difference between the first wire and the second wire is greater than the threshold value, the second wire is classified into another group different from the first wire, and the second wire is replaced with a new first wire. Identify semiconductor design support equipment. In the semiconductor design support device according to claim 3,
The wire identification unit is
Based on the bonding wire data,
The semiconductor design support device that identifies the bonding wire having the longest length as the first wire from among the plurality of bonding wires. The semiconductor design support apparatus according to claim 4,
Each of the plurality of bonding wires has a height,
The group is
A high loop group showing a set of bonding wires having a high height;
A low loop group indicating a set of bonding wires having a low height,
The wire identification unit is
Identifying one of the plurality of bonding wires as a first wire and classifying the first wire into the high loop group;
When the difference between the first wire and the second wire adjacent to the first wire is smaller than the threshold value, the second wire is classified into the high loop group and the second wire is replaced with a new first wire. Identified as a wire,
When the difference between the first wire and the second wire is greater than the threshold, classify the second wire into the low loop group and identify the second wire as a new first wire;
When the second wire is classified into the low loop group,
When the difference between the new first wire and the new second wire adjacent to the new first wire is greater than the threshold, classifying the new second wire into the high loop group and A semiconductor design support apparatus that identifies a new second wire as a new first wire. The semiconductor design support apparatus according to claim 5,
The wire identification unit is
The distance between the position coordinates of the electrode pad obtained based on the pad position data and the position coordinates of the connection point obtained based on the lead electrode data is the length, and the difference in length is calculated as difference data. Semiconductor design support device. The semiconductor design support apparatus according to claim 6,
The wire identification unit is
Based on the difference data, generate difference average value data that is an average value of the differences,
A value for estimating the adjacent bonding wires whose difference is smaller than the average value as wires formed at different heights, or the adjacent bonding wires whose difference is larger than the average value are the same. A semiconductor design support apparatus that determines the threshold value by correcting the difference average value data using a value for estimating a wire when formed at a height. A storage unit that stores chip data that is information about a semiconductor chip and package data that is information about a package on which the semiconductor chip is mounted;
A computer-executable program comprising: an arithmetic processing unit that determines whether or not the connection between the semiconductor chip and the package is appropriately performed;
The program is
(A) generating pad position data having information on arrangement positions of a plurality of electrode pads arranged on the semiconductor chip based on the chip data;
(B) generating lead electrode data having information on connection points when a plurality of lead electrodes arranged in the package are connected to a plurality of bonding wires based on the package data;
(C) generating bonding wire data based on the pad position data and the lead electrode data;
(D) classifying the plurality of bonding wires into groups;
(E) performing the determination based on the chip data and the package data;
The step (d) includes:
Calculating a difference in length between adjacent bonding wires of the plurality of bonding wires;
Classifying the adjacent bonding wires into the same group when the difference is less than a predetermined threshold;
The step (e) includes:
It is determined whether or not the bonding wires are properly formed by determining whether or not the interval between the bonding wires classified into the same group is within a predetermined value range. A program capable of executing a method comprising steps by a computer. The program according to claim 8, wherein
The step (d) includes:
Identifying one of the plurality of bonding wires as a first wire and classifying the first wire into one group;
When the difference between the first wire and the second wire adjacent to the first wire is smaller than the threshold value, the second wire is classified into the same group as the first wire, and the second wire is newly set. Identifying the first wire as
When the difference between the first wire and the second wire is greater than the threshold value, the second wire is classified into another group different from the first wire, and the second wire is replaced with a new first wire. A program executable by a computer comprising a step of identifying as The program according to claim 9,
The step (d) includes:
Based on the bonding wire data,
A computer-executable program that includes the step of: specifying the longest bonding wire as the first wire from among the plurality of bonding wires. The program according to claim 10, wherein
The step (d) includes:
Identifying one of the plurality of bonding wires as a first wire;
Classifying the first wire into a high loop group representing a set of high bonding wires;
When the difference between the first wire and the second wire adjacent to the first wire is smaller than the threshold value, the second wire is classified into the high loop group and the second wire is replaced with a new first wire. Identifying as a wire;
When the difference between the first wire and the second wire is greater than the threshold value, the second wire is classified into a low loop group indicating a set of bonding wires having a low height, and the second wire is Identifying as a new first wire;
When the second wire is classified into the low loop group and the difference between the new first wire and the new second wire adjacent to the new first wire is greater than the threshold, the new wire A computer-executable program comprising: classifying a second wire into the high loop group and identifying the new second wire as a new first wire. The program according to claim 11,
The step (d) includes:
The distance between the position coordinates of the electrode pad obtained based on the pad position data and the position coordinates of the connection point obtained based on the lead electrode data is the length, and the difference in length is calculated as difference data. A program that can be executed by a computer. The program according to claim 12,
The step (d) includes:
Generating difference average value data that is an average value of the differences based on the difference data; and
A value for estimating the adjacent bonding wires whose difference is smaller than the average value as wires formed at different heights, or the adjacent bonding wires whose difference is larger than the average value are the same. A program capable of executing a method including a step of correcting the difference average value data using a value for estimating a wire when formed at a height to determine the threshold. (A) reading out chip data that is information relating to the semiconductor chip from the storage unit, and generating pad position data having information on arrangement positions of a plurality of electrode pads arranged on the semiconductor chip based on the chip data; ,
(B) When package data, which is information relating to a package on which the semiconductor chip is mounted, is read from the storage unit, and a plurality of lead electrodes arranged in the package are connected to a plurality of bonding wires based on the package data Generating lead electrode data having information on the connection points of
(C) generating bonding wire data based on the pad position data and the lead electrode data;
(D) classifying the plurality of bonding wires into groups;
(E) performing the determination based on the chip data and the package data,
The step (d) includes:
Calculating a difference in length between adjacent bonding wires of the plurality of bonding wires;
Classifying the adjacent bonding wires into the same group when the difference is less than a predetermined threshold;
The step (e) includes:
It is determined whether or not the bonding wires are properly formed by determining whether or not the interval between the bonding wires classified into the same group is within a predetermined value range. A semiconductor design support method comprising steps. Designing a semiconductor device;
Comprising the step of manufacturing the semiconductor device,
The designing step includes
(A) reading out chip data that is information relating to the semiconductor chip from the storage unit, and generating pad position data having information on arrangement positions of a plurality of electrode pads arranged on the semiconductor chip based on the chip data; ,
(B) When package data, which is information relating to a package on which the semiconductor chip is mounted, is read from the storage unit, and a plurality of lead electrodes arranged in the package are connected to a plurality of bonding wires based on the package data Generating lead electrode data having information on the connection points of
(C) generating bonding wire data based on the pad position data and the lead electrode data;
(D) classifying the plurality of bonding wires into groups;
(E) performing the determination based on the chip data and the package data,
The step (d) includes:
Calculating a difference in length between adjacent bonding wires of the plurality of bonding wires;
Classifying the adjacent bonding wires into the same group when the difference is less than a predetermined threshold;
The step (e) includes:
It is determined whether or not the bonding wires are appropriately formed by determining whether or not an interval between the bonding wires classified into the same group is within a predetermined value range. Including steps,
The manufacturing step includes:
A method for manufacturing a semiconductor device, comprising: manufacturing the semiconductor device based on a determination result obtained in the step (e). Designing a semiconductor device;
Comprising the step of manufacturing the semiconductor device,
The designing step includes
Designing a semiconductor device;
Comprising the step of manufacturing the semiconductor device,
The designing step includes
(A) reading out chip data that is information relating to the semiconductor chip from the storage unit, and generating pad position data having information on arrangement positions of a plurality of electrode pads arranged on the semiconductor chip based on the chip data; ,
(B) When package data, which is information relating to a package on which the semiconductor chip is mounted, is read from the storage unit, and a plurality of lead electrodes arranged in the package are connected to a plurality of bonding wires based on the package data Generating lead electrode data having information on the connection points of
(C) generating bonding wire data based on the pad position data and the lead electrode data;
(D) classifying the plurality of bonding wires into groups;
(E) performing the determination based on the chip data and the package data,
The step (d) includes:
Calculating a difference in length between adjacent bonding wires of the plurality of bonding wires;
Classifying the adjacent bonding wires into the same group when the difference is less than a predetermined threshold;
The step (e) includes:
It is determined whether or not the bonding wires are appropriately formed by determining whether or not an interval between the bonding wires classified into the same group is within a predetermined value range. Including steps,
The manufacturing step includes:
A semiconductor device manufactured by a manufacturing method of a semiconductor device including a step of manufacturing the semiconductor device based on a determination result obtained in the step (e).

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