JP4860661B2 - Semiconductor package design method and semiconductor package layout design apparatus - Google Patents

Semiconductor package design method and semiconductor package layout design apparatus Download PDF

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JP4860661B2
JP4860661B2 JP2008135810A JP2008135810A JP4860661B2 JP 4860661 B2 JP4860661 B2 JP 4860661B2 JP 2008135810 A JP2008135810 A JP 2008135810A JP 2008135810 A JP2008135810 A JP 2008135810A JP 4860661 B2 JP4860661 B2 JP 4860661B2
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ball
semiconductor package
power supply
wire
terminals
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JP2009283779A (en
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孝行 松澤
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富士通セミコンダクター株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

  The present invention relates to a semiconductor package design method and a semiconductor package layout design apparatus.

  In recent years, semiconductor devices (LSIs) have been increasingly reduced in power supply voltage and circuit operation speed. As a result, the ratio between the high-potential side power supply voltage of the semiconductor device and the power supply noise is reduced. For example, the internal circuit malfunctions due to the power supply noise of the semiconductor device itself, and the influence of the power supply noise on the circuit operation of the semiconductor device increases. Yes.

  The power supply noise referred to here is an overshoot or undershoot that occurs when the power supply voltage drops or the internal circuit is switched. The power supply noise is the inductance and resistance of the internal circuit formed on the LSI, the wire of the semiconductor package, and the inductance of the interposer wiring that connects the terminal on the upper surface of the substrate connected to the wire and the ball terminal formed on the lower surface of the substrate. The electrical characteristics of resistance are greatly affected.

  Therefore, in recent years, when designing a semiconductor package using a semiconductor package layout design apparatus, it is necessary to design a semiconductor package with good power supply noise characteristics in consideration of power supply noise. In other words, the design of the layout of the wires of the semiconductor package on which the semiconductor device is mounted and the interposer wiring is important in improving the power supply noise characteristics.

  Therefore, conventionally, when designing a semiconductor package with good power supply noise characteristics using a design apparatus, power supply noise is measured and determined by the design apparatus when the design of the semiconductor package is completed. When the power supply noise characteristic is below a predetermined reference value, the semiconductor package has been redesigned.

Here, a semiconductor package design process by such a conventional semiconductor package layout design apparatus will be described.
As shown in FIG. 11, first, in step 101, the design apparatus performs power supply characteristic prediction. The design apparatus determines the power supply characteristics of a new semiconductor package based on the power supply characteristics of a semiconductor package designed in the past (hereinafter referred to as an existing semiconductor package) similar to the semiconductor package to be designed (hereinafter referred to as a new semiconductor package). Predict.

  Here, the power source characteristics include an I / O power source, an internal power source, a pad formed on the LSI to which GND is assigned, and a plurality of ball terminals formed on the lower surface of the substrate, and the I / O power source, This is an average of electrical characteristics (inductance and resistance) from a pad formed on an LSI to which various internal power sources and GND power sources are assigned to a ball terminal formed on the substrate.

  Next, in step 102, the design apparatus performs power supply noise analysis. The design apparatus performs power supply noise analysis based on the power supply characteristics of the new semiconductor package predicted in step 101. Here, the power supply noise analysis is that the design apparatus analyzes power supply noise using circuit simulation such as SPICE.

  Specifically, the design apparatus reflects the power supply characteristics of the new semiconductor package predicted in step 101 in a simulation circuit that models an internal circuit or a semiconductor package by using a circuit simulation such as SPICE. Then, the design apparatus performs simulation for power supply noise using a simulation circuit reflecting the predicted power supply characteristics (inductance and resistance) of the new semiconductor package.

  Subsequently, in step 103, the design apparatus designs a new semiconductor package. The design apparatus uses the layout data of the existing semiconductor package used for power supply characteristic prediction in step 101 to design the layout of wire wiring and the like of the new semiconductor package.

  When the design of the new semiconductor package (layout design such as wiring of wires) is completed, the process proceeds to step 104 where the design apparatus extracts the power supply characteristics. The design apparatus extracts power supply characteristics for the new semiconductor package designed in step 103.

  When the power supply characteristic for the new semiconductor package is extracted, in step 105, the design apparatus performs power supply noise analysis. The design apparatus performs power supply noise analysis based on the power supply characteristics extracted in step 104. Then, the design apparatus determines whether or not the analyzed power supply noise characteristic satisfies the standard. When the analyzed power supply noise characteristic satisfies the standard, the design apparatus completes the process using the designed new semiconductor package as final data. On the other hand, when the analyzed power supply noise does not satisfy the standard, the design apparatus redesigns a new semiconductor package.

However, the design apparatus may return to step 103 without processing steps 101 and 102 and design a layout such as wiring of a new semiconductor package again.
In addition, a method for selecting an optimum form and type of a semiconductor package before designing a new semiconductor package is known (see, for example, Patent Document 1). Here, the form of the semiconductor package is a multi-chip in which a plurality of semiconductor devices are stored in one semiconductor package, a stacked mounting in which a plurality of semiconductor devices are stacked and stored in one package, and the like. Types include QFP (Quad Flat Package), BGA (Ball Grid Array), and the like.
JP 2001-306644 A

  By the way, in the design method using the conventional semiconductor package layout design apparatus as described above, the power supply characteristic prediction accuracy of the new semiconductor package depends on the proximity of the design conditions with the existing semiconductor package. Here, the design conditions are various parameters of the package design such as the arrangement of pads, the number of pads, the size of the semiconductor device, the package size, and the interval between the ball terminals of the package.

  Therefore, if there is no existing semiconductor package whose design conditions are close to that of the new semiconductor package, the power supply characteristics of the new semiconductor package cannot be accurately predicted. In other words, the power supply characteristic of the designed new semiconductor package is a value far from the predicted power supply characteristic, and the power supply noise characteristic of the designed new semiconductor package is also a value far from the predicted power supply noise characteristic. As a result, the new semiconductor package has a problem in that the new semiconductor package is redesigned in order to satisfy the power supply noise characteristic standard, which increases the number of work steps.

  The disclosed semiconductor package design method and semiconductor package layout design apparatus have been made to solve the above-described problems, and are intended to reduce the number of work steps while stabilizing power supply noise characteristics in designing a semiconductor package. For the purpose.

  In this method, a semiconductor package layout design apparatus includes a plurality of terminals formed on the upper surface of a package substrate on which a semiconductor device on which a plurality of pads are formed along the upper surface periphery is mounted. A plurality of pads are formed in parallel to the formed row of pads, and each pad is connected to the corresponding terminal via a wire, and each terminal is formed on the lower surface of the package substrate via an interposer wiring. A method of designing a semiconductor package for creating layout data connected to a ball terminal, wherein the processing executed by the semiconductor package layout design apparatus is performed by a central processing unit provided in the semiconductor package layout design apparatus using a plurality of existing semiconductors For each package, a wire indicating the wiring of the wire. A first design process for storing wiring diagram data and ball layout data respectively indicating the arrangement of the ball terminals in a storage device; and the central processing unit includes: a new semiconductor package selected from the plurality of wire wiring diagram data; A second design process for determining similar wire wiring diagram data of the existing semiconductor package; and the central processing unit is configured to select the ball terminal for the determined wire wiring diagram data from the plurality of ball layout data. A third design process for determining the ball layout data in which the arrangement of the power supply noise characteristics is below the reference, and the central processing unit, based on the determined wire wiring diagram data and the ball layout data, Various power supply ball terminals, which are the ball terminals to which power is allocated, are connected to the pads. Calculated inductance and resistance, respectively, and a fourth design process of predicting the power supply noise characteristics.

  According to this configuration, in the second design process, the wire wiring diagram data of the existing semiconductor package similar to the new semiconductor package is determined from the plurality of wire wiring diagram data. Also, in the third design process, the arrangement of the ball terminals is less than the reference power supply noise characteristic arrangement with respect to the wire wiring diagram data determined in the second design process from the plurality of ball layout data. Determine the ball layout data.

  Then, in the fourth design process, the ball terminals to which power is allocated based on the wire wiring diagram data determined in the second design process and the ball layout data determined in the third design process up to the pad. Inductance and resistance were obtained, respectively, and power supply noise characteristics were predicted.

  Therefore, the power supply noise characteristic can be estimated with high accuracy before designing the semiconductor package, and the power supply noise characteristic of the semiconductor package can be easily improved. Moreover, in the design of the semiconductor package, it is not necessary to redesign, and the number of work steps can be reduced.

  According to the disclosed semiconductor package design method and semiconductor package layout design apparatus, it is possible to reduce the number of work steps while stabilizing power supply noise.

Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS.
As shown in FIG. 1, a semiconductor package layout design apparatus (computer) 11 for generating semiconductor package layout data comprises a general CAD (Computer Aided Design) apparatus, and a central processing unit (hereinafter referred to as CPU). 12, a memory 13, a storage device 14, a display device 15, an input device 16, and a drive device 17, which exchange data with each other via a bus 18.

  The CPU 12 executes a program using the memory 13 and realizes necessary processing such as semiconductor package design. The memory 13 stores programs and data necessary for providing various processes. The memory 13 typically includes a cache memory, a system memory, and a display memory.

  The display device 15 is used for displaying a semiconductor package, a parameter input screen, and the like, and for this, a CRT, LCD, PDP or the like is used. The input device 16 is used for inputting requests, instructions, patterns, and parameters from the user, and for this, a keyboard and a mouse device (not shown) are used.

  The CPU 12 as the wire wiring diagram data determination device, the ball layout data determination device, and the prediction device causes the display device 15 to display the pattern of the semiconductor package based on the layout data of the semiconductor package. Then, the CPU 12 adds and deletes the pattern on the display device 15 according to a signal from the input device 16 operated by the user, and adds and deletes the pattern to the layout data of the semiconductor package.

  The storage device 14 usually includes a magnetic disk device, an optical disk device, and a magneto-optical disk device. The storage device 14 stores program data and a file for generating semiconductor package data of the semiconductor device (semiconductor integrated circuit device) including the steps shown in FIG. The CPU 12 is stored in the storage device 14 in response to an instruction from the input device 16. The program and data are transferred to the memory 13 and executed.

  The drive device 17 drives the recording medium 19 and accesses the stored contents. The CPU 12 reads program data from the recording medium 19 via the drive device 17 and stores it in the storage device 14.

  As the recording medium 19, any computer-readable recording such as magnetic tape (MT), memory card, flexible disk, optical disk (CD-ROM, DVD-ROM,...), Magneto-optical disk (MO, MD,. Media can be used. The above-described program data can be stored in the recording medium 19 and loaded into the memory 13 for use as necessary.

  The recording medium 19 includes a medium and a disk device that record program data uploaded or downloaded via a communication medium. Furthermore, not only a recording medium that records a program that can be directly executed by a computer, but also a recording medium that records a program that can be executed once installed on another recording medium (such as a hard disk), or an encrypted program In addition, a recording medium on which a compressed program is recorded is also included.

Next, a schematic structure of a new semiconductor package designed by the semiconductor package layout design apparatus 11 will be described.
2 is a schematic configuration diagram for explaining a new semiconductor package, FIG. 3 is a schematic plan view for explaining terminals formed on the package substrate and pads provided on the LSI mounted on the package substrate, and FIG. 4 is a new semiconductor package. It is a schematic bottom view for demonstrating arrangement | positioning of the ball terminal provided in the package.

  As shown in FIG. 2, a new semiconductor package 21 to be designed has a package substrate 22, and an LSI 23 as a semiconductor device is mounted on the package substrate 22. The LSI 23 mounted on the package substrate 22 is molded with a resin 24.

  The LSI 23 has a plurality of external terminals 25 (hereinafter referred to as pads) as shown in FIG. Each pad 25 provided on the LSI 23 is formed along each side of the upper surface 23a of the LSI 23. As shown in FIG. 3, the pads 25 are formed along each side in two rows in a staggered manner. Incidentally, an array in which the pads 25 are formed in two rows in a staggered pattern along each side is referred to as a stagger type, and an array in which the pads 25 are formed in a row along each side is referred to as an inline type.

  As shown in FIG. 3, a plurality of terminals 26 are formed on the upper surface 22a of the package substrate 22 so as to surround the mounted LSI 23, and the plurality of terminals 26 are arranged in a staggered manner along each side of the upper surface 22a of the LSI 23. Each of the pads 25 is electrically connected to the corresponding pad 25 via a wire 27.

  The plurality of terminals 26 provided on the package substrate 22 are formed in three rows on the package substrate 22 in parallel with each side of the LSI 23. Here, for convenience of explanation, each terminal 26 in the column (first column) closest to the LSI 23 is referred to as a first-stage terminal 26a. Each terminal 26 (second row) next to each first stage terminal 26a is referred to as a second stage terminal 26b. Further, each terminal 26 in the farthest row (third row) is referred to as a third stage terminal 26c.

  Each pad 25 arranged on the upper surface 23a of the LSI 23 is connected to any one of the three rows of terminals 26 arranged in parallel along the side of the corresponding LSI 23 via the wire 27. Electrically connected.

  Incidentally, the wire 27 that connects the pad 25 of the LSI 23 and each first stage terminal 26a in the first row is referred to as a first stage wire 27a. The wires 27 that connect the pads 25 of the LSI 23 and the second-stage terminals 26b in the second row are referred to as second-stage wires 27b. Furthermore, the wire 27 that connects the pad 25 of the LSI 23 and the third-stage terminal 26c in the third row is referred to as a third-stage wire 27c. Accordingly, the length of the first stage wire 27a is the shortest, and then the length of the second stage wire 27b is short. The length of the third stage wire 27c is the longest.

  As shown in FIG. 4, a rectangular frame-shaped first ball terminal assignment region Z1 is provided on the lower surface 22b of the package substrate 22, and the outside of the first ball terminal assignment region Z1 is spaced apart by a predetermined distance. A two-ball terminal assignment region Z2 is provided. Further, a thermal ball region Z3 is provided inside the first ball terminal assignment region Z1 at a predetermined interval and at a position corresponding to the position where the LSI 23 is mounted.

  The assigned ball terminals 28 are provided in the first ball terminal assignment area Z1 and the second ball terminal assignment area Z2. The ball terminal 28 is provided with a power supply ball terminal 28A for various power supplies (I / O power supply, internal power supply, GND) and a signal ball terminal 28B for signals other than the power supply ball terminal 28A.

  The ball terminals 28 formed in the first ball terminal assignment area Z1 and the second ball terminal assignment area Z2 have the same shape and the same material, and in the areas Z1 and Z2, the same pitch in the horizontal direction and the vertical direction in FIG. Are arranged in Each ball terminal 28 is provided corresponding to each terminal 26 (26 a, 26 b, 26 c) formed on the upper surface 22 a of the package substrate 22, and is connected to the corresponding terminal 26 (26 a, 26 b, 26 c) and the package substrate 22. Each is electrically formed through the formed interposer wiring (not shown).

A plurality of thermal balls 28C having the same shape and the same material as the ball terminals 28 are formed in the thermal ball region Z3.
Next, an outline of the design process of the new semiconductor package 21 of the present embodiment will be described.

  The CPU 12 generates the layout data of the new semiconductor package 21 by executing the processes of steps 31 to 39 shown in FIG. 5, and further verifies the generated layout data of the new semiconductor package 21.

  First, in step 31, the CPU 12 determines the number of wire stages. The number of wire stages corresponds to the number of columns in which each terminal 26 provided on the package substrate 22 is arranged in parallel to one side of the LSI 23, and the wire 27 is connected from the pad 25 of the LSI 23 to the terminal 26 in each column. The number of columns that can be selected. Therefore, in the case of the new semiconductor package 21 shown in FIG. 3, since the terminals 26 are in three rows, the number of wire steps is three.

  The CPU 12 reads the wiring diagram data of the wires 27 (hereinafter referred to as “wire wiring diagram data”) connecting the terminals 26 of the new semiconductor package 21 and the pads 25 of the LSI 23 from the wire wiring library 40 and stores the new semiconductor package 21. Based on the design conditions, wire wiring diagram data with good power supply noise characteristics is determined.

  As shown in FIGS. 7 and 8, the wire wiring library 40 has a wiring diagram of each wire wiring diagram data determined according to various design conditions in a full matrix ball layout in which ball terminals 28 are arranged in a grid pattern. The arranged ball layout is made into a library and stored in the storage device 14.

  The wire wiring diagram data differs depending on the arrangement method of the pads 25, the number of pads 25, the number of stages of the wires 27, the type of the new semiconductor package 21, the interval between the ball terminals 28, and the like. Therefore, here, the various design conditions refer to the arrangement method of the pads 25, the number of pads 25, the number of stages of the wires 27, the type of the new semiconductor package 21, and the distance between the ball terminals 28.

Hereinafter, the determination process of the number of steps of the wire 27 performed based on these conditions will be described.
The CPU 12 selects the design object from the wire wiring library 40 in the order of design conditions, the arrangement method of the pads 25, the number of pads 25, the number of stages of the wires 27, the type of the new semiconductor package 21, and the interval of the ball terminals 28. The wire wiring diagram data of the wire wiring diagram whose design condition is close to that of the new semiconductor package 21 is selected. Then, the CPU 12 determines the wire wiring diagram data in which the number of stages of the wires 27 (the number of arrangement of the terminals 26) is large and the assembly feasibility of the semiconductor package 21 and the signal wiring feasibility are satisfied among the selected wire wiring diagram data. .

  That is, by selecting the wiring diagram of the wire wiring diagram data having a large number of stages of the wires 27, the wire angle θ (see FIG. 3) is reduced, so that the length of the wire 27 can be shortened. Here, as shown in FIG. 3, the wire angle θ is an angle at which the wires 27 at both ends of each side of the new semiconductor package 21 expand outward. Therefore, if the number of stages of the wires 27 is large, the wires 27 are shortened, and the inductance and resistance of the wires 27 are reduced. Therefore, the power supply noise characteristics of the new semiconductor package 21 are also improved.

  Further, the assembly feasibility of the new semiconductor package 21 means that the semiconductor package 21 can actually be assembled. The cause of the inability to assemble is the contact between adjacent wires 27. The contact between the wires 27 is more likely to occur as the number of steps of the wires 27 is smaller.

  That is, when the number of stages of the wires 27 decreases, the number of wires 27 increases per stage. For this reason, the row in which the terminals 26 are arranged is wider than the row in which the pads 25 are arranged. In the row in which the terminals 26 are arranged, the inclination of the wires 27 increases from the central portion of the row in which the terminals 26 are arranged toward both ends, so that the interval between the wires 27 is narrowed. As a result, when the number of steps of the wires 27 decreases, the possibility that adjacent wires 27 come into contact with each other increases. For example, it can be seen that the number of three wire stages shown in FIG. 7 has a larger wire angle θ than the number of four wire 27 shown in FIG. 8, and the possibility that the wires 27 are in contact with each other is higher.

  Further, the signal wiring feasibility means that the interposer wirings assigned to the signal ball terminals 28B excluding the power supply ball terminals 28A for various power sources (I / O power source, internal power source, GND) can be wired. Say. As the number of stages of the wires 27 increases, the area for interposer wiring connected to the signal ball terminal 28B decreases. That is, among the wires 27, the short wire 27 is connected to the power supply ball terminal 28A for various power supplies in order to improve the power supply characteristics, so the wire 27 connected to the signal ball terminal 28B is long. Is assigned to the long wire 27.

  On the other hand, when the number of stages of the wires 27 is increased, the distance between the terminal 26 connected to the signal ball terminal 28B and the signal ball terminal 28B is reduced, and the interposer wiring connected to all the signal ball terminals 28B cannot be wired. there is a possibility. For example, the region d1 for wiring the interposer wiring connected to the signal ball terminal 28B having three stages of wires 27 shown in FIG. 7 is connected to the signal ball terminal 28B having four stages of wires 27 shown in FIG. It can be seen that it is longer than the region d2 where the interposer wiring to be connected is wired.

Therefore, the optimum number of steps of the wire 27 is determined within a range in which the interposer wiring can be wired.
When the wire wiring diagram data having design conditions similar to those of the new semiconductor package 21 is determined from the wire wiring library 40 as described above, in step 32, the CPU 12 performs ball layout processing.

  Based on the wire wiring diagram data determined in step 31, the CPU 12 has a wire 27 having a short length (hereinafter referred to as a short wire in the case of FIG. 3) in the ball layout stored in the wire wiring library 40. A ball layout that can be connected to the ball terminal 28 at a short distance from the terminal 26 (first stage terminal 26a) to which the first stage wire 27a is connected is determined.

The detailed ball layout determination process will be described with reference to FIG.
As shown in FIG. 6, in step 61, the CPU 12 selects a standard ball layout. The CPU 12 selects and reads one standard ball layout from the standard ball layouts stored in the standard ball layout library 41. Here, the standard ball layout stored in the standard ball layout library 41 includes information on the type of the new semiconductor package 21 and the distance between the ball terminals 28.

  This standard ball layout is a ball layout used for a semiconductor package having a standard arrangement of ball terminals 28 and a large number of productions among ball layouts designed in the past. Generally, a semiconductor package with a large number of productions has a lower cost for the semiconductor package because the initial investment can be divided by the number of productions, compared with a semiconductor package with a small number of productions.

  When one standard ball layout is selected and read, in step 62, the CPU 12 determines whether or not the read standard ball layout satisfies the following condition (referred to as a first condition).

Here, the contents of the first condition are the following (1) and (2).
(1) Close to the terminal 26 (first stage terminal 26a) for connecting the short wire (first stage wire 27a) of the determined wire wiring diagram to the ball terminal 28 of the read standard ball layout, for example, Various power supply ball terminals 28A (I / O power supply ball terminals, internal power supply ball terminals, GND ball terminals) within the range within the first or second ball terminal 28 from the terminal 26 (first ball terminal assignment region Z1) ).
(2) A range (second ball terminal assignment) provided outside the range (first ball terminal assignment region Z1) to which various power supply ball terminals 28A connected to the short wires 27 (first-stage wires 27a) are allocated. For example, 50 to 60 balls of the various power supply ball terminals 28A are allocated to the area Z2).

  If the read standard ball layout satisfies the first condition (YES in step 62), the CPU 12 determines the read standard ball layout as final data and completes the process.

On the other hand, if the read standard ball layout does not satisfy the first condition (NO in step 62), the CPU 12 proceeds to step 63.
In step 63, the CPU 12 confirms whether or not an unprocessed ball layout remains in the standard ball layout library 41. If an unprocessed ball layout remains (YES in step 63), the CPU 12 returns to step 61. That is, the CPU 12 repeatedly performs steps 61 to 63 until the standard ball layout read in step 61 satisfies the first condition.

  If all the standard ball layouts stored in the standard ball layout library 41 are processed and there is no standard ball layout that satisfies the first condition (NO in step 63), the CPU 12 proceeds to step 64.

  In step 64 (is the cost constraint relaxed), the CPU 12 determines whether or not the development cost of the new semiconductor package 21 is higher than the development cost of the new semiconductor package 21 designed using the new wire wiring diagram and ball layout. To do.

  That is, when a new wire wiring diagram and ball layout are newly designed, the number of work steps is increased as compared with the case where a new semiconductor package 21 is designed by diverting the existing wire wiring diagram and ball layout. Expense increases. Therefore, here, whether or not the development cost when the new semiconductor package 21 is developed using the new wire wiring diagram and ball layout exceeds the development cost permitted in the development of the new semiconductor package 21 this time. Is judged.

  If the development cost of the semiconductor package design when designing using a new wire wiring diagram or ball layout does not exceed the allowable development cost (YES in step 64), the CPU 12 proceeds to step 65. In step 65 (ball layout creation), the CPU 12 newly designs a new semiconductor package 21 based on the following second condition, and completes the process using the layout data of the semiconductor package 21 as final data.

Here, the contents of the second condition are the following (1) to (4).
(1) Various power supply ball terminals 28A close to the terminal 26 to which the wire 27 is connected with respect to the read ball terminal 28 of the standard ball layout, for example, within a range within the first or second ball 27 from the terminal 26. (I / O power supply ball terminal, internal power supply ball terminal, GND ball terminal) are allocated.

  (2) Various power supply ball terminals 28A (I / O power supply ball terminals, internal power supply ball terminals) remaining in a range provided outside the range of (1) (range in which various power supply ball terminals 28A are allocated) , Ball terminals for GND) are allocated, for example, 50 to 60 balls.

  (3) For example, 64 balls of the thermal ball 28C are allocated to the position (thermal ball region Z3) corresponding to the position where the LSI 23 is mounted on the lower surface 22b of the package substrate 22.

(4) The ball terminals 28 other than the ball terminals (power supply ball terminal 28A and thermal ball 28C) assigned to each range under the conditions (1) to (3) are deleted.
On the other hand, if the development cost of the semiconductor package design when designing using new wire wiring diagram data or ball layout exceeds the allowed development cost (NO in step 64), the CPU 12 proceeds to step 66. In step 66 (reading standard ball layout), the CPU 12 reads one standard ball layout from the standard ball layouts stored in the standard ball layout library 41.

Next, in step 67, the CPU 12 determines whether or not the standard ball layout read in step 66 satisfies the following third condition.
Here, the content of the third condition is close to the terminal 26 of the wiring diagram of the wire wiring diagram data determined in the process of determining the number of stages of the wires 27 with respect to the ball terminal 28 of the read standard ball layout. Various power supply ball terminals 28A (I / O power supply ball terminals, internal power supply ball terminals, GND ball terminals) are assigned within the range of the first or second ball terminal 28 from the terminal 26.

  If the read standard ball layout satisfies the third condition (YES in step 67), the CPU 12 completes the process using the standard ball layout read in step 66 as final data. On the other hand, if the read standard ball layout does not satisfy the third condition (YES in step 67), the CPU 12 proceeds to step 68.

  In step 68 (whether there is an unprocessed standard ball layout?), The CPU 12 checks whether or not a ball layout that has not been processed in steps 66 and 67 remains in the standard ball layout library 41. If a ball layout that has not been processed in steps 66 and 67 remains (YES in step 68), the CPU 12 proceeds to step 66. That is, the CPU 12 repeatedly performs steps 66 to 68 until the standard ball layout read in step 66 satisfies the condition.

  If all the standard ball layouts stored in the standard ball layout library 41 are processed and there is no standard ball layout that satisfies the third condition (NO in step 68), the CPU 12 proceeds to step 69. To do.

  In step 69 (selection of standard ball layout), the CPU 12 reads one of the standard ball layouts stored in the standard ball layout library 41 again.

  In step 70 (whether the fourth condition is satisfied), the CPU 12 selects a standard ball layout satisfying the following fourth condition from the standard ball layout read in step 69. Here, the content of the fourth condition is that the distance between the first ball terminal assignment area Z1 in the read standard ball layout and the terminal 26 of the wire wiring diagram determined in the process of determining the number of stages of the wires 27 is the shortest. Choose one. Then, the CPU 12 completes the process using the standard ball layout that satisfies the fourth condition as the final data.

  Here, as an example, 64 thermal balls 28C arranged in the thermal ball area Z3, 56 various power supply ball terminals 28A arranged in the first ball terminal assignment area Z1, and 2nd ball terminal assignment area Z2 A case will be described in which 50 power supply ball terminals 28A are arranged.

  As shown in FIG. 9, in the ball layout, a first ball terminal assignment area Z1, a second ball terminal assignment area Z2, and a thermal ball area Z3 are allocated on the package substrate 22. In FIG. 9, the ball terminals 28 arranged in each of the regions Z1 to Z3 are shown by one grid that is partitioned in a grid pattern.

  Various power supply ball terminals 28A (I / O power supply ball terminals, internal power supply ball terminals, GND ball terminals) assigned to the first ball terminal assignment area Z1 and the second ball terminal assignment area Z2 are lattices. The net name is described in Here, the ball terminal for I / O power supply, the ball terminal for internal power supply, and the ball terminal for GND are indicated by “I”, “V”, and “G”, respectively. The ball terminal for signal 28B assigned to the second ball terminal assignment area Z2 is indicated by a blank in the lattice.

  Also, the ball 28 assigns other various power supply ball terminals 28A (I / O power supply ball terminal I, internal power supply ball terminal V, GND ball terminal G) and signal ball terminals in the regions Z1, Z2 and Z3. The ball 28 has been deleted from the areas Z4 and Z5 that are not provided.

  The thermal ball area Z3 is arranged in the area below the LSI 23 in a configuration of eight thermal balls 28C vertically and eight thermal balls 28C horizontally. However, as long as the thermal ball region Z3 is a region below the LSI 23, any configuration (for example, seven thermal balls 28C vertically, nine thermal balls 28C horizontally, nine thermal balls 28C vertically, There may be seven thermal balls 28C on the side.

  The first ball terminal assignment area Z1 is annularly provided on the outer periphery of the thermal ball area Z3. Accordingly, the various power supply ball terminals 28A are arranged in the first ball terminal assignment region Z1. The second ball terminal assignment area Z2 is provided in an annular shape on the outer periphery of the first ball terminal assignment area Z1. In the second ball terminal assignment area Z2, various power supply ball terminals 28A and signal ball terminals 28B are arranged. The signal ball terminals 28B are evenly arranged in the second ball terminal assignment region Z2 so as not to cause the signal ball terminals 28B to interfere with each other.

  By performing such a ball layout determination process, the CPU 12 can reduce the number of ball layout reviews. When the ball layout is determined under the first condition and the second condition, there is no need for reconsideration. When the ball layout is determined under the third condition, the reexamination is performed once. When the ball layout is determined under the fourth condition, the reexamination is performed. It turns out that becomes 3 times. Therefore, when the ball layout is determined under the first condition and the second condition, the CPU 12 does not need to review the ball layout, so that the development period of the new semiconductor package 21 can be shortened.

Next, when the ball layout is determined in step 32, in step 33, the CPU 12 assigns the power supply ball terminal 28A.
For the ball layout determined in step 32, the CPU 12 designates each selected ball terminal 28 as a power supply ball terminal 28A, and each of the power supply ball terminals 28A has an I / O power supply ball terminal I and an internal power supply ball terminal V, respectively. , One of the GND ball terminals G is assigned.

In step 34, the CPU 12 estimates power supply characteristics.
The CPU 12 applies a short wire (in FIG. 3) to each of the power supply ball terminals 28A assigned in the ball layout determined in step 33, among the wires 27 in the wiring diagram of the wire wiring diagram data determined in step 31. The first stage wire 27a) is assigned. Then, the CPU 12 calculates power supply characteristics for each power supply ball terminal 28A (I / O power supply ball terminal I, internal power supply ball terminal V, GND ball terminal G).

Next, details of the power supply characteristic estimation processing will be described.
The power supply characteristics are the electrical characteristics (inductance and resistance) of the wire 27 and the interposer wiring connected to various power supply ball terminals 28A (I / O power supply ball terminal I, internal power supply ball terminal V, GND ball terminal G). ) Is calculated. The CPU 12 can estimate by adding the electrical characteristics (inductance and resistance) of the wire 27 and the interposer wiring and averaging them.

Here, calculation of the electrical characteristics (inductance and resistance) of the wire 27 will be described first.
The CPU 12 assigns short wires to be connected to the various power supply ball terminals 28 </ b> A based on the wire wiring diagram data determined in the wire stage number determination process and the arrangement of the pads 25 of the LSI 23. Specifically, the CPU 12 sequentially connects each first-stage wire 27a to the GND ball terminal, and connects the remaining first-stage wires 27a to the I / O power supply ball terminal I and the internal power supply ball terminal V. To do.

  The CPU 12 determines the length of the wire 27 for each power supply ball terminal 28A. More specifically, as shown in FIG. 10, the length of the wire 27 is obtained by measuring the distance d3 between the pad 25 and the terminal 26 to be connected. Since there are a plurality of various power supply ball terminals 28A, the CPU 12 averages the length of the wire 27 connected to the various power supply ball terminals 28A for each of the various power supply ball terminals 28A. Each is calculated. The CPU 12 uses the inductance and resistance per unit distance (for example, per 1 mm) of the wire 27 stored in the storage device 14 (library) for the calculated length of each wire 27, The electrical characteristics (inductance and resistance) of the wire 27 are calculated for each power supply ball terminal 28A.

Next, electrical characteristics (inductance and resistance) of the interposer wiring will be described.
Since there are a plurality of power supply ball terminals 28A, the CPU 12 calculates the length per interposer wiring by averaging the lengths of the interposer wirings of the various power supply ball terminals 28A for each of the various power supply ball terminals 28A. . As shown in FIG. 10, the length of the interposer wiring is obtained by measuring the distance d4 between the terminal 26 and the ball 28 to be connected.

  The CPU 12 determines the inductance per unit distance (for example, per ball interval d5) of the interposer wiring stored in the storage device 14 (library) with respect to the length of the interposer wiring for each power supply ball terminal 28A. Based on the resistance, the electrical characteristics (inductance and resistance) of the interposer wiring are calculated for each power supply ball terminal 28A.

  As described above, before designing the semiconductor package 21, the number of wire stages is determined and the ball layout is determined. Among the wire wiring diagrams and ball layouts designed in the past, the specification of the semiconductor device to be designed is used. Select one with good power supply noise characteristics. Then, the CPU 12 performs power supply noise analysis processing based on the selected wire wiring diagram and ball layout, and determines whether or not the standard of power supply noise characteristics is satisfied. When the power supply noise characteristic standard is not satisfied, the above-described series of processing is repeated until the power supply noise characteristic standard is satisfied. Therefore, the power supply noise characteristic can be estimated with high accuracy before the new semiconductor package 21 is designed, and the power supply noise characteristic of the new semiconductor package 21 can be easily improved. Further, in designing the new semiconductor package 21, it is not necessary to redesign and the design period can be shortened.

Subsequently, in step 35, the CPU 12 performs power supply noise analysis.
The CPU 12 performs power supply noise analysis based on the power supply characteristics of the various power supply ball terminals 28 </ b> A calculated in step 34. The CPU 12 determines whether or not the standard of the power supply noise characteristic is satisfied based on the result of the power supply noise analysis. If the analyzed power supply noise characteristic satisfies the standard (YES in step 35), the CPU 12 proceeds to step 36. On the other hand, if the analyzed power supply noise characteristic does not satisfy the standard (NO in step 35), the CPU 12 proceeds to step 31.

If it is determined that the analyzed power supply noise characteristic satisfies the standard, in step 36, the CPU 12 generates a package design constraint.
The CPU 12 generates data including the number of wire stages, the ball layout, and various power supply ball terminals 28A information obtained in the processes of steps 31 to 33 as package design constraints.

When the package design constraint is generated, in step 37, the CPU 12 performs package design.
The CPU 12 designs a semiconductor package based on the package design constraint generated in step 36.

When the design of the new semiconductor package 21 is completed, in step 38, the CPU 12 performs power supply characteristic extraction.
The CPU 12 extracts the power supply characteristics of the various power supply ball terminals 28A of the new semiconductor package 21 designed in step 37.

Subsequently, in step 39, the CPU 12 performs power supply characteristic verification.
The CPU 12 compares the power characteristics estimated in Steps 34 (before designing the semiconductor package) and 38 (after designing the semiconductor package) to confirm whether there is a difference. If there is no difference in power supply characteristics before and after designing the semiconductor package, the CPU 12 completes the process using the layout data of the semiconductor package 21 designed in step 37 as final data. That is, if it is determined that the new semiconductor package 21 designed in step 37 has no difference in the power supply characteristics estimated in steps 34 and 38, the power supply noise characteristics depend on the power supply characteristics, so that the power supply noise characteristics are also different. It turns out that it meets the standard.

As described above, according to the present embodiment, the following effects can be obtained.
(1) According to the present embodiment, before designing the new semiconductor package 21, the number of wire steps is determined and the ball layout is determined. From the previously designed wire wiring diagram data and ball layout, a new Those having good power supply noise characteristics with respect to the specifications of the semiconductor package 21 are selected. Then, the CPU 12 performs power supply noise analysis processing based on the selected wire wiring diagram data and ball layout, and determines whether or not the power supply noise characteristic standard is satisfied. When the power supply noise characteristic standard is not satisfied, the above-described series of processing is repeated until the power supply noise characteristic standard is satisfied. Therefore, the power supply noise characteristic can be estimated with high accuracy before the new semiconductor package 21 is designed, and the power supply noise characteristic of the new semiconductor package 21 can be easily improved. Further, in designing the new semiconductor package 21, it is not necessary to redesign and the design period can be shortened.

  (2) According to the present embodiment, the wire wiring in which the row of the plurality of terminals 26 formed on the package substrate 22 is the largest among the wire wiring diagram data of the existing semiconductor package stored in the wire wiring diagram library 40. Graphic data was determined.

  Therefore, since the length of the wire can be shortened, the inductance and resistance of the wire are reduced, and the power supply noise characteristic of the new semiconductor package is improved. In addition, the distance between the wires can be widened, the possibility that adjacent wires come into contact with each other can be reduced, and the semiconductor package can be easily assembled.

  (3) According to the present embodiment, among the ball layout data stored in the standard ball layout library 41, the wire wiring diagram data having the most columns of the plurality of terminals 26 formed on the package substrate 22 is included. Of the wires 27, the ball layout data assigned the closest (or second closest) ball terminal 28 to the terminal 26 of the package substrate 22 to which the shortest or second shortest wire 27 is connected is determined. .

  Therefore, since the length of the interposer wiring can be shortened, the inductance and resistance of the interposer wiring are reduced, and the power supply noise characteristics of the new semiconductor package 21 can be improved.

  (4) According to the present embodiment, since many various power supply ball terminals 28A are allocated to the first ball terminal assignment area Z1, most of the power supply ball terminals 28A are connected to the power supply ball terminals 28A. The length of the interposer wiring can be shortened. As a result, the inductance and resistance of the interposer wiring are reduced, and the power supply noise characteristics of the new semiconductor package can be improved.

  (5) According to the present embodiment, the inductance and resistance per unit length of the wire 27 and the inductance and resistance per unit length of the interposer wiring connecting the terminal 26 and the ball terminal 28 are stored in the storage device 14 in advance. did. Then, the lengths of the wire 27 and the interposer wiring connected to the power supply ball terminal 28A are calculated, and the power supply ball terminal 28A is calculated based on the calculated value and the inductance and resistance per unit length stored in the storage device 14. The electrical characteristics up to the pad 25 were calculated.

Therefore, the electrical characteristics up to the pad 25 in the power supply ball terminal 28A can be easily calculated.
In addition, you may implement each said embodiment in the following aspects.

  In the above embodiment, the short-length wire 27 (first-stage wire 27a) is connected to the various power supply ball terminals 28A, and the various power supply ball terminals 28A are arranged in the first ball terminal assignment area Z1. However, the various power supply ball terminals 28A may be changed to signal ball terminals 28B.

  In the above embodiment, the new semiconductor package 21 that uses the wires 27 is designed. However, a semiconductor package that does not use wires such as a flip chip package may be designed. In other words, since the flip chip package does not use wires, the number of wire stages is not determined, and the power supply characteristics are estimated only by calculating the power supply characteristics of the interposer wiring.

  In the above-described embodiment, the determination process of the number of wire stages includes the arrangement method of the pads 25, the number of pads 25, the number of wire stages, the type of the new semiconductor package 21, and the distance d5 between the ball terminals 28 among the design conditions from the wire wiring library. In this order, wire wiring diagram data having design conditions close to those of the new semiconductor package 21 is determined. The arrangement method of the pads 25, the number of pads 25, the number of stages of the wires 27, the type of the new semiconductor package 21, and the distance d5 between the ball terminals 28 are determined. The order may be different.

It is a schematic block diagram of a semiconductor package layout design apparatus. It is a schematic block diagram of a semiconductor package. It is a schematic plan view of a semiconductor package. It is a schematic bottom view of a semiconductor package. It is a flowchart which shows the outline of a design method. It is a flowchart which shows a ball layout determination process. It is explanatory drawing of a wire wiring determination process. It is explanatory drawing of a wire wiring determination process. It is explanatory drawing of a ball layout. It is explanatory drawing of the estimation process of a power supply characteristic. It is a flowchart which shows the outline of the conventional design method.

Explanation of symbols

11 Semiconductor Package Layout Design Device 12 Central Processing Unit (CPU)
13 Memory 14 Storage Device 21 New Semiconductor Package 22 Package Substrate 23 Semiconductor Device (LSI)
25 External terminal (pad)
26 terminal 27 wire 28 ball terminal 28A power supply ball terminal 28B signal ball terminal Z1 first ball terminal assignment area Z2 second ball terminal assignment area Z3 thermal ball area

Claims (6)

  1. The semiconductor package layout design apparatus includes a plurality of terminals formed on the upper surface of the package substrate on which a semiconductor device having a plurality of pads formed along the upper surface periphery is mounted. A plurality of pads are formed in parallel to the row of pads, and each pad is connected to the corresponding terminal via a wire, and each terminal is a ball terminal formed on the lower surface of the package substrate via an interposer wiring. A semiconductor package design method for creating connected layout data,
    The process executed by the semiconductor package layout design apparatus is as follows:
    The central processing unit included in the semiconductor package layout design apparatus stores, in a storage device, wire wiring diagram data indicating the wiring of the wires and ball layout data indicating the arrangement of the ball terminals, respectively, for a plurality of existing semiconductor packages. A first design process to
    A second design process in which the central processing unit determines wire wiring diagram data of the existing semiconductor package similar to a new semiconductor package from the plurality of wire wiring diagram data;
    The central processing unit determines, from the plurality of ball layout data, ball layout data in which the arrangement of the ball terminals has a power noise characteristic arrangement below a reference with respect to the determined wire wiring diagram data. A third design process to
    Based on the determined wire wiring diagram data and the ball layout data, the central processing unit obtains an inductance and a resistance to the pads for each of the power supply ball terminals, which are the ball terminals to which power is allocated. And a fourth design process for predicting power supply noise characteristics.
  2. The method of designing a semiconductor package according to claim 1,
    The wire wiring diagram data of the existing semiconductor package determined in the second design process is
    Assembling the new semiconductor package and wiring to which signals are assigned can be wired, and the wire wiring diagram data having the largest number of columns of a plurality of terminals formed on the package substrate is provided. A method for designing a semiconductor package.
  3. The method of designing a semiconductor package according to claim 2,
    The ball layout data determined in the third design process is
    Of the wires in the wire wiring diagram data determined in the second design process, the shortest or the second shortest wire is connected to the terminal of the package substrate to which the shortest or the second shortest wire is connected. A method for designing a semiconductor package, characterized in that the ball layout data is assigned with ball terminals.
  4. The method of designing a semiconductor package according to claim 3,
    The ball layout data is
    On the lower surface of the package substrate,
    A thermal ball region in which a thermal ball is disposed at a lower surface position corresponding to a position where the semiconductor device is mounted;
    A first ball terminal assignment region in which the various power supply ball terminals are arranged in an annular shape on the outer periphery of the thermal ball region;
    A method for designing a semiconductor package, comprising: a plurality of power supply ball terminals and a second ball terminal assignment region in which signal ball terminals are arranged in an annular shape on an outer periphery of the first ball terminal assignment region.
  5. The method of designing a semiconductor package according to any one of claims 1 to 4,
    The fourth design process includes
    Inductance and resistance per unit length of the wire, and inductance and resistance per unit length of the interposer wiring connecting the terminal and the ball terminal are stored in the storage device in advance,
    The lengths of the wire and interposer wiring connected to the various power supply ball terminals are calculated, respectively, and based on the calculated value and the inductance and resistance per unit length stored in the storage device, the various power supply ball terminals A method for designing a semiconductor package, comprising calculating electrical characteristics up to the pad.
  6. A plurality of terminals formed on the upper surface of the package substrate on which a semiconductor device having a plurality of pads formed along the upper surface periphery is mounted are parallel to the pad array formed along the upper surface periphery. The layout data is created in which each pad is connected to the corresponding terminal via a wire, and each terminal is connected to a ball terminal formed on the lower surface of the package substrate via an interposer wiring. A semiconductor package layout design device,
    A storage device for storing wire wiring diagram data indicating the wiring of the wires and ball layout data indicating the arrangement of the ball terminals, respectively, for a plurality of existing semiconductor packages;
    A wire wiring diagram data determining device for determining wire wiring diagram data of the existing semiconductor package similar to a new semiconductor package from the plurality of wire wiring diagram data;
    Ball layout data in which the arrangement of the ball terminals has a power noise characteristic arrangement below a reference with respect to the determined wire wiring diagram data among the plurality of ball layout data by the wire wiring diagram data determination device. A ball layout data determination device for determining
    A predicting device for determining an inductance and a resistance up to the pad for each of the ball terminals to which power is allocated based on the determined wire wiring diagram data and ball layout data, and predicting power noise characteristics. Semiconductor package layout design equipment.
JP2008135810A 2008-05-23 2008-05-23 Semiconductor package design method and semiconductor package layout design apparatus Expired - Fee Related JP4860661B2 (en)

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