CN114330207A - Chip bonding pad information extraction method and system and electronic equipment - Google Patents
Chip bonding pad information extraction method and system and electronic equipment Download PDFInfo
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- CN114330207A CN114330207A CN202111669785.8A CN202111669785A CN114330207A CN 114330207 A CN114330207 A CN 114330207A CN 202111669785 A CN202111669785 A CN 202111669785A CN 114330207 A CN114330207 A CN 114330207A
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Abstract
The embodiment of the application relates to the field of storage device application, and discloses a chip pad information extraction method, a chip pad information extraction system and electronic equipment.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a method and a system for extracting information from a chip pad, and an electronic device.
Background
In flash memory devices, for example: during the manufacturing process of Solid State Drives (SSD), a chip is usually packaged. In chip packaging, the connection of the chip to the lead frame (or substrate) provides electrical connections for power and signal distribution. Ensuring the smooth electrical connection and input/output between the chip and the outside of the package is an important step in the packaging process. Flip Chip Bonding (Flip Chip Bonding) and Wire Bonding (Wire Bonding) are currently mainstream, and the Chip and the lead frame (or the substrate) can be connected. Although flip chip applications have grown rapidly, most of the connections are still wire bonded.
On the die, Pad Open of a die pin refers to a hole in the top metal of the die through which a bonding wire can be wired to the lead frame.
The accuracy rate of the conventional padopen data extraction method is low due to manual recording, and the mode of extracting padopen embedded in an EDA tool cannot be counted.
Based on this, there is a need for improvement in the art.
Disclosure of Invention
The embodiment of the application provides an information extraction method and system for a chip bonding pad and electronic equipment, so that the information extraction speed of the chip bonding pad is increased, and the packaging production efficiency is further improved.
In order to solve the above technical problem, an embodiment of the present application provides the following technical solutions:
in a first aspect, an embodiment of the present application provides an information extraction method for a chip pad, where the method includes:
acquiring configuration information of a chip layout, wherein the configuration information comprises length information and width information of the chip layout and pad region information of each pad region of a chip, and each pad region comprises a plurality of pads;
extracting coordinate information of each bonding pad of the chip layout;
according to the pad area information, performing area division on each pad, and determining a pad area corresponding to each pad;
generating a pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each pad;
and processing the pad layout of the chip to generate a pad distribution diagram of the chip.
In some embodiments, extracting coordinate information for each pad of the chip layout comprises:
extracting bottom-layer coordinates of four vertexes of each bonding pad from the chip layout;
top-level coordinates of four vertices of each pad are determined based on a first function, wherein the first function is used to map the bottom-level coordinates of the vertices to the top-level coordinates of the top-level of the layout.
In some embodiments, the method further comprises:
after the top coordinates of the four vertexes of each pad are extracted, the coordinates of the center point of each pad are converted according to the top coordinates of the four vertexes of each pad.
In some embodiments, the method further comprises:
and calculating the minimum pad pitch of the chip layout according to the coordinate information of each pad area.
In some embodiments, calculating the minimum pad pitch of the chip layout according to the coordinate information of each pad region includes:
determining the minimum pad spacing of each pad area according to the coordinate information of each pad area;
and determining the minimum pad pitch of the chip layout according to the minimum pad pitch of each pad region, wherein the minimum pad pitch of the chip layout is the minimum value of the minimum pad pitches of all the pad regions.
In some embodiments, the chip arrangement includes a single layer arrangement and/or a double layer arrangement, and calculating the minimum pad pitch of each pad region includes:
and calculating the single-layer minimum pad spacing and/or the double-layer minimum pad spacing of the chip based on a second function, wherein the second function is used for calculating the single-layer minimum pad spacing and/or the double-layer minimum pad spacing according to the center point coordinate of each pad.
In some embodiments, the pad region includes an upper region, a lower region, a left region, and a right region, the method further comprising:
and respectively carrying out reverse-time needle sequencing on each bonding pad in the upper area, the lower area, the left area and the right area.
In some embodiments, the method further comprises:
traversing each bonding pad of the chip layout to extract a label name of each bonding pad of the chip layout, wherein the label name of each bonding pad is bound with the coordinate information;
and if the label name does not exist or is not unique, determining that the pad has an error, and generating error reporting information.
In a second aspect, an embodiment of the present application provides an information extraction system for a chip pad, where the system includes:
the chip layout management system comprises an input module, a layout management module and a layout management module, wherein the input module is used for acquiring configuration information of a chip layout, the configuration information comprises length information and width information of the chip layout and pad region information of each pad region of a chip, and each pad region comprises a plurality of pads;
the extraction module is used for extracting the coordinate information of each bonding pad of the chip layout;
the algorithm module is used for carrying out region division on each bonding pad according to the bonding pad region information and determining the bonding pad region corresponding to each bonding pad;
the output module is used for generating a bonding pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each bonding pad; and processing the pad layout of the chip to generate a pad distribution diagram of the chip.
In a third aspect, an embodiment of the present application provides an electronic device, including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method according to the first aspect.
In a fourth aspect, embodiments of the present application further provide a non-transitory computer-readable storage medium storing computer-executable instructions for enabling a flash memory device to perform the method according to the first aspect.
The beneficial effects of the embodiment of the application are that: in contrast to the prior art, in the embodiment of the present application, a method, a system and an electronic device for extracting information from a chip pad are provided, where the method includes: acquiring configuration information of a chip layout, wherein the configuration information comprises length information and width information of the chip layout and pad region information of each pad region of a chip, and each pad region comprises a plurality of pads; extracting coordinate information of each bonding pad of the chip layout; according to the pad area information, performing area division on each pad, and determining a pad area corresponding to each pad; generating a pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each pad; and processing the pad layout of the chip to generate a pad distribution diagram of the chip. The method and the device have the advantages that the configuration information of the chip layout is obtained, the coordinate information of each bonding pad of the chip layout is determined, the bonding pad region corresponding to each bonding pad is determined, the bonding pad layout of the chip is generated, the bonding pad layout is processed, and a bonding pad distribution diagram is generated.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic view of a wire bond provided in an embodiment of the present application;
fig. 2 is a top view and a side view of a chip package provided by an embodiment of the present application;
FIG. 3 is a schematic diagram of a pad pitch according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of an information extraction method for a chip pad according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a graphical user interface of configuration information of a chip layout according to an embodiment of the present application;
FIG. 6 is a detailed flowchart of step S402 in FIG. 4;
fig. 7 is a schematic flowchart illustrating a process of calculating a minimum pad pitch of a chip layout according to an embodiment of the present application;
FIG. 8 is a schematic diagram of an arrangement of chips provided in an embodiment of the present application;
FIG. 9 is a schematic illustration of a single layer arrangement of wire bonding rules provided in an embodiment of the present application;
FIG. 10 is a schematic diagram of a pad pitch according to an embodiment of the present disclosure;
FIG. 11 is a table diagram illustrating an information of a pad according to an embodiment of the present application;
FIG. 12 is a diagram illustrating a pad distribution of a chip according to an embodiment of the present disclosure;
fig. 13 is a schematic structural diagram of an information extraction system for a chip pad according to an embodiment of the present disclosure;
fig. 14 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that, if not conflicted, the various features of the embodiments of the present application may be combined with each other within the scope of protection of the present application. Additionally, while functional block divisions are performed in apparatus schematics, with logical sequences shown in flowcharts, in some cases, steps shown or described may be performed in sequences other than block divisions in apparatus or flowcharts. In addition, the words "first", "second", "third", and the like used herein do not limit the data and execution order, but merely distinguish the same items or similar items having substantially the same functions and actions.
Before the present application is explained in detail, terms and expressions referred to in the embodiments of the present application are explained, and the terms and expressions referred to in the embodiments of the present application are applicable to the following explanations:
(1) wire Bonding (Wire Bonding) refers to a process of connecting an on-chip pad and a lead frame (or a substrate) with a very fine Wire.
(2) Pad Open refers to an opening in the top metal of the chip through which a bonding wire can be routed to the leadframe.
(3) Pad Pitch (Pad Pitch), i.e., the Pitch of the same edge of two adjacent identical pads (PadOpen).
Referring to fig. 1, fig. 1 is a schematic diagram of a wire bond according to an embodiment of the present disclosure;
as shown in fig. 1, Wire bonding (Wire bond) is a process of connecting a pad on a chip and a lead frame (or a substrate) with a very fine Wire.
Referring to fig. 2 again, fig. 2 is a top view and a side view of a chip package according to an embodiment of the disclosure;
as shown in fig. 2, Pad Open refers to a Pad of a chip pin on a chip die, which means that a hole is formed in a top metal of the chip, and a bonding wire can be pulled to a lead frame through the Pad, wherein Pad is an interface for connecting the inside of the chip and a chip package.
Referring to fig. 3, fig. 3 is a schematic diagram of a pad pitch according to an embodiment of the disclosure;
as shown in fig. 3, the Pad Pitch (Pad Pitch) refers to a Pitch of the same edge of two adjacent same pads (Pad Open), or adjacent different Pad sizes appear on one chip die, and the center Pitch of two Pad Open is Pad Pitch. The smallest Pad Pitch (Pad Pitch) among all Pad pitches on one die is generally taken.
At present, the mainstream of the chip adopts a wire bond packaging form, and the data of PadOpen is generally as much as dozens. In order to determine whether the PadOpen layout meets the packaging requirements, information such as PadOpen coordinates is extracted quickly and automatically, and a table is formed, which is very necessary in the design stage. On one hand, the method can assist in judging whether the PadOpen is reasonable or not in layout design. Alternatively, the table information is provided to a packaging plant as part of the chip packaging material to determine packaging feasibility.
Currently, the existing methods for extracting PadOpen data include:
(1) and manually recording, recording the PadOpen data into a table one by one, and extracting the inspection pad pitch. The disadvantages are that: the workload is large, repeated extraction is needed for each design modification, human errors are easy to occur, and the smallest pad pitch of the chip cannot be accurately obtained.
(2) And the EDA tool embeds and extracts the PadOpen data function, but the function is not complete. The drawback is that the function is not complete and the Pad Open profile cannot be output.
Based on this, the embodiment of the application provides an information extraction method for a chip bonding pad, so as to improve the information extraction speed of the chip bonding pad, output the bonding pad layout of a chip, and further improve the efficiency of packaging production.
Referring to fig. 4, fig. 4 is a schematic flowchart illustrating an information extraction method for a chip pad according to an embodiment of the present disclosure;
the information extraction method of the chip bonding pad is applied to electronic equipment, and particularly, an execution main body of the information extraction method of the chip bonding pad is one or more processors of the electronic equipment.
As shown in fig. 4, the method for extracting information from a chip pad includes:
step S401: acquiring configuration information of a chip layout, wherein the configuration information comprises length information and width information of the chip layout and pad region information of each pad region of a chip, and each pad region comprises a plurality of pads;
specifically, the configuration information of the chip layout is generated by data input by a user through a graphical user interface, specifically, a graphical user interface is pre-established, and the graphical user interface is used for receiving the configuration information of the chip layout input by the user, wherein the configuration information includes length information and width information of the chip layout and pad region information of each pad region of the chip. In an embodiment of the application, the graphical user interface is generated by a graphical interface built-in function of the EDA tool.
Referring to fig. 5 again, fig. 5 is a schematic diagram of a graphical user interface of configuration information of a chip layout according to an embodiment of the present application;
as shown in FIG. 5, in the graphical user interface, the configuration information entered by the user is printed into the output form and the output profile. The configuration information includes a project name, an information extraction date, a length and a width of a chip layout, a library name for generating a pad layout (a library name for generating a pad open layout), a layout cell name, and description information for specifying a process and a process of the chip, and specifically, the description information of the process includes information such as a thickness of a metal layer/a top metal used by a wafer factory/a process node/a chip, for example: the wafer factory is A factory, the process node is 40nm, and the metal layers used by the chip are a layer of poly, 7 layers of metal, wherein one layer of thick metal.
Wherein the configuration information further includes: single-layer arrangement information and/or double-layer arrangement information, and if a user selects to include single-layer arrangement (inlineppopen arrangement), determining that the configuration information includes single-layer arrangement information; if the user selects a double-layer arrangement (steady pad open arrangement), it is determined that the configuration information includes double-layer arrangement information. It is to be understood that, if the configuration information includes the two-layer arrangement information, the configuration information generally includes the single-layer arrangement information; if the user selects to include single-layer arrangement information, the configuration information includes only single-layer arrangement information.
Wherein, the configuration information further includes: pad area information of each pad area, wherein the pad area includes an upper area, a lower area, a left area, a right area, and an inner area, and a user selects pad areas (pad open areas) on four sides and inside of the chip by using a mouse frame on the graphical user interface, so as to determine coordinate values of the respective pad areas, for example: a coordinate range for each pad area.
In the embodiment of the application, the configuration information of the chip layout can be quickly and conveniently output to the information table of the bonding pad by inputting the configuration information of the chip layout by using the graphical user interface.
In the embodiment of the present application, the configuration information is maintained in the form of a configuration information file, for example: configuration information input by a user is stored in a configuration information file, so that the configuration information has the functions of storing and reloading, and the configuration information file can be read again later when the information (pad open information) of the chip bonding pad needs to be extracted again, so that the operation of repeatedly inputting related information is omitted, and the time is saved.
Step S402: extracting coordinate information of each bonding pad of the chip layout;
specifically, please refer to fig. 6 again, fig. 6 is a detailed flowchart of step S402 in fig. 4;
as shown in fig. 6, the step S402: extracting coordinate information of each pad of the chip layout, including:
step S4021: extracting bottom-layer coordinates of four vertexes of each bonding pad from the chip layout;
specifically, coordinate information (pad open coordinate information) of each pad of the entire chip is extracted.
Step S4022: top-level coordinates of four vertices of each pad are determined based on a first function, wherein the first function is used to map the bottom-level coordinates of the vertices to the top-level coordinates of the top-level of the layout.
Specifically, a first function is predefined, where the first function is used to map bottom coordinates of vertices to top coordinates of a top layer of the layout, that is, to determine top coordinates of four vertices of each pad, for example: the first function comprises a boxcar function, and the boxcar function is used for extracting coordinates of four vertexes of a rectangle from the layout and mapping the coordinates into coordinate values of the top layer of the layout. It will be appreciated that the pad (pad open) is rectangular and is mapped to the top level coordinates to ensure that all pad open coordinates are unique. And then extracting the pad open of the chip one by using the boxcar function, and saving the pad open by using a variable, which is beneficial to subsequent processing.
In an embodiment of the present application, the method further includes:
traversing each bonding pad of the chip layout to extract a label name of each bonding pad of the chip layout, wherein the label name of each bonding pad is bound with the coordinate information;
and if the label name does not exist or is not unique, determining that the pad has an error, and generating error reporting information.
Specifically, the label name of each pad is bound to the coordinate information of the pad. It will be appreciated that, in general, each pad (pad open) on a chip layout needs to be labeled with a name that marks the pad open corresponding to its chip pin. And judging whether the unique label name exists on the pad open by traversing all the pad opens, and if no label name exists on the pad open or only one label name exists on the pad open, generating error report information, so that a layout engineer can add the label name or correct the label name.
Step S403: according to the pad area information, performing area division on each pad, and determining a pad area corresponding to each pad;
specifically, according to the pad region information, region division is performed on each pad (pad open) to determine a pad region corresponding to each pad, and each pad in each pad region is sequenced, and the minimum pad pitch of the chip layout is calculated.
It can be understood that, because each pad in each pad area is sequenced, the position of each pad in the information table of the subsequently output pad is easier to locate, which is beneficial for a layout engineer to perform operations of adding a label or correcting a label name.
Wherein, carry out regional division to each pad, confirm the pad region that each pad corresponds, include:
the chip layout is divided into an upper area, a lower area, a left area, a right area and a middle area. The pad open area coordinate value input from the graphical user interface, i.e. the coordinate range of each pad area, is compared with the coordinate values of all pads (pad open coordinate value), if the pad open coordinate value falls within the pad open area coordinate value, then the pad open is classified into the corresponding area. For example, if the coordinate value of pad open1 is in the left region (left pad open region) of the chip layout, then pad open1 is drawn into the left region (left pad open region). And so on to determine the corresponding pad area of each pad.
In the embodiment of the application, after the top-level coordinates of the four vertexes of each pad are extracted, the top-level coordinates of the four vertexes of each pad are converted into the coordinates of the center point of each pad.
And calculating the minimum pad pitch of the chip layout according to the coordinate information of each pad area.
Specifically, please refer to fig. 7 again, fig. 7 is a schematic flow chart illustrating a process of calculating a minimum pad pitch of a chip layout according to an embodiment of the present application;
as shown in fig. 7, calculating the minimum pad pitch of the chip layout according to the coordinate information of each pad region includes:
step S701, determining the minimum pad interval of each pad area according to the coordinate information of each pad area;
referring to fig. 8 again, fig. 8 is a schematic diagram of a chip arrangement manner provided in the embodiment of the present application;
as shown in fig. 8, the chip arrangement includes a single-layer arrangement and a double-layer arrangement. It can be understood that the arrangement of the Pad Open of the chip is generally divided into Iline (single-layer arrangement or linear arrangement) and Stagger (double-layer arrangement or delta arrangement). Chip pad Open is typically placed around the chip. However, there may be some enhanced power Pad Open or test Pad Open inside the chip, and these internal Pad Open will not be pulled out of the chip. As shown In FIG. 8, the pad Open arrangement of the left chip is Inline, and the right chip is Stagger.
Referring to fig. 9, fig. 9 is a schematic diagram illustrating a single-layer wire bonding rule according to an embodiment of the present disclosure;
it can be understood that, in the chip layout design, the placement of the pad open must consider the wire bond rule (wire bond rule) to prevent that the package production cannot be performed because the rule of the package factory cannot be satisfied after the chip design is completed. Therefore, when the layout is designed, all pad open discharge information needs to be extracted from the layout, and the length and the width of each pad open, the coordinates of the central point of the pad open, the In-line/Stagger pad pitch and other information are counted. And the layout engineer performs a preliminary comparison according to the information and the wire bond rule of the packaging factory to see whether the requirements are met or not, thereby judging whether the design is advanced or not. Next, the statistical information is also given to the packaging engineer, and the packaging engineer will perform simulation of the wire bond and finally determine whether the arrangement of the pad open meets the packaging requirement.
As shown in fig. 9, LP represents padpost of the InLine arrangement, B, H represents the width and length of PadOpen, P1 represents padpost of the four corner region of the chip, and L represents the pitch (space) of two adjacent padposts.
Step S702: and determining the minimum pad pitch of the chip layout according to the minimum pad pitch of each pad region, wherein the minimum pad pitch of the chip layout is the minimum value of the minimum pad pitches of all the pad regions.
In the embodiment of the application, the minimum pad pitches of different arrangement modes are different. The pad area comprises an upper area, a lower area, a left area and a right area, and in order to better calculate the minimum pad pitch, the method further comprises the following steps: and respectively carrying out reverse-time needle sequencing on each bonding pad in the upper area, the lower area, the left area and the right area. By sequencing each bonding pad in the upper area, the lower area, the left area and the right area in a counterclockwise way and labeling each bonding pad in sequence, the bonding pads with error reporting information can be positioned conveniently.
Specifically, the chip arrangement mode includes single-layer arrangement and/or double-layer arrangement, and the calculation of the minimum pad pitch of each pad region includes:
and calculating the single-layer minimum pad spacing and/or the double-layer minimum pad spacing of the chip based on a second function, wherein the second function is used for calculating the single-layer minimum pad spacing and/or the double-layer minimum pad spacing according to the center point coordinate of each pad.
In the embodiment of the application, the pad pitch is a difference between central point coordinates of two adjacent pads, specifically, the pad pitch is a difference between abscissa and ordinate of the central point coordinates of two adjacent pads, and the difference between the abscissa and the difference between the ordinate are determined according to an origin position of a coordinate system established by a chip layout and an orientation of a pad.
Specifically, a second function is predefined, wherein the second function is used for calculating the single-layer minimum pad pitch and/or the double-layer minimum pad pitch according to the center point coordinates of each pad.
Specifically, the second function includes a findPitch function, and pad pitch operations are performed on the upper region, the lower region, the left region, and the right region, respectively, that is, pad pitches of the upper region, the lower region, the left region, and the right region are calculated, and different algorithms are used for different arrangement modes of a single-layer arrangement (In line) and a double-layer arrangement (stagger).
Specifically, a plurality of single-layer pad pitches of each pad region are calculated based on a second function to determine a single-layer minimum pad pitch of each pad region, wherein the single-layer minimum pad pitch is the minimum value of the plurality of single-layer pad pitches; calculating a plurality of double-layer pad pitches of each pad region based on a second function to determine a double-layer minimum pad pitch of each pad region, wherein the double-layer minimum pad pitch is the minimum value of the plurality of double-layer pad pitches;
and determining the minimum pad pitch of each pad region according to the single-layer minimum pad pitch and the double-layer minimum pad pitch of each pad region, wherein the minimum pad pitch of each pad region is the minimum value of the single-layer minimum pad pitch and the double-layer minimum pad pitch of the pad region.
And determining the minimum pad pitch of the chip layout according to the minimum pad pitch of each pad region, wherein the minimum pad pitch of the chip layout is the minimum value of the minimum pad pitches of all the pad regions.
For example: and finally, comparing the minimum In line pad pitch and the minimum stager pad pitch of each pad region, and finding out the minimum In line pad pitch and the minimum stager pad pitch of the chip to determine the minimum pad pitch of the chip layout, wherein the minimum pad pitch of the chip layout is the smaller value of the minimum In line pad pitch and the minimum stager pad pitch.
Referring to fig. 10 again, fig. 10 is a schematic diagram of a pad pitch according to an embodiment of the present disclosure;
as shown in fig. 10, an X value of the Pad Open center point coordinate is taken first, and the X values of two adjacent Pad opens are subtracted to obtain a Pad Pitch, and for single layer (Inline) and double layer (stager), respectively, all pads are determined, for example, a single layer Pad Pitch1, an Inline Pad Pitch2, and an Inline Pad Pitch3, and a double layer Pad Pitch stager Pitch1, a stager Pad Pitch2, a stager Pad Pitch3, a stager Pad Pitch4, a stager Pad Pitch5, and a stager Pad Pitch6, and a double layer minimum Pad Pitch stager Pad min and a single layer minimum Pad Pitch min in are found from all the Pad pitches to determine a minimum Pad Pitch.
Step S404: generating a pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each pad;
in an embodiment of the present application, before generating a pad layout of a chip, the method further includes:
the table of information for the output pads is formatted.
Referring to fig. 11, fig. 11 is a schematic diagram of an information table of a pad according to an embodiment of the present disclosure;
as shown in fig. 11, the Pad information table includes item names and process information descriptions, the length and width of the chip layout, the single-layer minimum Pad pitch (InLine) and the double-layer minimum Pad pitch (stagger), and the center point coordinate value (PadOpen center point coordinate value), the Pad length (PadOpen length), and the Pad width (PadOpen width) of each Pad.
Specifically, generating the pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each pad includes:
automatically generating layout commands supported by an EDA tool according to the length and the width of the chip layout and the coordinate information of each bonding Pad, and then automatically generating the bonding Pad layout (Pad open layout) of the chip by using the EDA tool, wherein the coordinate information of each bonding Pad comprises the coordinate information of four vertexes of each bonding Pad (the coordinate values of the four vertexes of the Pad open).
In an embodiment of the present application, the method further comprises: the length and width of each pad are determined from the top level coordinates of the four vertices of each pad.
Step S405: and processing the pad layout of the chip to generate a pad distribution diagram of the chip.
Specifically, a screenshot command is called to capture a pad layout of the chip so as to generate a pad distribution diagram of the chip. Referring to fig. 12, fig. 12 is a distribution diagram of pads of a chip according to an embodiment of the disclosure.
In the embodiment of the application, the output information table and the output distribution diagram of the bonding pads are helpful for judging whether the packaging rules of a packaging factory are met or not in advance during chip design, so that the repeated design steps are avoided, the output information table and the distribution diagram of the bonding pads can also be used as packaging data to be sent to the packaging factory, and whether the final production of the bonding pads of the chip can be realized or not is finally determined, so that the packaging production efficiency is improved.
It is understood that chip designs can be divided into logic circuit designs and physical designs. The physical design refers to a process of converting a logic circuit design into a layout which can be produced by a wafer factory. Therefore, the pad layout of the chip can be directly used for producing the wafer. And the packaging factory only needs padopen's relevant information just can carry out the chip package, need not use the pad territory of chip, consequently, through carrying out the screenshot to the pad territory of chip and handling to supply the encapsulation engineer to use.
In the embodiment of the application, by obtaining configuration information of a chip layout, the configuration information including length information and width information of the chip layout and pad region information of each pad region of a chip, each pad region including a plurality of pads, determining coordinate information of each pad of the chip layout, determining a pad region corresponding to each pad, generating the pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each pad, and processing the pad layout to generate a pad distribution map, the information extraction speed of the chip pad can be increased, the pad layout of the chip can be output, and the efficiency of packaging production can be increased.
Referring to fig. 13, fig. 13 is a schematic structural diagram of an information extraction system for a chip pad according to an embodiment of the present disclosure;
the information extraction system of the chip bonding pad is applied to an electronic device, and particularly, the information extraction system of the chip bonding pad is applied to one or more processors of the electronic device, and the electronic device comprises a terminal.
As shown in fig. 13, the information extraction system 130 for a chip pad includes:
the input module 131 is configured to obtain configuration information of the chip layout, where the configuration information includes length information and width information of the chip layout, and pad region information of each pad region of the chip, and each pad region includes a plurality of pads;
the extracting module 132 is configured to extract coordinate information of each pad of the chip layout;
the algorithm module 133 is configured to perform area division on each pad according to the pad area information, and determine a pad area corresponding to each pad;
the output module 134 is configured to generate a pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each pad; and processing the pad layout of the chip to generate a pad distribution diagram of the chip.
In the embodiment of the present application, the information extraction system of the die pad may also be built by hardware devices, for example, the information extraction system of the die pad may be built by one or more than two chips, and the chips may work in coordination with each other to complete the information extraction method of the die pad described in the above embodiments. For another example, the information extraction system of the chip pad may also be built by various types of logic devices, such as a general processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a single chip, an arm (acorn RISC machine) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components.
The information extraction system of the chip pad in the embodiment of the present application may be a device, or may be a component, an integrated circuit, or a chip in a terminal. The device can be mobile electronic equipment or non-mobile electronic equipment. By way of example, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the non-mobile electronic device may be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a Television (TV), a teller machine or a self-service machine, and the like, and the embodiments of the present application are not particularly limited.
The information extraction system of the chip pad in the embodiment of the present application may be a device having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, and embodiments of the present application are not limited specifically.
The information extraction system for the chip bonding pad provided by the embodiment of the application can realize each process realized in fig. 4, and is not repeated here to avoid repetition.
It should be noted that the information extraction system of the chip pad can execute the method of the information extraction system of the chip pad provided by the embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method. For technical details that are not described in detail in the embodiment of the system for extracting information from a chip pad, reference may be made to the method for extracting information from a chip pad provided in the above-mentioned embodiment.
In an embodiment of the present application, an information extraction system for a chip pad is provided, including: the chip layout management system comprises an input module, a layout management module and a layout management module, wherein the input module is used for acquiring configuration information of a chip layout, the configuration information comprises length information and width information of the chip layout and pad region information of each pad region of a chip, and each pad region comprises a plurality of pads; the extraction module is used for extracting the coordinate information of each bonding pad of the chip layout; the algorithm module is used for carrying out region division on each bonding pad according to the bonding pad region information and determining the bonding pad region corresponding to each bonding pad; the output module is used for generating a bonding pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each bonding pad; and processing the pad layout of the chip to generate a pad distribution diagram of the chip. The method and the device have the advantages that the configuration information of the chip layout is obtained, the coordinate information of each bonding pad of the chip layout is determined, the bonding pad region corresponding to each bonding pad is determined, the bonding pad layout of the chip is generated, the bonding pad layout is processed, and a bonding pad distribution diagram is generated.
Referring to fig. 14 again, fig. 14 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;
as shown in fig. 14, the electronic device 140 includes one or more processors 141 and a memory 142. In fig. 14, one processor 141 is taken as an example.
The processor 141 and the memory 142 may be connected by a bus or other means, and fig. 14 illustrates the connection by a bus as an example.
The processor 141 is configured to provide computing and control capabilities to control the electronic device 140 to perform corresponding tasks, for example, to control the electronic device 140 to perform the method for extracting information from the chip pad in any of the above method embodiments, including: acquiring configuration information of a chip layout, wherein the configuration information comprises length information and width information of the chip layout and pad region information of each pad region of a chip, and each pad region comprises a plurality of pads; extracting coordinate information of each bonding pad of the chip layout; according to the pad area information, performing area division on each pad, and determining a pad area corresponding to each pad; generating a pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each pad; and processing the pad layout of the chip to generate a pad distribution diagram of the chip.
The method and the device have the advantages that the configuration information of the chip layout is obtained, the coordinate information of each bonding pad of the chip layout is determined, the bonding pad region corresponding to each bonding pad is determined, the bonding pad layout of the chip is generated, the bonding pad layout is processed, and a bonding pad distribution diagram is generated.
The memory 142, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the information extraction method of the chip pad in the embodiment of the present application. The processor 141 may implement the information extraction method of the chip pad in any of the method embodiments described below by running non-transitory software programs, instructions, and modules stored in the memory 112. Specifically, memory 142 may include Volatile Memory (VM), such as Random Access Memory (RAM); the memory 142 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory (flash memory), a Hard Disk Drive (HDD) or a solid-state drive (SSD), or other non-transitory solid-state memory device; memory 142 may also comprise a combination of the above types of memory.
The memory 142 may include high speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 142 optionally includes memory located remotely from processor 141, which may be connected to processor 141 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more modules are stored in memory 142, and when executed by the one or more processors 141, perform the method for extracting information of a chip pad in any of the above-described method embodiments, e.g., perform the various steps shown in fig. 4 described above; the functions of the respective modules or units of fig. 13 can also be realized.
In this embodiment of the application, the electronic device 140 may further include a wired or wireless network interface, a keyboard, an input/output interface, and other components to facilitate input and output, and the electronic device 140 may further include other components for implementing device functions, which are not described herein again.
The electronic device of the embodiment of the present application exists in various forms, and performs the above-described steps shown in fig. 4; the functions of the various elements of FIG. 13 may also be implemented, including but not limited to: fixed terminal, mobile terminal, etc.
Embodiments of the present application also provide a computer-readable storage medium, such as a memory, including a program code, which is executable by a processor to perform the method for extracting information from a chip pad in the above embodiments. For example, the computer-readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a Compact Disc Read-Only Memory (CDROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.
Embodiments of the present application also provide a computer program product including one or more program codes stored in a computer readable storage medium. The processor of the electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code to perform the method steps of the information extraction method of the chip pad provided in the above-described embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by hardware associated with program code, and the program may be stored in a computer readable storage medium, where the above mentioned storage medium may be a read-only memory, a magnetic or optical disk, etc.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a general hardware platform, and certainly can also be implemented by hardware. It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; within the context of the present application, features from the above embodiments or from different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. An information extraction method for a chip bonding pad, the method comprising:
acquiring configuration information of a chip layout, wherein the configuration information comprises length information and width information of the chip layout and pad region information of each pad region of a chip, and each pad region comprises a plurality of pads;
extracting coordinate information of each bonding pad of the chip layout;
according to the pad area information, performing area division on each pad, and determining a pad area corresponding to each pad;
generating a pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each pad;
and processing the pad layout of the chip to generate a pad distribution diagram of the chip.
2. The method according to claim 1, wherein the extracting coordinate information of each pad of the chip layout comprises:
extracting bottom-layer coordinates of four vertexes of each bonding pad from the chip layout;
top-level coordinates of four vertices of each pad are determined based on a first function, wherein the first function is used to map bottom-level coordinates of the vertices to top-level coordinates of a top level of the layout.
3. The method of claim 2, further comprising:
after the top-level coordinates of the four vertexes of each bonding pad are extracted, the coordinates of the center point of each bonding pad are converted according to the top-level coordinates of the four vertexes of each bonding pad.
4. The method of claim 3, further comprising:
and calculating the minimum pad pitch of the chip layout according to the coordinate information of each pad area.
5. The method according to claim 4, wherein calculating the minimum pad pitch of the chip layout according to the coordinate information of each pad region comprises:
determining the minimum pad spacing of each pad area according to the coordinate information of each pad area;
and determining the minimum pad pitch of the chip layout according to the minimum pad pitch of each pad region, wherein the minimum pad pitch of the chip layout is the minimum value of the minimum pad pitches of all the pad regions.
6. The method according to claim 4 or 5, wherein the arrangement of the chips comprises a single-layer arrangement and/or a double-layer arrangement, and the calculating the minimum pad pitch of each pad region comprises:
and calculating the single-layer minimum pad spacing and/or the double-layer minimum pad spacing of the chip based on a second function, wherein the second function is used for calculating the single-layer minimum pad spacing and/or the double-layer minimum pad spacing according to the center point coordinate of each pad.
7. The method of claim 1, wherein the pad region comprises an upper region, a lower region, a left region, and a right region, the method further comprising:
and respectively carrying out reverse time needle sequencing on each bonding pad in the upper area, the lower area, the left area and the right area.
8. The method of claim 1, further comprising:
traversing each bonding pad of the chip layout to extract a label name of each bonding pad of the chip layout, wherein the label name of each bonding pad is bound with coordinate information;
and if the label name does not exist or is not unique, determining that the pad has an error, and generating error reporting information.
9. An information extraction system for a chip pad, the system comprising:
the chip layout management system comprises an input module, a control module and a control module, wherein the input module is used for acquiring configuration information of a chip layout, the configuration information comprises length information and width information of the chip layout and pad region information of each pad region of a chip, and each pad region comprises a plurality of pads;
the extraction module is used for extracting the coordinate information of each bonding pad of the chip layout;
the algorithm module is used for carrying out region division on each bonding pad according to the bonding pad region information and determining the bonding pad region corresponding to each bonding pad;
the output module is used for generating the pad layout of the chip according to the length information and the width information of the chip layout and the coordinate information of each pad; and processing the pad layout of the chip to generate a pad distribution diagram of the chip.
10. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117245266A (en) * | 2023-11-17 | 2023-12-19 | 深圳市大族封测科技股份有限公司 | Welding spot correction method and device, computer equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117245266A (en) * | 2023-11-17 | 2023-12-19 | 深圳市大族封测科技股份有限公司 | Welding spot correction method and device, computer equipment and storage medium |
| CN117245266B (en) * | 2023-11-17 | 2024-02-23 | 深圳市大族封测科技股份有限公司 | Welding spot correction method and device, computer equipment and storage medium |
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