CN116011394B

CN116011394B - Abnormality detection method, abnormality detection device, abnormality detection equipment and storage medium

Info

Publication number: CN116011394B
Application number: CN202310010291.1A
Authority: CN
Inventors: 万智泉; 霍婷婷; 邓庆文; 张汝云; 沈剑良; 刘勤让
Original assignee: Zhejiang Lab
Current assignee: Zhejiang Lab
Priority date: 2023-01-04
Filing date: 2023-01-04
Publication date: 2023-09-01
Anticipated expiration: 2043-01-04
Also published as: CN116011394A

Abstract

The specification discloses an anomaly detection method, device, equipment and storage medium, which can analyze each target connection network of a wafer substrate composed of each basic unit according to the position distribution of each basic unit in each layer structure of the wafer substrate in the layer structure and according to the preset superposition relation between each layer structure of the wafer substrate, so that each target connection network obtained by analyzing the wafer substrate layout can be compared with each connection network in a wafer substrate schematic diagram designed by a research staff to determine whether the wafer substrate is abnormal or not when the wafer substrate is prepared according to the wafer substrate layout, and further whether the prepared wafer substrate is in an error causing open circuit or short circuit anomaly or not can be effectively detected.

Description

Abnormality detection method, abnormality detection device, abnormality detection equipment and storage medium

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a method, an apparatus, a device, and a storage medium for detecting an abnormality.

Background

At present, the system on a chip technology gradually replaces the traditional printed circuit board (Printed Circuit Board, PCB) technology due to the characteristics of high cost performance, excellent energy consumption ratio and the like of the system on a chip.

In the prior art, the wafer substrate layout designed by the research and development personnel lacks an effective fault checking method, so that the correctness of the designed wafer substrate layout cannot be ensured, and further, the production test work of the designed wafer substrate is difficult to carry out.

Therefore, how to effectively detect the abnormality of the wafer substrate layout is a problem to be solved.

Disclosure of Invention

The present specification provides an abnormality detection method, apparatus, device, and storage medium, to partially solve the above-mentioned problems existing in the prior art.

The technical scheme adopted in the specification is as follows:

the present specification provides an abnormality detection method applied to a wafer substrate including: the micro-bump array layer, the micro-pad array layer, the rewiring layer, the via hole layer and the silicon through hole layer, wherein micro-bumps for realizing different functions contained in the micro-bump array layer are connected with micro-pads with corresponding functions in the micro-pad array layer through the rewiring layer, the via hole layer and the silicon through hole layer, and the method comprises the following steps:

the method comprises the steps of obtaining a wafer substrate layout of each layer structure of the wafer substrate, obtaining a schematic diagram of the wafer substrate, and aiming at each layer structure of the wafer substrate, wherein the wafer substrate layout comprises position distribution of each basic unit arranged in the layer structure, and the basic units comprise: at least one of metal lines, vias, through silicon vias, micro bumps, and micro pads;

Determining the position distribution of each basic unit arranged in each layer structure of the wafer substrate in the layer structure according to the wafer substrate layout, and determining each connection network formed by the connection relation between each basic unit in the wafer substrate layout when each micro bump contained in the micro bump array layer is connected with a corresponding micro pad in the micro pad array layer according to the position distribution of each basic unit arranged in each layer structure of the wafer substrate in the layer structure and the preset superposition relation between each layer structure of the wafer substrate, wherein each micro bump is connected with each basic unit through each basic unit as each target connection network;

and determining whether an abnormality exists when preparing the wafer substrate according to the wafer substrate layout according to whether the difference exists between each connecting network of the wafer substrate and each target connecting network in the schematic diagram.

Optionally, obtaining a wafer substrate layout of each layer structure of the wafer substrate specifically includes:

and acquiring a wafer substrate layout of each layer structure of the wafer substrate, determining a function identifier corresponding to each micro bump of the micro bump array layer in the wafer substrate layout, and determining a function identifier corresponding to each micro pad of the micro pad array layer in the wafer substrate layout.

Optionally, determining whether an abnormality exists when preparing the wafer substrate according to the wafer substrate layout according to whether a difference exists between each connection network of the wafer substrate and each target connection network in the schematic diagram, specifically includes:

judging whether the number of the target connection networks exceeds the number of the connection networks of the wafer substrate in the schematic diagram;

if yes, determining that open circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout.

Optionally, the method further comprises:

acquiring a function identifier of each target connection network, and judging whether the target connection network with the identifier type corresponding to the function identifier not being a designated type exists in each target connection network;

Optionally, the method further comprises:

determining a target connection network which is different from each connection network of the wafer substrate by 5 from each target connection network by comparing each target connection network with each connection network of the wafer substrate in the schematic diagram, and taking the target connection network as an abnormal connection network;

Determining each basic unit related to the abnormal connection network from each basic unit of the wafer substrate as an abnormal basic unit;

and determining the position 0 of the prepared wafer substrate with open-circuit abnormality in the wafer substrate layout according to the position distribution of each abnormal basic unit in the wafer substrate layout where the abnormal basic unit is located.

for each target connection network, determining a connection network corresponding to the target connection network 5 network in the connection networks of the schematic diagram as a basic connection network corresponding to the target connection network;

judging whether the function identifier of the target connection network is consistent with the function identifier of the basic connection network corresponding to the target connection network;

if not, determining that the short circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout.

Optionally, the method further comprises:

0 determining each sub-target connection network according to the position distribution of each basic unit in each layer structure of the wafer substrate in the layer structure and according to the preset superposition relation between each layer structure of the wafer substrate, wherein each connection network formed by the connection relation between each basic unit in the wafer substrate layout is used as each sub-target connection network when the micro-convex points of the abnormal connection network are connected with the corresponding basic units in the layer structure; and 5, determining whether the layer structure is abnormal or not according to the difference between the sub-target connection network corresponding to the wafer substrate under the layer structure in the wafer substrate layout and the sub-connection network corresponding to the wafer substrate under the layer structure in the schematic diagram aiming at each layer structure of the wafer substrate.

Optionally, the method further comprises:

acquiring the position distribution of each basic unit arranged in the layer structure in the wafer substrate layout;

and determining the position of the prepared wafer substrate with short circuit abnormality in the wafer substrate layout according to the position distribution of each basic unit arranged in the layer structure in the wafer substrate layout.

Optionally, the connection network includes: at least one of a power supply network, a ground network, a configuration network, a clock network, and a signal transmission network.

The present specification provides an abnormality detection apparatus including:

the device comprises an acquisition module, a control module and a control module, wherein the acquisition module is used for acquiring a wafer substrate layout of each layer structure of a wafer substrate and acquiring a schematic diagram of the wafer substrate, and aiming at each layer structure of the wafer substrate, the wafer substrate layout comprises the position distribution of each basic unit arranged in the layer structure, and the basic units comprise: at least one of metal lines, vias, through silicon vias, micro bumps, and micro pads;

the determining module is used for determining the position distribution of each basic unit arranged in each layer structure of the wafer substrate in the layer structure according to the wafer substrate layout, determining each connecting network formed by the connecting relation between each basic unit in the wafer substrate layout when each micro bump contained in the micro bump array layer is connected with a corresponding micro pad in the micro pad array layer according to the position distribution of each basic unit arranged in each layer structure of the wafer substrate in the layer structure and according to the preset superposition relation between each layer structure of the wafer substrate, and taking the connecting network formed by the connecting relation between each basic unit in the wafer substrate layout as each target connecting network, wherein the micro bumps are connected with the micro pads through the basic units;

And the detection module is used for determining whether the wafer substrate is abnormal or not according to the wafer substrate layout according to whether the difference exists between each connecting network of the wafer substrate and each target connecting network in the schematic diagram.

Optionally, the acquiring module is specifically configured to acquire a wafer substrate layout of each layer structure of the wafer substrate, determine a function identifier corresponding to each micro bump of the micro bump array layer in the wafer substrate layout, and determine a function identifier corresponding to each micro pad of the micro pad array layer in the wafer substrate layout.

Optionally, the detection module is specifically configured to determine whether the number of the target connection networks exceeds the number of the connection networks of the wafer substrate in the schematic diagram; if yes, determining that open circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout.

Optionally, the detection module is specifically configured to obtain a function identifier of each target connection network, and determine whether there is a target connection network in which an identifier type corresponding to the function identifier is not a specified type in the target connection networks; if yes, determining that open circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout.

The present specification provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the above-described abnormality detection method.

The present specification provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the above-described anomaly detection method when executing the program.

The above-mentioned at least one technical scheme that this specification adopted can reach following beneficial effect:

in the anomaly detection method provided in the present specification, firstly, a wafer substrate layout of each layer structure of a wafer substrate is obtained, and a schematic diagram of the wafer substrate is obtained, wherein for each layer structure of the wafer substrate, the wafer substrate layout includes a position distribution of each basic unit disposed in the layer structure, and the basic units include: at least one of metal wires, through holes, through silicon vias, micro bumps and micro pads is determined according to the wafer substrate layout, the position distribution of each basic unit arranged in each layer structure of the wafer substrate in the layer structure is determined, and according to the position distribution of each basic unit arranged in each layer structure of the wafer substrate in the layer structure and according to the preset superposition relation between each layer structure of the wafer substrate, each connection network formed by the connection relation between each basic unit in the wafer substrate layout when each micro bump contained in the micro bump array layer is connected with the corresponding micro pad in the micro pad array layer is determined as each target connection network, wherein each micro bump and each micro pad are connected through each basic unit, and according to whether the difference exists between each connection network and each target connection network of the wafer substrate in the schematic diagram, whether the wafer substrate is abnormal or not when the wafer substrate is manufactured according to the wafer substrate layout is determined.

According to the method, according to the position distribution of each basic unit arranged in each layer structure of the wafer substrate in the layer structure and the superposition relation among the preset layers of the wafer substrate, each target connection network of the wafer substrate formed by each basic unit is analyzed, so that each target connection network obtained through analysis of the wafer substrate layout and each connection network in a schematic diagram of the wafer substrate designed by a researcher can be compared to determine whether an abnormality exists when the wafer substrate is prepared according to the wafer substrate layout, and further whether an error causing the prepared wafer substrate to have an open circuit or a short circuit abnormality exists in the wafer substrate layout can be effectively detected.

Drawings

The accompanying drawings, which are included to provide a further understanding of the specification, illustrate and explain the exemplary embodiments of the present specification and their description, are not intended to limit the specification unduly. In the drawings:

fig. 1 is a schematic flow chart of an abnormality detection method provided in the present specification;

FIG. 2 is a schematic cross-sectional view of a wafer substrate provided in the present specification;

FIG. 3 is a schematic diagram of a wafer substrate layout corresponding to the micro bump array layer provided in the present specification;

FIG. 4 is a schematic diagram of a wafer substrate layout corresponding to a micro pad array layer provided in the present specification;

FIG. 5 is a schematic diagram of a wafer substrate layout provided in the present specification with a first redistribution layer corresponding to a first via layer;

FIG. 6 is a schematic diagram of a wafer substrate layout corresponding to a second redistribution layer and a second via layer provided in the present disclosure;

FIG. 7 is a schematic diagram of various connection networks included in the schematic diagram of the wafer substrate provided in the present specification;

FIG. 8 is a schematic diagram of each target connection network provided in the present specification;

FIG. 9 is a schematic diagram of a wafer substrate layout provided in this specification with open circuit anomalies;

FIG. 10 is a schematic diagram of a wafer substrate layout provided in this specification with shorting anomalies;

FIG. 11 is a schematic diagram of a sub-connection network corresponding to a wafer substrate under a first redistribution layer in the schematic diagram provided in the present specification;

FIG. 12 is a schematic diagram of a sub-connection network corresponding to a wafer substrate under a first rewiring layer in the wafer substrate layout provided in the present specification;

fig. 13 is a schematic view of an abnormality detection apparatus provided in the present specification;

Fig. 14 is a schematic view of an electronic device corresponding to fig. 1 provided in the present specification.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present specification more apparent, the technical solutions of the present specification will be clearly and completely described below with reference to specific embodiments of the present specification and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present specification. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.

The following describes in detail the technical solutions provided by the embodiments of the present specification with reference to the accompanying drawings.

Fig. 1 is a schematic flow chart of an abnormality detection method provided in the present specification, including the following steps:

s101: the method comprises the steps of obtaining a wafer substrate layout of each layer structure of the wafer substrate, obtaining a schematic diagram of the wafer substrate, and aiming at each layer structure of the wafer substrate, wherein the wafer substrate layout comprises position distribution of each basic unit arranged in the layer structure, and the basic units comprise: at least one of metal lines, vias, through-silicon vias, micro bumps, and micro pads.

In the present disclosure, a server of a service platform may detect a wafer substrate layout of each layer of structure of a wafer substrate designed by a researcher, so as to detect an error in the wafer substrate layout, which causes an open circuit or a short circuit abnormality in the prepared wafer substrate, and then may feed back the error to the researcher, so that the researcher corrects the detected error, as shown in fig. 2.

Fig. 2 is a schematic cross-sectional view of a wafer substrate provided in the present specification.

As can be seen from fig. 2, the wafer substrate is composed of a stack of layers, where each layer of the wafer substrate includes: the micro bump array layer, the micro pad array layer, the rewiring layer, the via hole layer, the silicon through hole layer and the like, wherein one surface of the wafer substrate is mainly used for connecting pins of heterogeneous core particles, the other surface of the wafer substrate is mainly used for connecting pins of the core particle configuration substrate, a system on a wafer can be formed by the wafer substrate, the heterogeneous core particles and the core particle configuration substrate, the micro bump array layer is arranged on one surface of the wafer substrate, a plurality of micro bumps for realizing different functions are contained in the micro bump array layer, the micro bumps can be connected with each heterogeneous core particle, the micro pad array layer is arranged on the other surface of the wafer substrate, a plurality of micro pads for realizing different functions are contained in the micro pad array layer, the micro pads are connected with the core particle configuration substrate, and the micro bumps are connected with micro pads with corresponding functions in the micro pad array layer through the via hole layer 1, the via hole layer 2 and the rewiring layer 2.

For example: the micro-bump for realizing signal transmission is connected with the micro-pad for realizing signal transmission in the micro-pad layer through the corresponding basic unit (the basic unit comprises at least one of metal wire, via hole, micro-bump and micro-pad) in different layer structures of the wafer substrate, so that heterogeneous core particles and core particle configuration substrates are connected through the wafer substrate, and the heterogeneous core particles and core particle configuration substrates are particularly shown in fig. 3 and 4.

Fig. 3 is a schematic diagram of a wafer substrate layout corresponding to the micro bump array layer provided in the present specification.

As can be seen from fig. 3, the micro bump array layer of the wafer substrate may be composed of a plurality of micro bumps for implementing different functions, preferably, the micro bump array layer of the wafer substrate may be composed of 36 micro bumps, which are mainly used for implementing five different functions, wherein VDD and V1 in fig. 3 respectively represent micro bumps for supplying power to different voltage domains, GND represents micro bumps for grounding, CLK1 and CLK2 represent micro bumps for transmitting different clock signals, F1 and F2 represent micro bumps for transmitting different configuration signals, and S1-S4 represent micro bumps for transmitting different transmission signals.

In fig. 3 and fig. 4, VDD, V1, GND, CLK1, CLK2, F1, F2, S1, S2, S3, S4, etc. are the function identifiers corresponding to each micro bump or micro pad.

Fig. 4 is a schematic diagram of a wafer substrate layout corresponding to the micro pad array layer provided in the present specification.

As can be seen from fig. 4, the micro pad array layer of the wafer substrate may be composed of several micro pads performing different functions, preferably, the micro pad array is composed of 16 micro pads, wherein VDD and V1 in fig. 4 respectively represent micro pads for supplying power of different voltage domains, GND represents micro pads for grounding, CLK1 and CLK2 represent micro pads for transmitting different clock signals, F1 and F2 represent micro pads for transmitting different configuration signals, and S1-S4 represent micro pads for transmitting different transmission signals.

The reason why the number of micro bumps in the micro bump array layer of the wafer substrate is different from the number of micro pads in the micro pad array layer is that the number of micro bumps in the micro bump array layer of the wafer substrate is different from the number of micro pads in the micro pad array layer because the die arrangement substrate pins are larger than the die pin size and the pitch.

Further, the micro bumps in the micro bump array layer of the wafer substrate may be connected to the micro pads in the micro pad array layer through the rewiring layer, the via layer and the through silicon via layer inside the wafer substrate, as shown in fig. 5 and fig. 6.

Fig. 5 is a schematic diagram of a wafer substrate layout provided in the present specification and corresponding to a first redistribution layer and a first via layer.

As can be seen from fig. 2 and fig. 5, the micro bumps in the micro bump array layer and the micro pads in the micro pad array layer located on the upper surface and the lower surface of the wafer substrate may be connected through the metal lines in the rewiring layer and the vias in the via layer inside the wafer substrate, in fig. 5, the patterns of the shapes of diamond, circle, triangle, square, pentagon, hexagon and the like are used to represent the vias used when the micro bumps of the wafer substrate are connected with the corresponding micro pads, wherein the circle represents the vias used when VDD corresponds to the micro bumps and is connected with the micro pads, the triangle represents the vias used when V1 corresponds to the micro bumps and is connected with the micro pads, the square represents the vias used when GND corresponds to the micro bumps and is connected with the micro pads, the hexagon represents the vias used when the micro bumps corresponding to F1 and F2 are connected with the micro pads, and the pentagon represents the vias used when the micro bumps corresponding to S1-S4 are connected with the micro pads.

The patterns of the shapes such as diamond, circle, triangle, square, pentagon, hexagon, etc. in the above description are only used to indicate different vias in the via layer, and do not mean that the actual shape of the via is the shape of these patterns.

In fig. 5, the shadows with different gray scales represent metal lines used for connecting different through holes in the first layer rerouting layer, and as can be seen from fig. 5, in the first layer rerouting layer, eight micro bumps corresponding to the round representation VDD can be connected together through the corresponding through holes in the first layer through hole layer by using the metal lines in the shape of a Chinese character 'jing', so that when the micro bumps are connected with the next layer through hole layer and the rerouting layer, connection can be completed only by using two through holes, and when the micro bumps are connected with the micro pads in the micro pad array layer, only two micro pads are occupied, namely eight micro bumps in the micro bump array layer are connected with two corresponding micro pads in the micro pad array layer.

Similarly, in fig. 5, three triangles representing V1 corresponding to three triangles located at the upper left corner of the via layer are connected together in the via layer of the first layer via layer by metal wires, three triangles representing V1 corresponding to three triangles located at the upper right corner of the via layer are connected together in the via layer of the first layer via layer, three triangles representing V1 corresponding to three triangles located at the lower left corner of the via layer are connected together in the via layer of the first layer via layer, and three triangles representing V1 corresponding to three triangles located at the lower right corner of the via layer are connected together in the via layer of the first layer via layer, so that only four micro pads in the micro pad array layer can be connected with twelve micro pads corresponding to V1 in the micro pad array.

Further, in fig. 5, the shading on the square, pentagon, diamond, hexagon corresponding via is used to characterize the connection with the metal lines and/or vias in the next re-routing layer and via layer by the metal lines passing through the via.

Fig. 6 is a schematic diagram of a wafer substrate layout corresponding to a second redistribution layer and a second via layer provided in the present specification.

As can be seen from fig. 6, eight micro bumps corresponding to the square representation GND can be connected together through the metal wire in the shape of a well in the corresponding via hole of the first layer, so that when the micro bumps are connected with the next layer of via hole layer and the rewiring layer, the connection can be completed only by using two via holes, and further, when the micro bumps are connected with the micro pads in the micro pad array layer, only two micro pads are occupied.

As can be seen from fig. 5 and fig. 6, when designing the wafer substrate layout, a developer can control how to connect the micro bumps in the micro bump array layer with the corresponding micro pads in the micro pad array layer by adjusting the position distribution of the metal wires in the rewiring layer and the through holes in the through holes layer, so that heterogeneous core particles and core particle configuration substrates can be connected through the wafer substrate, and signals with different functions can be transmitted.

Based on the above, when the wafer substrate layout designed by the researcher needs to be abnormally detected, each micro bump can be connected to the corresponding micro pad in the micro pad array layer through the metal wire, the via hole and the through silicon hole in each layer structure of the wafer substrate, and the connection relation among the micro bumps, the metal wire, the via hole, the through silicon hole and the micro pad is extracted to form a connection network, so that the wafer substrate layout designed by the researcher can be detected based on the connection network.

The connection network described above may be, for example: the micro-bump for transmitting clock signals is connected with a corresponding micro-pad in the micro-pad array layer through at least part of metal wires of the rewiring layer and at least part of through holes of the through hole layer, wherein the micro-bump, the metal wires connected with the micro-bump, the through holes connected with the micro-bump and the micro-pads connected with the micro-bump form a connecting network together.

The connection relationship between the basic units in the micro bump array layer, the via layer, the rewiring layer and the through silicon via layer in the wafer substrate layout can be analyzed, so that each target connection network can be extracted from the wafer substrate layout.

It should be noted that the connection network may be functionally divided into: a power supply network, a ground network, a configuration network, a clock network, a signal transmission network, etc.

In addition, when the wafer substrate layout of the wafer substrate is wrong, the wafer substrate layout is reflected from the extracted connection network of the wafer substrate, so that whether the wafer substrate layout is abnormal or not can be determined by detecting the connection network of the wafer substrate extracted based on the wafer substrate layout.

It should be noted that, when designing the wafer substrate, a developer usually designs a schematic diagram of the wafer substrate, and further designs a wafer substrate layout corresponding to each layer of structure of the wafer substrate according to the designed schematic diagram of the wafer substrate, so after extracting each connection network of the wafer substrate designed according to the wafer substrate layout based on the wafer substrate layout, the connection network of the wafer substrate designed according to the wafer substrate layout can be compared with each connection network designed by the developer in the schematic diagram to determine whether the wafer substrate layout is abnormal.

From the above, it can be seen that the connection network in the wafer substrate layout can be extracted to perform abnormality detection on the wafer substrate layout based on the extracted connection network, and before that, it is required to obtain the wafer substrate layout of each layer structure of the wafer substrate and obtain the schematic diagram of the wafer substrate.

Further, after the wafer substrate layout corresponding to the micro bump array layer and the wafer substrate layout corresponding to the micro pad array layer of the wafer substrate are obtained, the function identifier corresponding to each micro bump of the micro bump array layer in the wafer substrate layout and the function identifier corresponding to each micro pad of the micro pad array layer in the wafer substrate layout can be determined, which can be understood as determining the identifiers of the functions corresponding to the micro bumps and the micro pads in the micro bump array layer and the micro pad array layer in each wafer substrate layout, so as to be used for extracting the connection network corresponding to different functions from each wafer substrate layout based on the function identifiers corresponding to each micro bump and the micro pad, where the functions include: for grounding, for transmitting clock signals, for multi-voltage domain powering, etc., where the functional identification may include: VDD, V1, GND, CLK1, CLK2, F1, F2, S1 to S4, and the like.

In the present specification, the execution body for implementing the abnormality detection method may refer to a designated device such as a server provided on a service platform, or may refer to a designated device such as a desktop computer or a notebook computer, and for convenience of description, the abnormality detection method provided in the present specification will be described below by taking the server as an example of the execution body.

S102: and determining each connection network formed by the connection relation between each basic unit in the wafer substrate layout when each micro bump contained in the micro bump array layer is connected with a corresponding micro pad in the micro pad array layer according to the determined position distribution of each basic unit in each layer structure of the wafer substrate in the layer structure, the position distribution of each basic unit in each layer structure of the wafer substrate in the layer structure and the preset superposition relation between each layer structure of the wafer substrate, and the connection relation between each micro bump and each basic unit in the wafer substrate layout is used as each target connection network.

S103: and determining whether an abnormality exists when preparing the wafer substrate according to the wafer substrate layout according to whether the difference exists between each connecting network of the wafer substrate and each target connecting network in the schematic diagram.

Further, after the wafer substrate layout and the schematic diagram of the wafer substrate are obtained, the server may determine, according to the wafer substrate layout, the position distribution of each basic unit set in each layer structure of the wafer substrate in the layer structure, and determine, according to the position distribution of each basic unit set in each layer structure of the wafer substrate in the layer structure and according to the preset stacking relationship between each layer structure of the wafer substrate, each connection network formed by the connection relationship between each basic unit in the wafer substrate layout when each micro bump included in the micro bump array layer is connected to a corresponding micro pad in the micro pad array layer, as each target connection network, where the micro bump and the micro pad are connected through each basic unit, as shown in fig. 7 and 8.

Fig. 7 is a schematic diagram of each connection network included in the schematic diagram of the wafer substrate provided in the present specification.

As can be seen from fig. 7, when designing the schematic diagram of the wafer substrate, the developer designs for the wafer substrate what the connection network should have, what functions are respectively implemented, in the schematic diagram of the wafer substrate shown in fig. 7, it is shown that the wafer substrate designed by the developer should include 14 connection networks, which are connection networks 1 and 2 composed of respective basic units when the micro bumps for transmitting clock signals are connected to the corresponding micro pads, respectively, connection networks 3 and 4 composed of respective basic units when the micro bumps for transmitting different configuration signals are connected to the corresponding micro pads, connection networks 5 composed of respective basic units when the micro bumps for grounding are connected to the corresponding micro pads, connection networks 6, 7, 8, 9 composed of respective basic units when the micro bumps for transmitting different transmission signals are connected to the corresponding micro pads, and connection networks 10, 11, 12, 13, 14 composed of respective basic units when the micro bumps for not supplying power are connected to the corresponding micro pads.

When the micro-bumps for grounding and the corresponding micro-pads are connected, only one connection network 5 is formed in the connection network formed by each basic unit, because the corresponding through holes of the micro-bumps for grounding are connected through metal wires in the rewiring layer, the micro-bumps for grounding form the same connection network, and when the micro-bumps for grounding and the corresponding micro-pads are connected, only one connection network 5 is formed in the connection network formed by each basic unit.

Fig. 8 is a schematic diagram of each target connection network provided in the present specification.

As can be seen from fig. 8, each of the target connection networks extracted from the wafer substrate layout comprises 15 connection networks, namely target connection networks 1 and 2 for transmitting clock signals, target connection networks 3 and 4 for transmitting different configuration signals, target connection network 5 for grounding and for supplying power to different voltage domains, target connection networks 6, 7, 8, 9 for transmitting different transmission signals, target connection networks 10, 11, 12, 13, 14 for supplying power, and target connection network 15 for which no function can be determined.

If the wafer substrate layout designed by the developer is not abnormal, the number of the target connection networks and the function identifier corresponding to each target connection network extracted from the wafer substrate layout should be consistent with the number of the connection networks and the function identifier corresponding to each connection network in the schematic diagram, and as can be seen from the above, the number of the target connection networks and the function identifier corresponding to each target connection network extracted from the wafer substrate layout provided in fig. 8 are inconsistent with the number of the connection networks and the function identifier corresponding to each connection network in the schematic diagram, so that it can be determined that the abnormality exists in the wafer substrate layout corresponding to fig. 8.

Further, the server may determine whether the number of each target connection network exceeds the number of each connection network of the wafer substrate in the schematic diagram, if so, it may determine that an open circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout, because when an open circuit abnormality exists in the wafer substrate of each wafer substrate layout design, each basic unit corresponding to a certain connection network is not connected into one target connection network due to the open circuit, and because of the disconnected portion, each basic unit originally belonging to one target connection network forms two or more target connection networks respectively, so that the number of each target connection network exceeds the number of each connection network of the wafer substrate in the schematic diagram.

For example: it is assumed that one target connection network for transmitting clock signals in the wafer substrate is composed of a micro bump for transmitting clock signals in the micro bump array layer, one via in the first layer via layer, a metal wire in the first layer rerouting layer, a via in the second layer via layer, a metal wire in the second layer rerouting layer, a through silicon via in the through silicon via layer, a micro pad for transmitting clock signals in the micro pad array layer, and that when an open circuit abnormality exists in the first layer rerouting layer, the micro bump for transmitting clock signals is not connected with the micro pad for transmitting clock signals, so that there is one target connection network for transmitting clock signals originally split into two target connection networks for transmitting clock signals here.

In addition, the server can also acquire the identification of each target connection network, judge whether the target connection network with the identification type not being the designated type exists in each target connection network, and if yes, determine that the open circuit abnormality exists when preparing the wafer substrate according to the wafer substrate layout.

For example: if an open circuit abnormality exists in the first layer of the rewiring layer of the wafer substrate, the metal wire in the first layer of the rewiring layer is not connected with the micro-bump for transmitting the clock signal and the micro-pad for transmitting the clock signal, so that the metal wire alone serves as a target connection network of an uncertain function, namely, a target connection network of which the identification type is not a specified type.

Further, the server determines a target connection network inconsistent with each connection network of the wafer substrate from each target connection network by comparing each target connection network with each connection network of the wafer substrate in the schematic diagram, determines each basic unit related to the abnormal connection network from each basic unit of the wafer substrate as an abnormal connection network, and determines the position of the prepared wafer substrate with open circuit abnormality in the wafer substrate layout according to the position distribution of each abnormal basic unit in the wafer substrate layout where the abnormal basic unit is located.

For example: in each of the target connection networks shown in fig. 8, there are five target connection networks with the function identifier V1, but in the schematic diagram, there are only four connection networks with the function identifier V1, and in each of the target connection networks shown in fig. 8, there is also a connection network 15 with the function identifier 1 (i.e., a connection network with no function determination), at this time, it may be determined that there is an open circuit abnormality in the connection network for power supply in the wafer substrate of each wafer substrate layout design, at this time, it may be determined from each basic unit of the wafer substrate that there is an open circuit abnormality in the prepared wafer substrate according to the position distribution of each abnormal basic unit in the wafer substrate layout where the abnormal basic unit is located, and at this time, each basic unit related to the five target connection networks with the function identifier V1 (i.e., an abnormal connection network) may be determined as an abnormal basic unit, as shown in fig. 9.

Fig. 9 is a schematic diagram of a wafer substrate layout provided in this specification with open circuit anomalies.

As can be seen from fig. 9, it can be determined that, according to the position of each abnormal basic unit in the corresponding wafer substrate layout, in the second layer rewiring layer of the wafer substrate, the metal line at the upper right corner of the wafer substrate is not connected with the via hole, so that an open circuit abnormality exists in the wafer substrate, that is, the hatched area at the upper right corner in fig. 9 is not connected with the via hole represented by the triangle, so that an open circuit abnormality exists in the wafer substrate, and that five target connection networks with function identifier V1 exist in each determined target connection network, and one target connection network with identifier type that is not of the specified type (that is, the connection network 15).

In addition, the server may determine, for each target connection network, a connection network corresponding to the target connection network in each connection network of the schematic diagram, as a base connection network corresponding to the target connection network, determine whether a function identifier of the target connection network is identical to a function identifier of the base connection network corresponding to the target connection network, and if not, determine that there is a short circuit abnormality when preparing the wafer substrate according to the wafer substrate layout.

For example: in fig. 8, there is a target connection network for grounding and for supplying power at the same time, because there is a short circuit fault in the wafer substrate of the wafer substrate layout design, so that there is a connection relationship between the target connection network corresponding to the micro bump for supplying power and the target connection network corresponding to the micro bump for grounding, and thus the two target connection networks become one connection network (i.e. one target connection network is used for grounding and for supplying power at the same time), as shown in fig. 10.

Fig. 10 is a schematic diagram of a wafer substrate layout provided in the present specification with short circuit anomalies.

As can be seen from fig. 10, in the first layer of rewiring layers of the wafer substrate, vias for grounding (i.e., vias represented by squares in fig. 10) and vias for power supply (i.e., vias represented by circles in fig. 10) in the first layer of vias are connected together, thereby forming a short circuit.

Further, the server may determine each sub-target connection network according to the position distribution of each basic unit set in each layer structure of the wafer substrate in the layer structure and according to the preset superposition relationship between each layer structure of the wafer substrate, where, for each layer structure of the wafer substrate, the connection network formed by the connection relationship between each basic unit in the wafer substrate layout is used as each sub-target connection network when the micro-bump of the abnormal connection network is connected with the corresponding basic unit in the layer structure.

For example: the connection network for grounding is assumed to be composed of micro bumps for grounding, through holes in a first layer of through hole layers, metal wires in a first layer of rerouting layer, through holes in a second layer of through hole layers, metal wires in a second layer of rerouting layer, through holes in a through silicon hole layer, micro pads for grounding in a micro pad array layer, at this time, the corresponding sub-connection network under the micro pad array layer is composed of micro bumps for grounding in the micro pad array layer, the corresponding sub-connection network under the first layer of through hole layers is composed of micro bumps for grounding in the micro pad array layer, through holes in the first layer of through hole layers, which have connection relation with the micro bumps for grounding in the micro pad array layer, the corresponding sub-connection network under the first layer of rerouting layer is composed of micro bumps for grounding in the micro pad array layer, through holes in the first layer of through hole layers, which have connection relation with the micro bumps for grounding in the micro pad array layer, and so on.

Further, the server may determine, for each layer structure of the wafer substrate, whether there is an abnormality in preparing the layer structure according to the wafer substrate layout corresponding to the layer structure according to whether there is a difference between the sub-target connection network corresponding to the layer structure of the wafer substrate in the wafer substrate layout and the sub-connection network corresponding to the layer structure of the wafer substrate in the schematic diagram, as shown in fig. 11 and fig. 12.

Fig. 11 is a schematic diagram of a sub-connection network corresponding to a wafer substrate under a first redistribution layer in the schematic diagram provided in the present specification.

As can be seen from fig. 11, the corresponding sub-connection networks of the wafer substrate under the first redistribution layer in the schematic diagram have 21 connection networks, namely sub-connection networks 1 and 2 for transmitting clock signals, sub-connection networks 3 and 4 for transmitting different configuration signals, sub-connection networks 5 to 12 for grounding (here eight grounded sub-connection networks since eight micro bumps for grounding are not yet connected together in this layer structure), sub-connection networks 13, 14, 15, 16 for transmitting different transmission signals, and sub-connection networks 17, 18, 19, 20, 21 for supplying power.

Fig. 12 is a schematic diagram of a sub-connection network corresponding to a wafer substrate under a first rewiring layer in the wafer substrate layout provided in the present specification.

As can be seen from fig. 12, in the wafer substrate layout, there are 20 connection networks for the corresponding sub-target connection network of the wafer substrate under the first layer rerouting layer, respectively sub-target connection networks 1 and 2 for transmitting clock signals, sub-target connection networks 3 and 4 for transmitting different configuration signals, sub-target connection network 5 for grounding and for supplying power (i.e. connection network with short circuit), sub-target connection networks 6 to 12 for grounding, sub-target connection networks 13, 14, 15, 16 for transmitting different transmission signals, sub-target connection networks 17, 18, 19, 20 for supplying power.

As can be seen from the above, since there is a short-circuit abnormality in the first layer rerouting layer, there is a connection relationship between the sub-connection network for power supply and the sub-connection network for ground in the layer, and thus the number of extracted sub-target connection networks and the function identification of each sub-target network are inconsistent with the number of sub-connection networks and the function identification of each sub-connection network in the schematic diagram, so that it can be determined that there is an abnormality in the layer structure.

By the method, the layer-by-layer detection can be performed on each layer of structure of the wafer substrate, so that whether the wafer substrate layout corresponding to each layer of structure of the wafer substrate has short circuit abnormality or not can be determined.

Further, the server can obtain the position distribution of each basic unit arranged in the layer structure in the wafer substrate layout, and determine the position of the prepared wafer substrate with short circuit abnormality in the wafer substrate layout according to the position distribution of each basic unit arranged in the layer structure in the wafer substrate layout.

From the above, it can be seen that, the server not only can analyze each target connection network of the wafer substrate composed of each basic unit according to the position distribution of each basic unit in each layer structure of the wafer substrate in the layer structure and according to the preset superposition relationship between each layer structure of the wafer substrate, so as to compare each target connection network obtained by analyzing the wafer substrate layout with each connection network in the schematic diagram of the wafer substrate designed by the developer, to determine whether there is an abnormality when preparing the wafer substrate according to the wafer substrate layout, but also can analyze each layer structure of the wafer substrate layer by layer to determine which layer structure of the wafer substrate corresponds to the wafer substrate layout has an abnormality, and further can effectively detect whether there is an error in the wafer substrate layout.

The foregoing provides an abnormality detection method for one or more embodiments of the present disclosure, and based on the same concept, the present disclosure further provides a corresponding abnormality detection device, as shown in fig. 13.

Fig. 13 is a schematic diagram of an abnormality detection device provided in the present specification, including:

the obtaining module 1301 is configured to obtain a wafer substrate layout of each layer structure of a wafer substrate, and obtain a schematic diagram of the wafer substrate, where for each layer structure of the wafer substrate, the wafer substrate layout includes a position distribution of each basic unit disposed in the layer structure, where the basic unit includes: at least one of metal lines, vias, through silicon vias, micro bumps, and micro pads;

a determining module 1302, configured to determine, according to the wafer substrate layout, a position distribution of each basic unit set in each layer structure of the wafer substrate in the layer structure, and determine, according to a position distribution of each basic unit set in each layer structure of the wafer substrate in the layer structure and according to a preset stacking relationship between each layer structure of the wafer substrate, each connection network formed by a connection relationship between each basic unit in the wafer substrate layout when each micro bump included in a micro bump array layer is connected to a corresponding micro pad in a micro pad array layer, as each target connection network, where the micro bump and the micro pad are connected through each basic unit;

The detecting module 1303 is configured to determine whether an abnormality exists when the wafer substrate is prepared according to the wafer substrate layout according to whether a difference exists between each connection network of the wafer substrate and each target connection network in the schematic diagram.

Optionally, the obtaining module 1301 is specifically configured to obtain a wafer substrate layout of each layer structure of the wafer substrate, determine a function identifier corresponding to each micro bump of the micro bump array layer in the wafer substrate layout, and determine a function identifier corresponding to each micro pad of the micro pad array layer in the wafer substrate layout.

Optionally, the detecting module 1303 is specifically configured to determine whether the number of the target connection networks exceeds the number of the connection networks of the wafer substrate in the schematic diagram; if yes, determining that open circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout.

Optionally, the detecting module 1303 is specifically configured to obtain a function identifier of each target connection network, and determine whether there is a target connection network in the target connection networks, where an identifier type corresponding to the function identifier is not a specified type; if yes, determining that open circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout.

Optionally, the detecting module 1303 is specifically configured to determine, from the target connection networks, a target connection network inconsistent with each connection network of the wafer substrate as an abnormal connection network by comparing each target connection network with each connection network of the wafer substrate in the schematic diagram; determining each basic unit related to the abnormal connection network from each basic unit of the wafer substrate as an abnormal basic unit; and determining the position of the open circuit abnormality of the prepared wafer substrate in the wafer substrate layout according to the position distribution of each abnormal basic unit in the wafer substrate layout where the abnormal basic unit is located.

Optionally, the detecting module 1303 is specifically configured to determine, for each target connection network, a connection network corresponding to the target connection network in the connection networks of the schematic diagram, as a base connection network corresponding to the target connection network; judging whether the function identifier of the target connection network is consistent with the function identifier of the basic connection network corresponding to the target connection network; if not, determining that the short circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout.

Optionally, the detecting module 1303 is specifically configured to determine each sub-target connection network according to a position distribution of each basic unit set in each layer structure of the wafer substrate in the layer structure and according to a preset superposition relationship between each layer structure of the wafer substrate, where, for each layer structure of the wafer substrate, each connection network formed by connection relationships between each basic unit in the wafer substrate layout when a micro bump of the abnormal connection network is connected with a corresponding basic unit in the layer structure is used as each sub-target connection network; and determining whether the wafer substrate layout corresponding to the layer structure is abnormal or not according to whether the sub-target connection network corresponding to the wafer substrate under the layer structure in the wafer substrate layout is different from the sub-connection network corresponding to the wafer substrate under the layer structure in the schematic diagram aiming at each layer structure of the wafer substrate.

Optionally, the detecting module 1303 is specifically configured to obtain a position distribution of each basic unit disposed in the layer structure in the wafer substrate layout in the layer structure; and determining the position of the prepared wafer substrate with short circuit abnormality in the wafer substrate layout according to the position distribution of each basic unit arranged in the layer structure in the wafer substrate layout.

Optionally, the connection network includes: the connection network includes: at least one of a power supply network, a ground network, a configuration network, a clock network, and a signal transmission network.

The present specification also provides a computer readable storage medium having stored thereon a computer program operable to perform a method of one of the methods provided in fig. 1 above.

The present specification also provides a schematic structural diagram of an electronic device corresponding to fig. 1 shown in fig. 14. As shown in fig. 14, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a nonvolatile storage, and may of course include hardware required by other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs to implement the method described above with respect to fig. 1.

Of course, other implementations, such as logic devices or combinations of hardware and software, are not excluded from the present description, that is, the execution subject of the following processing flows is not limited to each logic unit, but may be hardware or logic devices.

In the 90 s of the 20 th century, improvements to one technology could clearly be distinguished as improvements in hardware (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) or software (improvements to the process flow). However, with the development of technology, many improvements of the current method flows can be regarded as direct improvements of hardware circuit structures. Designers almost always obtain corresponding hardware circuit structures by programming improved method flows into hardware circuits. Therefore, an improvement of a method flow cannot be said to be realized by a hardware entity module. For example, a programmable logic device (Programmable Logic Device, PLD) (e.g., field programmable gate array (Field Programmable Gate Array, FPGA)) is an integrated circuit whose logic function is determined by the programming of the device by a user. A designer programs to "integrate" a digital system onto a PLD without requiring the chip manufacturer to design and fabricate application-specific integrated circuit chips. Moreover, nowadays, instead of manually manufacturing integrated circuit chips, such programming is mostly implemented by using "logic compiler" software, which is similar to the software compiler used in program development and writing, and the original code before the compiling is also written in a specific programming language, which is called hardware description language (Hardware Description Language, HDL), but not just one of the hdds, but a plurality of kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), lava, lola, myHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog are currently most commonly used. It will also be apparent to those skilled in the art that a hardware circuit implementing the logic method flow can be readily obtained by merely slightly programming the method flow into an integrated circuit using several of the hardware description languages described above.

The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic controllers, and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller may thus be regarded as a kind of hardware component, and means for performing various functions included therein may also be regarded as structures within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.

The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of each element may be implemented in one or more software and/or hardware elements when implemented in the present specification.

It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present description is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.

The foregoing is merely exemplary of the present disclosure and is not intended to limit the disclosure. Various modifications and alterations to this specification will become apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, or the like, which are within the spirit and principles of the present description, are intended to be included within the scope of the claims of the present description.

Claims

1. An anomaly detection method, wherein the method is applied to a wafer substrate, the wafer substrate comprising: the micro-bump array layer, the micro-pad array layer, the rewiring layer, the via hole layer and the silicon through hole layer, wherein micro-bumps for realizing different functions contained in the micro-bump array layer are connected with micro-pads with corresponding functions in the micro-pad array layer through the rewiring layer, the via hole layer and the silicon through hole layer, and the method comprises the following steps:

Determining whether an abnormality exists when preparing the wafer substrate according to the wafer substrate layout according to whether a difference exists between each connecting network of the wafer substrate and each target connecting network in the schematic diagram, wherein, for each target connecting network, determining the connecting network corresponding to the target connecting network in each connecting network of the schematic diagram as a basic connecting network corresponding to the target connecting network, judging whether the functional identifier of the target connecting network is consistent with the functional identifier of the basic connecting network corresponding to the target connecting network, if not, determining that a short circuit abnormality exists when preparing the wafer substrate according to the wafer substrate layout; and

determining each sub-target connection network according to the position distribution of each basic unit in each layer structure of the wafer substrate in the layer structure and according to the superposition relation between each layer structure of the wafer substrate, wherein each connection network formed by the connection relation between each basic unit in the wafer substrate layout is used as each sub-target connection network when the micro-convex points of the abnormal connection network are connected with the corresponding basic units in the layer structure of the wafer substrate;

And determining whether the wafer substrate layout corresponding to the layer structure is abnormal or not according to whether the sub-target connection network corresponding to the wafer substrate under the layer structure in the wafer substrate layout is different from the sub-connection network corresponding to the wafer substrate under the layer structure in the schematic diagram aiming at each layer structure of the wafer substrate.

2. The method according to claim 1, wherein obtaining a wafer substrate layout of each layer structure of the wafer substrate specifically comprises:

3. The method according to claim 1, wherein determining whether there is an abnormality in preparing the wafer substrate according to the wafer substrate layout according to whether there is a difference between each connection network of the wafer substrate and each target connection network in the schematic diagram, specifically comprises:

4. A method as claimed in claim 3, wherein the method further comprises:

5. A method as claimed in claim 3, wherein the method further comprises:

determining target connection networks inconsistent with all connection networks of the wafer substrate from all the target connection networks as abnormal connection networks by comparing all the target connection networks with all the connection networks of the wafer substrate in the schematic diagram;

and determining the position of the open circuit abnormality of the prepared wafer substrate in the wafer substrate layout according to the position distribution of each abnormal basic unit in the wafer substrate layout where the abnormal basic unit is located.

6. The method of claim 1, wherein the method further comprises:

7. The method of claim 1, wherein the connecting network comprises: at least one of a power supply network, a ground network, a configuration network, a clock network, and a signal transmission network.

8. An abnormality detection apparatus, comprising:

The detection module is used for determining whether an abnormality exists when the wafer substrate is prepared according to the wafer substrate layout according to whether the difference exists between each connecting network of the wafer substrate and each target connecting network in the schematic diagram, wherein the connecting network corresponding to the target connecting network in each connecting network of the schematic diagram is determined as a basic connecting network corresponding to the target connecting network, whether the function identifier of the target connecting network is consistent with the function identifier of the basic connecting network corresponding to the target connecting network or not is determined, if the function identifier of the target connecting network is consistent with the function identifier of the basic connecting network corresponding to the target connecting network, the situation that a short circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout is determined, and the sub-target connecting networks are determined according to the position distribution of each basic unit arranged in each layer structure of the wafer substrate and the superposition relation between each layer structure of the wafer substrate, wherein the micro-salient points of the abnormal connecting network are connected with the basic units in the layer structure of the wafer substrate when the micro-salient points are connected with the basic units corresponding to each layer structure, and the connection relation between the basic units in the wafer substrate is formed as the sub-target connecting networks; and determining whether the wafer substrate layout corresponding to the layer structure is abnormal or not according to whether the sub-target connection network corresponding to the wafer substrate under the layer structure in the wafer substrate layout is different from the sub-connection network corresponding to the wafer substrate under the layer structure in the schematic diagram aiming at each layer structure of the wafer substrate.

9. The apparatus of claim 8, wherein the obtaining module is specifically configured to obtain a wafer substrate layout of each layer structure of the wafer substrate, determine a function identifier corresponding to each micro bump of the micro bump array layer in the wafer substrate layout, and determine a function identifier corresponding to each micro pad of the micro pad array layer in the wafer substrate layout.

10. The apparatus of claim 8, wherein the detection module is specifically configured to determine whether the number of target connection networks exceeds the number of connection networks of the wafer substrate in the schematic diagram; if yes, determining that open circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout.

11. The apparatus of claim 8, wherein the detection module is specifically configured to obtain a function identifier of each target connection network, and determine whether there is a target connection network in the target connection networks, where an identifier type corresponding to the function identifier is not a specified type; if yes, determining that open circuit abnormality exists when the wafer substrate is prepared according to the wafer substrate layout.

12. A computer-readable storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method of any of the preceding claims 1-7.

13. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any of the preceding claims 1-7 when executing the program.