TWI348820B - Output buffer circuit - Google Patents

Output buffer circuit

Info

Publication number
TWI348820B
TWI348820B TW096124438A TW96124438A TWI348820B TW I348820 B TWI348820 B TW I348820B TW 096124438 A TW096124438 A TW 096124438A TW 96124438 A TW96124438 A TW 96124438A TW I348820 B TWI348820 B TW I348820B
Authority
TW
Taiwan
Prior art keywords
output buffer
buffer circuit
circuit
output
buffer
Prior art date
Application number
TW096124438A
Other languages
English (en)
Other versions
TW200814528A (en
Inventor
Hiroshi Miyazaki
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of TW200814528A publication Critical patent/TW200814528A/zh
Application granted granted Critical
Publication of TWI348820B publication Critical patent/TWI348820B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
TW096124438A 2006-07-31 2007-07-05 Output buffer circuit TWI348820B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006208602A JP4978094B2 (ja) 2006-07-31 2006-07-31 出力バッファ回路

Publications (2)

Publication Number Publication Date
TW200814528A TW200814528A (en) 2008-03-16
TWI348820B true TWI348820B (en) 2011-09-11

Family

ID=38985543

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096124438A TWI348820B (en) 2006-07-31 2007-07-05 Output buffer circuit

Country Status (5)

Country Link
US (1) US7724062B2 (zh)
JP (1) JP4978094B2 (zh)
KR (1) KR100895657B1 (zh)
CN (1) CN101119114B (zh)
TW (1) TWI348820B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5115275B2 (ja) * 2008-03-31 2013-01-09 富士通セミコンダクター株式会社 出力バッファ回路
JP5560682B2 (ja) * 2009-12-08 2014-07-30 株式会社リコー スイッチングレギュレータ
CN101951246B (zh) * 2010-07-05 2012-09-05 清华大学 静态电压电平恢复器
US8648583B2 (en) * 2010-10-29 2014-02-11 R2 Semiconductor, Inc. Delay block for controlling a dead time of a switching voltage regulator
TW201242251A (en) * 2011-04-15 2012-10-16 Novatek Microelectronics Corp Output buffer
CN105207658B (zh) * 2014-06-11 2018-03-27 华邦电子股份有限公司 输出缓冲器
CN107204768A (zh) * 2017-06-12 2017-09-26 成都锐成芯微科技股份有限公司 高压差电平转换电路及方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4622482A (en) * 1985-08-30 1986-11-11 Motorola, Inc. Slew rate limited driver circuit which minimizes crossover distortion
US5606275A (en) * 1995-09-05 1997-02-25 Motorola, Inc. Buffer circuit having variable output impedance
JP2891920B2 (ja) 1996-02-21 1999-05-17 山形日本電気株式会社 出力バッファ回路
JPH10285013A (ja) 1997-04-08 1998-10-23 Mitsubishi Electric Corp 出力バッファ回路
WO1998051012A1 (en) * 1997-05-01 1998-11-12 Mitsubishi Denki Kabushiki Kaisha Output buffer circuit
US6181542B1 (en) * 1998-12-21 2001-01-30 Taiwan Semiconductor Manufacturing Company Method of making a stack-polysilicon capacitor-coupled dual power supply input/output protection circuit
JP2001144600A (ja) * 1999-11-17 2001-05-25 Nec Corp 多電源対応の半導体集積回路用入出力バッファ
JP2002280893A (ja) * 2001-03-21 2002-09-27 Ricoh Co Ltd 半導体装置
JP2003133938A (ja) * 2001-10-26 2003-05-09 Mitsubishi Electric Corp 出力回路
JP3980383B2 (ja) * 2002-03-18 2007-09-26 株式会社ルネサステクノロジ 半導体集積回路装置
KR100475054B1 (ko) * 2002-05-09 2005-03-10 삼성전자주식회사 비트 구성에 상관없이 데이터 출력시간이 일정한 동기식반도체 장치 및 데이터 출력시간 조절 방법
JP2005079763A (ja) * 2003-08-29 2005-03-24 Toshiba Corp 半導体装置
JP3984222B2 (ja) * 2003-12-15 2007-10-03 株式会社東芝 信号レベル変換回路
JP4492852B2 (ja) * 2004-03-30 2010-06-30 株式会社ルネサステクノロジ 半導体集積回路装置
JP4089704B2 (ja) * 2005-06-13 2008-05-28 セイコーエプソン株式会社 半導体集積回路
JP4158787B2 (ja) * 2005-06-14 2008-10-01 セイコーエプソン株式会社 半導体集積回路
JP4769108B2 (ja) * 2006-03-29 2011-09-07 川崎マイクロエレクトロニクス株式会社 出力バッファ回路
US7646233B2 (en) * 2006-05-11 2010-01-12 Dsm Solutions, Inc. Level shifting circuit having junction field effect transistors
US7468615B1 (en) * 2007-03-28 2008-12-23 Xilinx, Inc. Voltage level shifter

Also Published As

Publication number Publication date
US7724062B2 (en) 2010-05-25
KR20080012164A (ko) 2008-02-11
KR100895657B1 (ko) 2009-05-07
JP4978094B2 (ja) 2012-07-18
US20080024189A1 (en) 2008-01-31
CN101119114A (zh) 2008-02-06
CN101119114B (zh) 2010-09-22
JP2008035385A (ja) 2008-02-14
TW200814528A (en) 2008-03-16

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees