TWI347632B - - Google Patents
Info
- Publication number
- TWI347632B TWI347632B TW096110835A TW96110835A TWI347632B TW I347632 B TWI347632 B TW I347632B TW 096110835 A TW096110835 A TW 096110835A TW 96110835 A TW96110835 A TW 96110835A TW I347632 B TWI347632 B TW I347632B
- Authority
- TW
- Taiwan
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/80—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006108940 | 2006-04-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200802536A TW200802536A (en) | 2008-01-01 |
TWI347632B true TWI347632B (zh) | 2011-08-21 |
Family
ID=38575720
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096110835A TW200802536A (en) | 2006-04-11 | 2007-03-28 | Method of manufacturing semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (2) | US8158333B2 (zh) |
KR (1) | KR100847951B1 (zh) |
CN (1) | CN100499023C (zh) |
TW (1) | TW200802536A (zh) |
Families Citing this family (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8852851B2 (en) | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
JP4996155B2 (ja) * | 2006-07-18 | 2012-08-08 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7521371B2 (en) * | 2006-08-21 | 2009-04-21 | Micron Technology, Inc. | Methods of forming semiconductor constructions having lines |
US8072601B2 (en) * | 2007-02-28 | 2011-12-06 | Kabushiki Kaisha Toshiba | Pattern monitor mark and monitoring method suitable for micropattern |
US7790360B2 (en) * | 2007-03-05 | 2010-09-07 | Micron Technology, Inc. | Methods of forming multiple lines |
JP2008233383A (ja) * | 2007-03-19 | 2008-10-02 | Toshiba Corp | パターン作成方法、パターン作成プログラム、マスクの製造方法、および半導体装置の製造方法 |
KR100880323B1 (ko) * | 2007-05-11 | 2009-01-28 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
JP2009049338A (ja) * | 2007-08-23 | 2009-03-05 | Toshiba Corp | 半導体装置及びその製造方法 |
US7989307B2 (en) | 2008-05-05 | 2011-08-02 | Micron Technology, Inc. | Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same |
US10151981B2 (en) | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
JP2009295785A (ja) * | 2008-06-05 | 2009-12-17 | Toshiba Corp | 半導体装置の製造方法 |
KR101435520B1 (ko) | 2008-08-11 | 2014-09-01 | 삼성전자주식회사 | 반도체 소자 및 반도체 소자의 패턴 형성 방법 |
JP2010087298A (ja) * | 2008-09-30 | 2010-04-15 | Toshiba Corp | 半導体装置の製造方法 |
JP2010087301A (ja) | 2008-09-30 | 2010-04-15 | Toshiba Corp | 半導体装置の製造方法 |
JP2010087300A (ja) * | 2008-09-30 | 2010-04-15 | Toshiba Corp | 半導体装置の製造方法 |
KR101540083B1 (ko) * | 2008-10-22 | 2015-07-30 | 삼성전자주식회사 | 반도체 소자의 패턴 형성 방법 |
US8273634B2 (en) | 2008-12-04 | 2012-09-25 | Micron Technology, Inc. | Methods of fabricating substrates |
US8247302B2 (en) | 2008-12-04 | 2012-08-21 | Micron Technology, Inc. | Methods of fabricating substrates |
US8796155B2 (en) | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
US8138092B2 (en) * | 2009-01-09 | 2012-03-20 | Lam Research Corporation | Spacer formation for array double patterning |
KR20100083581A (ko) * | 2009-01-14 | 2010-07-22 | 삼성전자주식회사 | 반도체 소자의 형성방법 |
JP5532611B2 (ja) * | 2009-01-23 | 2014-06-25 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法及び設計支援装置 |
US8268543B2 (en) | 2009-03-23 | 2012-09-18 | Micron Technology, Inc. | Methods of forming patterns on substrates |
US9330934B2 (en) | 2009-05-18 | 2016-05-03 | Micron Technology, Inc. | Methods of forming patterns on substrates |
KR20100126998A (ko) * | 2009-05-25 | 2010-12-03 | 삼성전자주식회사 | 라인 및 스페이스 패턴의 형성 방법 |
KR20110001292A (ko) | 2009-06-30 | 2011-01-06 | 삼성전자주식회사 | 패턴 구조물 및 이의 형성 방법 |
US7972926B2 (en) | 2009-07-02 | 2011-07-05 | Micron Technology, Inc. | Methods of forming memory cells; and methods of forming vertical structures |
CN102024821B (zh) * | 2009-09-18 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | 非易失性存储装置、非易失性存储器件及其制造方法 |
NL2006655A (en) * | 2010-06-28 | 2011-12-29 | Asml Netherlands Bv | Multiple patterning lithography using spacer and self-aligned assist patterns. |
DE102010040066B4 (de) * | 2010-08-31 | 2012-05-24 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung von Gateelektroden eines Halbleiterbauelements, die durch eine Hartmaske und Doppelbelichtung in Verbindung mit einem Größenreduzierungsabstandshalter hergestellt sind |
US8455341B2 (en) * | 2010-09-02 | 2013-06-04 | Micron Technology, Inc. | Methods of forming features of integrated circuitry |
KR101083918B1 (ko) * | 2010-12-15 | 2011-11-15 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 제조 방법 |
FR2972293A1 (fr) * | 2011-03-04 | 2012-09-07 | St Microelectronics Crolles 2 | Procédé de fabrication d'un circuit intégré sur la formation de lignes et de tranches |
JP5330440B2 (ja) * | 2011-03-23 | 2013-10-30 | 株式会社東芝 | 半導体装置の製造方法 |
US8575032B2 (en) | 2011-05-05 | 2013-11-05 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
JP5606388B2 (ja) | 2011-05-13 | 2014-10-15 | 株式会社東芝 | パターン形成方法 |
JP5659135B2 (ja) | 2011-12-19 | 2015-01-28 | 株式会社東芝 | パターン形成方法 |
US9177794B2 (en) | 2012-01-13 | 2015-11-03 | Micron Technology, Inc. | Methods of patterning substrates |
US8697537B2 (en) * | 2012-02-01 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of patterning for a semiconductor device |
US8629048B1 (en) | 2012-07-06 | 2014-01-14 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
US8980762B2 (en) * | 2012-08-31 | 2015-03-17 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
JP2014053436A (ja) | 2012-09-06 | 2014-03-20 | Toshiba Corp | 半導体記憶装置の製造方法 |
JP2014053565A (ja) | 2012-09-10 | 2014-03-20 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
US9099532B2 (en) | 2012-09-14 | 2015-08-04 | Sandisk Technologies Inc. | Processes for NAND flash memory fabrication |
US8987142B2 (en) * | 2013-01-09 | 2015-03-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-patterning method and device formed by the method |
CN104425220A (zh) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | 图案的形成方法 |
US9121890B2 (en) * | 2013-10-30 | 2015-09-01 | Globalfoundries Inc. | Planar metrology pad adjacent a set of fins of a fin field effect transistor device |
US10163652B2 (en) | 2014-03-13 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming patterns using multiple lithography processes |
US9390922B1 (en) | 2015-02-06 | 2016-07-12 | Sandisk Technologies Llc | Process for forming wide and narrow conductive lines |
US9425047B1 (en) | 2015-02-19 | 2016-08-23 | Sandisk Technologies Llc | Self-aligned process using variable-fluidity material |
US9502428B1 (en) | 2015-04-29 | 2016-11-22 | Sandisk Technologies Llc | Sidewall assisted process for wide and narrow line formation |
US9595444B2 (en) | 2015-05-14 | 2017-03-14 | Sandisk Technologies Llc | Floating gate separation in NAND flash memory |
KR102607278B1 (ko) * | 2016-04-28 | 2023-11-30 | 삼성전자주식회사 | 반도체 소자의 패턴 형성 방법 |
EP3419047A1 (en) * | 2017-06-22 | 2018-12-26 | IMEC vzw | A method for patterning a target layer |
CN109950246A (zh) * | 2017-12-21 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
CN109994482B (zh) * | 2017-12-29 | 2021-03-16 | 中芯国际集成电路制造(上海)有限公司 | 一种nand器件及其制作方法、电子装置 |
KR102391433B1 (ko) * | 2018-02-02 | 2022-04-27 | 주식회사 디비하이텍 | 비휘발성 메모리 소자용 게이트 구조물의 형성 방법 |
US10446395B1 (en) * | 2018-04-11 | 2019-10-15 | Globalfoundries Inc. | Self-aligned multiple patterning processes with layered mandrels |
KR20210001109A (ko) | 2019-06-26 | 2021-01-06 | 삼성전자주식회사 | 패턴 형성 방법과 집적회로 소자 및 그 제조 방법 |
CN111106001A (zh) * | 2019-12-19 | 2020-05-05 | 上海华力微电子有限公司 | Nand存储器的栅极结构形成方法、nand存储器及光罩掩膜版 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5328810A (en) | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
US6063688A (en) * | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
US6187694B1 (en) * | 1997-11-10 | 2001-02-13 | Intel Corporation | Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer |
KR100354440B1 (ko) * | 2000-12-04 | 2002-09-28 | 삼성전자 주식회사 | 반도체 장치의 패턴 형성 방법 |
KR20030002145A (ko) * | 2001-06-30 | 2003-01-08 | 주식회사 하이닉스반도체 | 반도체소자의 패턴 형성 방법 |
KR20050068363A (ko) * | 2003-12-30 | 2005-07-05 | 주식회사 하이닉스반도체 | 하드 마스크를 이용한 미세 패턴 형성 방법 |
JP4936659B2 (ja) | 2004-12-27 | 2012-05-23 | 株式会社東芝 | 半導体装置の製造方法 |
JP4921723B2 (ja) * | 2005-04-18 | 2012-04-25 | 株式会社東芝 | 半導体装置の製造方法 |
JP2006351861A (ja) * | 2005-06-16 | 2006-12-28 | Toshiba Corp | 半導体装置の製造方法 |
-
2007
- 2007-03-27 US US11/727,537 patent/US8158333B2/en active Active
- 2007-03-28 TW TW096110835A patent/TW200802536A/zh not_active IP Right Cessation
- 2007-04-10 KR KR1020070035088A patent/KR100847951B1/ko not_active IP Right Cessation
- 2007-04-11 CN CNB200710091164XA patent/CN100499023C/zh not_active Expired - Fee Related
-
2010
- 2010-05-11 US US12/662,910 patent/US8497060B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
TW200802536A (en) | 2008-01-01 |
KR20070101155A (ko) | 2007-10-16 |
CN100499023C (zh) | 2009-06-10 |
KR100847951B1 (ko) | 2008-07-22 |
US8158333B2 (en) | 2012-04-17 |
US20100221665A1 (en) | 2010-09-02 |
CN101055837A (zh) | 2007-10-17 |
US20070238053A1 (en) | 2007-10-11 |
US8497060B2 (en) | 2013-07-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |