TWI344191B - Semiconductor device having electrical contact from opposite sides and method therefor - Google Patents

Semiconductor device having electrical contact from opposite sides and method therefor Download PDF

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Publication number
TWI344191B
TWI344191B TW093123127A TW93123127A TWI344191B TW I344191 B TWI344191 B TW I344191B TW 093123127 A TW093123127 A TW 093123127A TW 93123127 A TW93123127 A TW 93123127A TW I344191 B TWI344191 B TW I344191B
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Taiwan
Prior art keywords
layer
electrode
semiconductor device
transistor
conductive
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TW093123127A
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English (en)
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TW200511500A (en
Inventor
Hector Sanchez
Michael A Mendicino
Byoung W Min
Kathleen C Yu
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Freescale Semiconductor Inc
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Publication of TW200511500A publication Critical patent/TW200511500A/zh
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Publication of TWI344191B publication Critical patent/TWI344191B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Description

1344191 九、發明說明： 【發明所屬之技術領域】 本發明大體而言係關於積體電路，且更具體言之，本發 明係關於建立到半導體電路元件的電氣接觸。 【先前技術】 目前，半導體利用使用電晶體閘建置而成的解耦電容 器。在一積體電路之内部供給中，當發生大量的開關活動 夺需要解搞電谷器來阻止電屋下降。然而，技術的進展 要求使用會導致不理想的閘極電容器電流泄漏之薄的閘極 氧化物。此外，此等電容器消耗了有用的電路佈局區域， 且因此該等電容器之使用是受到限制的。閘極電容器之電 流泄漏亦導致在低功率應用中至關重要的功率消耗浪費。 泄漏可以在以總解耦電容及加工複雜度為代價的情況下得 到減輕。由於解耦電容器與主動電路之間的遠距離，所以 解麵電容器的高頻響應受到限制。因為解耦電容器的放置 受到限制，所以該距離必定很遠，且通常解耦電容器之放 置比所期望的更遠離主動電路。因此，現有的解耦電容器 結構受到功率消耗問題、尺寸問題及/或電效率之困擾。 【發明内容】 :一種半導體，其具有如-電晶體之主動裝置及直接位於 該主動裝置下方如一電容器之被動裝置，肖主動裝置與該 被動裝置藉由-通路或傳導區域及互連而相連。該通路或 傳導區域接觸電晶體之一擴散區域或源區㈣底表面且接 觸該等電容器電極之第一電極
% —橫向定位之垂直通路及 94915.doc 互連接觸該等電容器電極之k電極4屬互連或傳導材 料可用作-電源平面，藉由將該電源平面建構於電晶體下 方而非建構為鄰近該電晶體而得以節省電路面積。 【實施方式】 圖1所說明的係如本發明之—半導體卜應瞭解本文 中的術語"在.····.之上"、"上覆於”及"在上方"係針對相 對於本文中所討論之每—個圖的具體方位而形成的層及結 構來作出定義。例如，在圖1、2及19中，使用術語"在…… 之上"來指任何在所說明基板12之垂直上方之物。然而，圖 3-18之說明提供圖卜2及19之反轉的方位。儘管相對於圖 1及圖2之原先方位，該等結構實際上位於基板12之下方， 但是術語”在之上"將繼續用於討論。亦顯而易見的是半 導體裝置1G及其所有實施例不僅在所說明的方位可運作， 而且在所有的方位（不管為90、18〇度或任何其它方位）都可 運作。亦可對半導體裝置1G進行多種建構，其中各種裝置 之方位將變化…主動層16結合到絕緣層14上且位於基板 12之上。在一形態中，主動層16係由經結合的矽、GaAs (砷 化鎵）或SiGe(鍺化石夕）或其它+導體材料所形成的半導體 層基板12可藉由任何為半導體裝置10之元件及其形成提 供合適的機械支持之材料來加以建構。 本文將描述之主動裝置及接觸係利用習知的加工技術來 加以圖案化，且對其將不作具體詳細的討論。此等包括多 晶矽閘極18、側壁間隔器20、背面源極區域22、汲極區域 23、閉極接觸26'氧化物28、絕緣触刻擋止層3〇、氧化物 94915.doc 1344191 3 1及者面接觸32。閘極係一控制電極且源極及汲極係一電 曰a體之電流電極。源極區域22及汲極區域23分別係—擴散 區域且各自充當電晶體之第一電流電極及第二電流電極， 而閘極接觸26充當電晶體之控制電極。一汲極接觸33電連 接至汲極區域23。氡化物28係在半導體中使用之任何習知 氧化物材料之氧化物層。應瞭解一薄閘極氧化物（未圖示） 位於多晶矽閘極18之下。背面接觸32延伸穿過主動層丨6及 掩藏的絕緣層14 »應注意在其它實施例中，背面接觸3 2可 能未延伸超過氧化物31之底表面，使得背面接觸32與汲極 接觸3 3具有近似相同的深度。 一蝕刻擋止層34沈積於氧化物28、汲極接觸33及背面接 觸32之上。如圖所示，背面接觸32代表習知的金屬化且包 括成功沈積、金屬限制及可靠性所必需的層。背面接觸32 及汲極接觸33充當一通路或互連結構β 在一形態中，絕緣層14可用Si〇2 (二氧化矽）來建構，且 充當一用於基板12之隨後移除的蝕刻擋止件。此結構形成 一絕緣體上矽（SOI)結構。然而，應瞭解本文中所提供之結 構可藉由用一不包含絕緣層14或主動層丨6之表體基板而建 構。應注意的是背面接觸32若並未延伸至基板12，則至少 延伸至主動層16之較低表面或第一表面之平面。 圖2所說明之係半導體裝置1〇，其中一載體基板％藉由結 e層3 6連接至赛刻擋止層3 4。結合層36可包括諸如基於氧 化物或聚合物之結合（諸如BCB或聚醯亞胺）的材料。載體基 板38充當一機械支撐以允許隨後移除基板12及處理半導體 94915.doc 裝置10。顯而易見，載體基板38亦可具有主動電路且無需 作為隨後將要被移除的犧牲層。此外，可使用金屬—金屬 類型結合’其中不需要蝕刻擋止層34且在載體基板38與背 面接觸32、閘極接觸26及汲極接觸33之間存在直接連接。 圖3說明一半導體裝置10,其中原先的基板12已被移除β 此移除過程可包括習知技術，諸如研磨法、化學機械研磨 法（CMP)、對絕緣層14有選擇性的濕式或乾式蝕刻法。此 外’此移除方法可包括非接觸式移除技術諸如雷射擡離 (laser lift-〇ff)、黏合材料的分解、結合物的分解等等。假 設載體基板38提供機械支撐，則現在載體基板38成為用於 裝置處理之底表面。在結合及基板移除過程中，為了便於 背面加工，半導體裝置之方位已進行18〇度的翻轉。因此， 與圖2相比，半導體裝置1〇在圖3中是倒轉的。圖中示描緣 出與源極區域22之接觸，但其可藉由習知方法自頂面製成 或如本文中所教示自背面製成。 圖4所說明的為一半導體裝置1〇，其中光阻層42界定了與 背面接觸32及背面源區域22對齊之開口。或者，此等接觸 可連接至其它裝置特徵，諸如來自背面之汲極區域23、多 晶矽閘極18,或連接至諸如二極體之主動裝置（未圖示）或諸 如電阻器之被動裝置（未圖示）之任一元件，等等。如圖4所 說明之層40係一用於輔助精確圖案化之抗反射塗層（ARC) 或硬光罩。此層40視特徵尺寸及加工精度而定為可選的。 層40可導電或絕緣，但是若層4〇導電，則必須將該層自 半導體裝置1 〇之最終結構移除。 94915.doc 1344191 圖5所说明的為一半導體裝置丨〇，其中在光阻層42中所界 疋之圖案已藉由利用乾式抑或濕式蝕刻加工或其組合而轉 印至層40、14及16中。接著移除光阻層42且開口 44及開口 48依照圖案而產生。開口44界定一至背面源極區域22之接 觸區域。應注意為了轉送圖案而執行的姓刻過程受到控制 以在背面源極區域22上停止而不損耗該背面源極區域22之 顯著部分。然而，在另一實施例中，如圖5中藉由作為側面 邊界線之虛線加以說明，穿過開口 44之受控蚀刻延伸穿過 背面源極區域22之一部分或全部。在第一實施例中利用兩 步驟蝕刻處理。第一步驟為基於氧化物的蝕刻且第二步驟 為基於矽的蝕刻。該基於矽之蝕刻可實施為定時蝕刻。開 口 48界定一與背面接觸32相鄰之接觸區域。或者，開口 44 及開口 48能在單獨的圖案化及蝕刻步驟中加以界定。此 外，藉由過度蝕刻圖3中的層14使得背面接觸32凸出且與開 口 44之頂部平面共平面，可消除對開口 48之需求。亦可藉 由不利用可選層40來消除對開口 48之需求。而且，在圖5 之所說明形態中’接著移除光阻層42。在另一實施例中， 一個位於背面源極區域22上方且一個位於背面源極區域下 方的兩個垂直毗鄰的接觸（未圖示）可在背面源極區域22内 電接合’以便形成一與背面接觸32具有相同高度之接觸。 圖ό所說明的係一半導體裝置1〇，其中導電層5〇與背面接 觸32及背面源極區域22電氣接觸。此導電層5〇除了包括入 適的障壁材料以外’可包括銅、鎢、銀、金、鋁或其它導 ΟΑ 體0 94915.doc -10- 1344191 圖7所說明的係一半導體裝置10,其t導電層50藉由利用 CMP或電研磨法或其它習知技術而平面化。該平面化形成 具有不同高度之通路或傳導區域52及傳導區域54。主動層 16具有一第一表面及一相對的第二表面，其中背面源極區 域22在第一表面中形成。源極區域22具有一頂表面及一底 表面。傳導區域52在主動層16中形成且具有一形成於主動 層16之第二表面處的第一末端。傳導區域52具有一形成於 源極區域22之底表面中的第二末端。亦應注意的是若開口 48如上所述的被消除了，則接著不形成傳導區域54。應注 意的是尚度無需不同，因為背面接觸32可被蝕刻至一該等 高度大體相同的量。在界定了傳導區域54之場合下，傳導 區域54中之一個及背面接觸32中之一個分別形成通路％及 通路57。應瞭解在另一實施例中’用於傳導區域52之開口 可如圖7中虛線所說明被蝕刻穿過背面源極區域22。在該實 施例中，背面源極區域22完全環繞傳導區域52且傳導區域 52延伸穿過背面源極區域22至主動層16之第一表面。應觀 察到在加工過程中此點處為半導體裝置10提供一具有第一 表面及第二表面之半導體層》該第二表面與該第一表面相 對。呈背面源極區域22之形態之擴散區域形成於該半導體 層之第一表面處。該擴散區域具有位於半導體層之第一表 面處的頂表面及底表面。如由傳導區域52所代表之通路在 半導體層中形成。該通路之一部分具有形成於該第二表面 處或該第二表面上方（意即延伸至層40之内部）的第—末端 及形成於該擴散區域之底表面處或底表面下方的第二末端 949I5.doc
'V 'V1344191 (意即延伸至背面源極區域22之内部）β 圖8所說明的係半導體裝置1〇，其中將層58、6〇及62形成 為上覆於層40上。在一形態令，層58係一介電質且用作一 敍刻擋止層。層60充當一低κ(介電常數）介電質，其中"低 Κ”通常為4.0或更小。層62充當一抗反射塗層（ARC)材料或 一硬光罩材料，且可絕緣抑或導電。應瞭解層62係一可選 層。在一形態中，層58、60及62可由習知沈積技術而形成。 一經圖案化的光阻層64上覆於層62上，以供界定最接近一 裝置層之電極的位置以及界定背面之傳導路線。在一形態 47 ’該傳導路線係用於界定供電導體及接地導體或其它電 路路線。 圖9所*兑明的係半導體裝置1〇,其中由光阻層所界定之 圖案被轉印至層62、60及58中以形成開口 66。在一形態中， 可藉由習知的乾式或濕式蝕刻技術而實施該圖案轉印。 圖10所忒明的係半導體裝置丨〇，其中開口的藉由使用習 知沈積技術而填充有-充當第-金屬結構之傳導材料68。 在一形態中，該傳導材料68係金屬且形成一金屬結構。在 一形態中，傳導材料68可藉由銅、銀、鎢、鎳、金、鋁及 其合金以及其它金屬來建構。顯而易見，傳導區域52、傳 導區域54及傳導材料68可使用習知的雙嵌入(dual in-laid) 圖案化、蝕刻及填充技術而形成。 圖U所說明的係半導體裝置10 ’其中傳導材料68被平面 化以形成傳導材料68之隔離料。習知的平面化技則諸如 CMP)可用於實施此加工步驟。在—替代形態中，該平面化 94915.doc -12· 1344191 處理可移除傳導材料68的足夠部分使得層62亦被移除。應/ 觀察到在加工十的此點處提供了呈傳導材料68之形態的金’ ^ 屬結構，以用於為一將形成於閘電極丨8周圍之電晶體提供 回授偏壓（back bias)。在此形態'中，無需傳導區域52。對於 ’、 此實施例而言，期望層14及4〇之厚度最小化。 圖12所甙明之係半導體裝置10 ’其中一障壁層72上覆於 傳導材料68及層62上。在一形態中，障壁層η藉由一介電 質而建構。在其它形⑮中，障壁層72可藉由僅沈積於傳導 材料6 8之金屬區域上的傳導材料（即無電障壁）而建構。一氧 φ 化物層73上覆於障壁層72上。一解輕電容器之由傳導材料 75形成的第一平板電極上覆於該氧化物層乃上。該第一平 板電極傳導材料75係傳導性的且通常為諸如氮化鈕、鋁、 鈕、氮化鈦及其它之金屬。—絕緣層77上覆於該第一平板 電極傳導材料75上且較佳係-介電常數在4.G或更大之範 圍内的高k介電材料。由傳導材料79形成之第二平板電極上 覆於絕緣層77上。該第二平板電極傳導材料乃亦為一導 體。光阻81上覆於半導體裝置1G上且形成—圖案以自該第 一平板電極傳導材料75界定一第二平板電極。 圖13說明-半導體裝置1〇，其中該第二平板電極傳導材 料79係由一習知蝕刻加工而形成。 圖14說明半導體裝置10，纟中將氮化物層83形成為上覆 ‘ 於第二平板電極傳導材料79之頂部上以作為一蝕刻擋止 ， 層。光阻85界定第一電極層之圖案。 " , 如圖15所說明之，光阻85之圖案轉印至層73、刃及以及 94915.doc -13- 1344191
傳導材料75中。該圖案可使用一習知的乾式蝕刻或濕式蝕 刻或其組合來加以轉印且對蝕刻擋止或障壁層72具選擇 性。將光阻81自半導體裝置10移除。將充當絕緣層之隨後 的氧化物薄膜87沈積且平面化（在一形態中，一研磨過程） 以形成一平面的上表面。將硬光罩層89形成為上覆於該氧 化物薄膜87上。一光阻91為半導體裝置1〇界定通路開口， 以供獲取除了到傳導材料68外亦到第一及第二電容器平板 之接觸。應注意，由金屬結構或傳導材料75、絕緣層77及 金屬結構或傳導材料79形成之電容器之至少一部分係位於 一與主動層丨6之表面垂直且穿過主動裝置（由閘極18、源極 區域22及汲極區域23形成之電晶體）的線上。應瞭解視導電 性摻雜而定，源極區域22及汲極區域23建構為源極/汲極區 域抑或汲極/源極區域。
如圖16所說明，該等通路開口以穿通接觸通路ιΐ3、頂面 電極通路93、底面電極通路95及通路96之形態钱刻而成。 光阻97界定金屬開口。層89充當類似於層62之抗反射塗層 (ARC)材料或硬光罩材料。 如圖17所說明，由光阻層97所界定之圖案被轉印至層 及氧化物薄膜。在-形態中，可藉由習知的乾式敍 技術抑或濕式蝕刻技術來實施該圖案轉印。藉由使用習 的沈積技術，以充當第二金屬結構之傳導材料99填充 口。在一形態中，該傳導材料99係金屬且形成—金屬結構 在-形態中，傳導材料99可藉由銅、銀 ' 鶴、鎳、金°、< 及其合金以及其它金屬來建構。顯而易見，所說明之^ 94915.doc 14 中的傳導材料99可藉由使用與圖u類似之習知的雙嵌入圖 案化、姓刻、填充及平面化技術來形成。在圖丨7中，在傳 導材料99及層89上沈積一鈍化層1〇卜在一形態中，該鈍化 層101可為碳化物、氮化物、氧化物材料或其它介電材料。 在此實施例中，呈電晶體形態之主動裝置由多晶矽閘極 18及相關聯的閘極氧化物（未圖示）、背面源極區域22及汲極 區域23所形成。假定除了所說明之電晶體以外，還可使用 新穎的結構（諸如鰭狀場效電晶體（FinFET)或垂直電晶體） 來代替習知的金氧半場效電晶體。在主動裝置（意即所說明 之電晶體）之直接下方形成一呈電容元件（在一應用中充當 解耦電容器）之形態的被動裝置β該解耦電容器之一部分沿 -穿過電晶體之任一部分之線定位，纟中該線與主動層Μ 之一表面垂直。 圖18所說明之係半導體裝置1〇，其中最終基板料藉由一 結合層92接合至鈍化層10卜應瞭解多個傳導層（未圖示）可 將傳導材料68及鈍化層101分離。此外，可去除結合層％ 及最終基板94而由多個傳導層（未圖示）加以取代以形成一 傳導凸塊結構。在該實施例中，氡體基板％為最終基板。 圖咖說明之料導體裝置1G，其中移除了載/基㈣ 及結合層36。此移除過程可包括習知技術，諸如研磨、化 學機械研磨（CMP)、對㈣擋止層34有選擇性的濕、式或乾式 姓刻。此外，此移除過程可包括非接觸式移除技術，諸: 雷射擡離、黏合材料之分解、結合物之分解等等。因此最 終基板94成為半導體裝置Π)之最終基板1於金屬層形成 949l5.doc 15 1344191 及C4附著之進一步加工可依照習知加工技術來實施。 現在應瞭解已提供一種用於形成一半導體裝置之方法， 該半導體裝置中-被動裝置係形成為位於—主動裝置之直 接下方。在所說明之形態中，該被動裝置建構為一由分別 乍為第板電極及第二平板電極之傳導材料了5及傳導材 料79及作為插入介電質之層73所形成之電容器。電容器之 傳導材料79藉由由料㈣99及68及傳導區域⑽背面接 觸中之接觸所开〉成之互連而與正面接觸。電容器之傳 導材料75亦藉由傳導材料99、68及傳導區域52至背面源極 區域22而連接至電晶體（即主動裝置卜此外，傳導材料以 可建構為一穿過半導體晶粒之有效率的電源平面，以穿過 半導體裝置10分配電源供應電壓。該電源平面將直接向電 晶體提供電力而不具有會消耗電路佈局區域之橫向電源平 面此外，傳導材料68之電源平面可用來為上覆之電晶體 提供一回授偏壓並藉由向該電源平面施加一預定偏壓來改 變電晶體特徵。在該實施中，傳導區域52未連接至用於提 供該偏壓之電源平面。該偏壓修改電晶體之耗盡區域。可 實施對該偏壓之控制，使得可針對一預定類型的電路操作 或在操作之特定週期期間（諸如，舉例而言，視所消耗的功 率之量而定的週期）藉由該電源平面來偏壓積體電路内之 電晶體部分。 在前述說明書中，本發明已參考特定實施例來加以描 述。然而，一般熟習此項技術者會瞭解到能進行各種修改 及變化而不偏離如以下申請專利範圍所述之本發明的範 94915.doc • 16· 1344191 目的，且無需按比例繪製。例如，為了有助於改善對本發 明之實施例的理解，圖中一些元件之尺寸相對於其它元件 之尺寸可能進行了誇示。 【主要元件符號說明】 10 半導體裝置 12 基板 14 層 16 層 18 閘極 20 側壁間隔器 22 背面源極區域 23 沒極區域 26 閘極接觸 28 氧化物 30 擋止層 31 氧化物 32 背面接觸 33 汲極接觸 34 擋止層 36 結合層 38 載體基板 40 可選層 42 光阻層 44 開口 949I5.doc 開口 傳導層 傳導區域 傳導區域 通路 通路 層 層 層 光阻層 開口 傳導材料 障壁層 氧化物層 電極傳導材料 層 電極傳導材料 光阻 氣化物層 光阻 氧化物薄膜 硬光罩層 光阻 層 19- 1344191 93 頂面電極通路 94 最終基板 95 底面電極通路 96 通路 97 光阻 99 傳導材料 101 鈍化層 113 接觸通路 94915.doc - 20

Claims (1)

1344191 第093123127號專利申請案 中文申請專利範圍替換本(100年1月）2<P^ 十、申請專利範圍： L 一種半導體裝置，包含： 一電晶體包含一第一電極，一閘極以及—第二電極， 該閘極係利用一閘極連接點連接至該半導體裝置之一後 面’該後面係由一基板支持；以及 -電容覆蓋該電晶體’該電容具有一第—電極連接至 忒半導體裝置之一前面及該電晶體之該第一電極，以及 一第二電極連接至該前面及該後面。 2. —種形成一半導體裝置之方法，包含： 一閘極以及一第二電 k供一電晶體包含一第一電極 極’遠問極係利用_閘極接點連接至該半導體裝置之一 後面，該後面係由一基板支持；以及 提么、電谷覆蓋該電晶體，該電容具有一第一電極連 接至"亥半導體裝置之—前面及該電晶體之該第-電極， 以及一第二電極連接至該前面及該後面。 94915-1000128.doc
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US6838332B1 (en) 2005-01-04
CN1823413A (zh) 2006-08-23
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US7122421B2 (en) 2006-10-17
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