TW201738966A - 多個背閘極電晶體 - Google Patents

多個背閘極電晶體 Download PDF

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Publication number
TW201738966A
TW201738966A TW105116603A TW105116603A TW201738966A TW 201738966 A TW201738966 A TW 201738966A TW 105116603 A TW105116603 A TW 105116603A TW 105116603 A TW105116603 A TW 105116603A TW 201738966 A TW201738966 A TW 201738966A
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Taiwan
Prior art keywords
transistor
wafer
backside
conductive contacts
contacts
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TW105116603A
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English (en)
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TWI618153B (zh
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泰瑞斯Ｂ 霍克
理查Ａ 菲利浦
安東尼Ｋ 史塔佩爾
卡斯羅 瑞納塔Ａ 卡米羅
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格羅方德半導體公司
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Publication of TWI618153B publication Critical patent/TWI618153B/zh

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Abstract

本揭露係關於半導體結構，尤係關於多個背閘極電晶體結構以及製造方法。該結構包括：電晶體，形成於半導體材料及下方基板上方；以及多個隔離接觸區，位於該電晶體的本體或通道下方，經構造成在不同位置向該電晶體的該本體提供局部電位。

Description

多個背閘極電晶體
本揭露係關於半導體結構，尤係關於多個背閘極電晶體結構以及製造方法。
已針對類比應用開發了超薄本體及超薄BOX(埋置氧化物)(ultra-thin body and ultra-thin BOX；UTBB)SOI CMOS技術。尤其，UTBB對於以高Id、Gmmax以及Av為特徵的類比應用具有良好的應用潛力。不過，這些及其它類型裝置受到操作缺陷的影響。例如，UTBB及其它類型裝置(例如FET)僅可向裝置的本體或通道的單個位置施加單個偏壓，因此在其功能性及關鍵參數上有所限制。在這種情況下，需要針對特定的應用設計特定的結構，從而導致較高的設計及製造成本。
在本揭露的一個態樣中，一種結構包括：形成於半導體材料及下方基板上方的電晶體；以及位於該電晶體的本體下方的多個隔離接觸區，經構造成在不同位置向該電晶體的該本體或通道提供局部電位。
在本揭露的一個態樣中，一種結構包括： 形成於半導體材料上方的電晶體；以及位於該電晶體下方的多個背側導電接觸，其向該電晶體的本體提供不同位置的不同偏壓。
在本揭露的一個態樣中，一種結構包括：設於晶圓上的電晶體；位於該電晶體的第一邊緣下方的第一背側導電區；延伸於該電晶體的第二邊緣下方的第二背側導電區；位於該電晶體的通道區下方的一個或多個多背側導電區；以及自該晶圓的前側與各該第一、第二以及一個或多個多背側導電區連接的電壓偏壓，其向該電晶體的本體提供不同位置的不同偏壓。
5‧‧‧多個背閘極電晶體結構
10‧‧‧基板、下方基板、晶圓、永久晶圓
12‧‧‧絕緣體層、絕緣材料
14‧‧‧半導體材料、半導體層、矽層
16‧‧‧矽化物層
18‧‧‧淺溝槽隔離(STI)結構、STI結構
20‧‧‧閘極介電材料
22‧‧‧閘極結構
24‧‧‧氮化矽層
26‧‧‧層間介電層、層間介電材料
27‧‧‧接觸
27'‧‧‧接觸
28‧‧‧線路
28'‧‧‧線路、金屬線路、上線路層
28"‧‧‧線路、金屬線路、上線路層
29‧‧‧接觸、背側接觸
29'‧‧‧接觸、背側接觸
29"‧‧‧接觸、背側接觸
30‧‧‧線路、金屬線路、背側線路
30"‧‧‧線路、背側線路
34‧‧‧焊料、焊料連接
50‧‧‧源汲區、通道邊緣區、邊緣、源區
50'‧‧‧通道、通道區
50"‧‧‧源汲區、通道邊緣區、邊緣、汲區
51‧‧‧雙鑲嵌開口、接觸
51'‧‧‧單鑲嵌開口、線路
100‧‧‧操作晶圓
200‧‧‧臨時晶圓
通過參照以本揭露的示例實施例的非限制性示例方式表示的多個附圖，在下面的具體實施方式中說明本揭露。
第1圖顯示依據本揭露的態樣的多個背閘極電晶體結構及相應製程。
第2圖顯示依據本揭露的額外態樣的多個背閘極電晶體結構及相應製程。
第3圖顯示依據本揭露的另外額外態樣的多個背閘極電晶體結構及相應製程。
第4圖顯示依據本發明的態樣的多個背閘極電晶體結構的頂視圖。
第5A至5E圖顯示依據本發明的態樣構建多個背閘極電晶體結構的製程。
本揭露係關於半導體結構，尤係關於多個背閘極電晶體結構以及製造方法。在實施例中，該多個背閘極電晶體結構可為超薄本體及埋置氧化物(UTBB)電晶體，其允許藉由改變BOX(buired oxide；埋置氧化物)層下方的區域的電位來操控閾值電壓。更具體而言，本揭露說明具有可藉由對特定位置(例如沿寬度尺寸的條紋或沿長度尺寸的條紋)施加特定偏壓而獨立操控的電晶體的部分的裝置。較佳地，藉由這樣的操控，可調整並匹配關鍵類比FET參數，例如汲極至源極擊穿電壓、gds及gm，以及Vt。而且，可詳細地調節或者(或許更正確地說)忽略(tune out)裝置的寬度變化。另外，可形成並動態地調變不對稱裝置。
在更具體的實施例中，本文中所述的結構可包括較長或較寬的電晶體，其中，可使用一個或多個淺溝槽隔離(shallow trench isolation；STI)區(接面)來橫向隔離或隔開背側接觸。例如，該STI接面最小可為約100奈米。例如，該結構可用於具有100奈米至2000奈米的長度的類比功能中。由於匹配被改進，故本文中所述的結構可為可用於類比功能的寬裝置或長裝置。在任意這些不同的變化中，藉由在電晶體的背側上設置接觸(例如閘極結構)，現在有可能向電晶體提供不同的偏壓，並因此針對不同的功能性提供操控裝置的能力，如本文中進一步所述。
本揭露的多個背閘極電晶體結構可通過若 干不同的工具以若干方式製造。不過，一般來說，該些方法及工具用以形成微米及奈米級尺寸的結構。用以製造本揭露的多個背閘極電晶體結構的方法(也就是技術)採用積體電路(IC)技術。例如，該結構構建於晶圓上並以藉由晶圓的頂部上的光微影製程圖案化的材料膜實現。詳而言之，該多個背閘極電晶體結構的製造使用三個基本構建塊：(i)在基板上沉積材料薄膜，(ii)藉由光微影成像而在該些膜的頂部上鋪設圖案化遮罩，以及(iii)相對於該遮罩而選擇性蝕刻該些膜。
第1圖通過沿第4圖中所示的線X-X’所作的剖視圖顯示依據本揭露的態樣的多個背閘極電晶體結構及相應製程。更具體而言，如第1圖中所示，多個背閘極電晶體結構5包括形成於基板10上的絕緣體層12。在實施例中，基板10可為例如玻璃基板或高電阻矽(Si)晶圓。絕緣體層12可為氧化物層。在絕緣體層12上形成半導體材料14。在實施例中，半導體材料14可由任意適當的材料組成，包括但不限於Si、SiGe、SiGeC、SiC、GE合金、GaAs、InAs、InP以及其它III/V或II/VI族化合物半導體。半導體材料14可形成約10奈米至約4000奈米的厚度，較佳約30奈米至100奈米，不過本文中考慮其它厚度。
在實施例中，半導體材料14可為絕緣體上矽(silicon-on-insulator；SOI)上的薄矽層，且絕緣層12可為該SOI晶圓上的埋置氧化物(BOX)。基板10可能已與該SOI晶圓上的初始操作晶圓被移除以後的BOX層12的下 側結合。
在暴露半導體層14上形成矽化物層16。在實施例中，矽化物層16可為例如現有技術中已知的鈷、鈦、鎳、鉑或鎢矽化物。矽化物層16可藉由傳統的自對準矽化物(self-aligned silicide；salacide)製程形成。作為非限制性示例，該矽化物製程以沉積薄的過渡金屬層例如鈷、鈦、鎳、鉑或鎢開始。在沉積該材料以後，加熱結構，以使該過渡金屬與(除其它區域以外)該半導體裝置的主動區(例如源極、汲極、閘極接觸區)中的暴露矽(或本文中所述的其它半導體材料)反應，從而形成低電阻過渡金屬矽化物。在該反應之後，藉由化學蝕刻移除任意剩餘的過渡金屬，保留該裝置的主動區中的矽化物。
仍請參照第1圖，淺溝槽隔離(STI)結構18可形成於半導體材料14中，也就是延伸穿過矽層14而無矽化物形成於表面上。在實施例中，STI結構18可藉由現有技術中已知的傳統光微影、蝕刻、沉積以及平坦化製程形成。更具體地說，在矽化物層16上方形成的阻劑可暴露於能量(例如光)，以形成一個或多個開口(例如圖案)。利用對半導體材料14及矽化物層16具有選擇性的化學材料，通過該些開口可執行蝕刻製程，例如反應性離子蝕刻(reative ion etching；RIE)。該蝕刻製程將在半導體材料14中形成開口。接著，利用傳統的剝離製程(例如氧灰化)移除該阻劑，隨後，在該些開口內沉積絕緣體材料。該沉積製程可為使用氧化物材料的傳統化學氣相沉積(chemical vapor deposition；CVD)製程。利用傳統的化學機械拋光(chemical mechanical polishing；CMP)製程可移除矽化物層16的表面上的任意剩餘氧化物材料。以此方式，可形成橫向隔離區。
仍請參照第1圖，在圖案化矽層14以後，在半導體層14上形成閘極介電材料20。在實施例中，依據裝置所需的性能特徵，可利用例如矽的熱氧化、低k或高k介電材料的化學氣相沉積等任意傳統的沉積製程來沉積閘極介電材料20。該高k介電材料可為例如HfO2，不過本文中考慮其它材料。
第1圖還顯示閘極結構22(例如FET閘極結構)的形成。在實施例中，閘極結構22可為藉由先閘極(gate first)或後閘極(gate last)製程形成的多晶閘極結構或金屬閘極結構。在實施例中，在先閘極或後閘極製程中，利用傳統的沉積、微影及蝕刻製程可形成閘極結構22。在任何情況下，閘極結構22都形成於閘極介電材料20上方。
閘極結構22可包括側壁結構、間隔物、接觸等，全部都藉由傳統製程形成，因此本文中無須為理解當前的結構而作進一步解釋。另外，在實施例中，半導體層14可以例如使用砷、銻、硼、磷或現有技術中已知的其它摻雜物的傳統方式摻雜或離子注入，以形成閘極結構22的源汲區。例如，砷可用於n型半導體，硼可用於p型半導體。
仍請參照第1圖，在閘極結構22及矽化物 層16上方沉積視需要的氮化矽層24。在實施例中，可利用傳統的CVD製程沉積氮化矽層24。氮化矽層24可沉積至約25奈米至約75奈米的厚度，不過本揭露考慮其它尺寸。在實施例中，氮化矽層24充當可動離子阻障層。而且，在實施例中，氮化矽層24充當蝕刻停止或標記層以供後續接觸27形成。在氮化矽層24上方沉積並平坦化層間介電層26。在實施例中，層間介電層26可為利用傳統的沉積製程(例如CVD製程)形成的氧化物或低k介電材料，如現有技術所已知者。
在層間介電層26中形成接觸27、27'及金屬線路28'、28"。例如，利用傳統的微影、蝕刻製程、沉積及平坦化製程可形成與閘極結構22的源汲區直接接觸的接觸27及線路28'。接觸27、27'及金屬線路28'、28"可藉由傳統的單或雙鑲嵌(damascene)製程形成，從而導致接觸27、27'及上線路層28'、28"。在實施例中，接觸27、27'及線路28'、28"可為任意導電材料，例如銅、鋁、鎢等。在沉積製程以後，可執行CMP製程以自層間介電層26移除任意殘餘金屬。或者，可利用第一單鑲嵌製程形成接觸27、27'並接著利用單鑲嵌製程或第二減蝕刻(subtractive etch)製程形成線路28'、28"，如現有技術所已知者。
另外，接觸29、29'以及線路30可穿過裝置的背側形成，延伸至或穿過絕緣體層12。接觸29、29'及金屬線路30藉由傳統的單或雙鑲嵌或減蝕刻微影、蝕刻製程及沉積製程形成。例如，接觸29、29'及線路30可藉由 傳統的雙鑲嵌製程或者現有技術中已知的任意方法例如單鑲嵌或減蝕刻形成。
如第1圖中進一步所示，在閘極結構22下方的絕緣體層12(例如BOX層)中形成一個或多個背側接觸29、29'及線路30。在實施例中，一個或多個背側接觸29、29'及線路30是藉由絕緣材料12橫向隔開的隔離區。除位於閘極結構的相對邊緣下方以外(例如閘極結構22的源汲區50、50")，一個或多個背側接觸29還位於閘極結構22下方。一個或多個背側接觸29及線路30可與由接觸27'、線路28"及接觸29'代表性顯示的不同電壓源連接。接觸29'與接觸27'、線路28"電性接觸，並且還與該FET下方的其中一個接觸29電性連接。該FET下方的所有接觸29都可與晶圓前側連接，從而使預定的電壓施加於該些接觸。
藉由使FET通道及本體背側接觸與不同的電壓源連接，現在有可能自裝置的背側獲得獨立的電壓控制，例如獨立的偏壓或電位，從而提供操控閘極結構22(例如電晶體)的特性的能力。更具體地說，閘極結構22下方(例如閘極結構22的通道區50'中(例如中心))的一個或多個接觸29可經偏壓以降低電晶體的導通電阻，而電晶體的邊緣(源汲區50、50")下方的一個或多個背側接觸29可經偏壓以改進閘極結構22的邊緣處的擊穿電壓。
例如，通道邊緣區50、50"可經偏壓以增加源極至汲極擊穿電壓，而離開通道邊緣區50、50"的通道區50'可經偏壓以降低通道電阻。這將導致NFET開關例如 具有改進的擊穿電壓以及較低的導通電阻。例如，藉由僅在源極(例如區50)向背閘極施加不同的電壓，有可能改進裝置的gds，使裝置不對稱。藉由在汲極端(例如元件符號50")施加電壓，還有可能提供正向偏壓。而且，如需要，藉由向一個或多個背側接觸動態地施加電壓，有可能提供動態不對稱(例如，如果裝置為通閘(passgate))。此外，對於高Vt裝置，現在有可能僅向如元件符號50'代表性所示的通道的中心部分施加背閘極電壓，從而提高Vt而不增加汲極電場並因此把對BTB(帶間)的影響最小化。另外，藉由在寬裝置的邊緣50、50"上施加不同的背閘極電壓，有可能消除較寬與較窄裝置的Vt變化，從而提供調諧的窄通道效應。
在實施例中，已對本文中所述的結構(例如具有0.01微米BOX厚度的背閘極的裝置)進行模擬。在該模擬中，已發現背閘極電壓在具有0.75V的漂移時，Vt可獲得100mV的漂移。下面是一組電壓條件，其應當與BOX厚度成線性比例。
Vg偏壓=1.5V；Vds偏壓=0.05V(線性區)；通道LR(左右)邊緣電壓偏壓-0.25V；以及通道中心電壓偏壓0.5V。
這些電壓條件往往“切斷(shut off)”裝置的外側邊緣，該外側邊緣通常具有與裝置的其餘部分相比較低的Vt。
在實施例中，背側接觸29、29'及線路30可為以特定間隔設置的任意導電金屬，例如銅、鎢、鋁、摻雜多晶等。背側接觸29、29'及線路30的導電性與前側接觸27、27'及線路28、28"相比則不太重要，因為無電流或低電流經過這些接觸29、29'及線路30。例如，一個或多個背側接觸29可沿閘極結構22的寬度尺寸而等距離間隔，藉由絕緣體層12的絕緣體材料隔開。或者，一個或多個背側接觸29可沿閘極結構22的長度尺寸而間隔，藉由絕緣體層12的絕緣體材料隔開。在另外的示例實施例中，一個或多個背側接觸29可為約20至30奈米寬，並隔開約20至30奈米的距離，不過依據閘極結構22的特定技術節點，本文中考慮其它尺寸。例如STI接面可為約100奈米，用於類比功能的裝置為約30奈米至2000奈米長。
如第1圖的實施例中所示，背側接觸29、29'完全穿過絕緣體層12形成，與閘極結構22下方的半導體材料14的背側接觸，不過如本文中所述也考慮其它配置。在實施例中，接觸29與控制施加於其的電壓偏壓的線路例如線路28"直接電性及物理接觸。
背側接觸29、29'可藉由傳統的微影、蝕刻及沉積方法形成。例如，在移除SOI操作晶圓以後並在接合/形成/接附永久基板10於絕緣體層12之前，當絕緣體層12暴露時，可在絕緣體層12上形成阻劑。如本文中已說明的那樣，該阻劑可暴露於能量(例如光)，以形成一個或多個開口(例如圖案)。利用對絕緣體層12具有選擇性的 化學材料，通過該些開口可執行蝕刻製程，例如反應性離子蝕刻(RIE)。該蝕刻製程將在絕緣體層12中形成開口，在利用傳統的剝離製程(例如氧灰化)剝離該阻劑以後，用金屬材料填充該些開口。該沉積製程可為CVD製程。利用傳統的CMP製程可移除絕緣體層12的表面上的任意剩餘金屬材料。一旦完成背側接觸，即可將基板10接附至絕緣體層12。
第2圖顯示依據本揭露的額外態樣的多個背閘極電晶體結構及相應製程。在此實施例中，多個背閘極電晶體結構5'包括形成於絕緣體層12中的一個或多個背側接觸29'及線路30。如上所述，一個或多個背側接觸29'及線路30是藉由絕緣材料12橫向隔開的隔離區。不過，在此實施例中，一條或多條背側線路30不具有抵達或接觸FET通道下方的半導體材料14的接觸。換句話說，一條或多條背側線路30僅部分穿過絕緣體層12形成，在線路30的端部與半導體材料14之間留有間隔。
利用傳統的光微影、蝕刻及沉積方法，在實質相同的位置，例如在閘極結構22的邊緣50、50"(例如源汲區)及通道區50'(例如中心)，以與如上所述實質相同的方式可形成一條或多條背側線路30；不過，該蝕刻製程將經定時以形成僅部分穿過絕緣體層12的厚度的溝槽。如第2圖中所示，一個或多個接觸29'可以與如第1圖中所述類似的方式藉由接觸29'、接觸27'及線路28"將FET通道下方的線路30與晶圓前側上的電壓源電性連接。
第3圖顯示依據本揭露的另外額外態樣的多個背閘極電晶體結構及相應製程。在此實施例中，多個背閘極電晶體結構5"包括完全穿過絕緣體層12形成的一個或多個背側接觸29"以及形成於絕緣體層12下方的線路30"。使用黏著層31將下方基板10與絕緣體層12接合。如上所述，一條或多條背側線路30"為隔離區，但現在藉由黏著層31橫向隔開。
在第3圖的實施例中，一條或多條背側線路30"不抵達或接觸半導體材料14。換句話說，一條或多條背側線路30"接觸絕緣體層12的下側，從而在線路30的頂部表面與半導體材料14的底部表面之間留有間隔。在實施例中，該間隔可為絕緣體層12的厚度。與其它實施例一樣，接觸29"用以將一條或多條線路30與晶圓前側上的電壓偏壓連接。
以與如上所述實質相同的方式，例如穿過絕緣體層14並在其表面上藉由傳統微影、蝕刻及沉積方法可形成一個或多個背側接觸29"及線路30"；不過，另外，在用以將絕緣體層12與半導體層14接合的接合回流(reflow)製程中，一條或多條背側線路30"將被封裝於黏著層31內。在此實施例中，如本文中所述的其它實施例那樣，一條或多條背側線路30"位於實質相同的位置，例如位於閘極結構22的邊緣50、50"(例如源汲區)及通道區50'(例如中心)。
在額外實施例中，第1至3圖中所示的實施 例的任意組合可經組合以形成背側接觸及線路。例如，本文中考慮接觸可形成於：(i)部分位於絕緣體層12及下方基板10的全部厚度內；(ii)部分位於絕緣體層12內且部分穿過下方基板10或黏著層材料31的厚度；以及/或者(iii)完全位於絕緣體層12及下方基板10的全部厚度內。
第4圖顯示依據本揭露的態樣的多個背閘極電晶體的頂視圖。如第4圖中所示，一個或多個背側接觸29和/或線路30的每一者係設於閘極結構22下方。要注意的是，背側接觸29僅包括於第1圖的實施例而不包括於第2及3圖的實施例。一條或多條背側線路30設於閘極結構22的源區50、汲區50"及通道50'下方。一個或多個背側接觸29'及線路30可與線路27(如第1圖中所示)連接。線路27與電壓源連接，以經由一個或多個背側接觸29和/或線路30的每一者向閘極結構的本體提供特定電壓(偏壓)。因此，以此方式，一個或多個背側接觸29和/或線路30可向閘極結構22的背側上的特定位置提供偏壓。
第5A至5E圖顯示依據本揭露的態樣移除SOI操作晶圓、在BOX中或上形成線路及接觸，以及將玻璃或其它操作晶圓接附至BOX的下側從而構建多個背閘極電晶體結構的製程。如第5A圖中所示，利用臨時接附接合製程(例如HD3007聚醯亞胺)，在形成一個或多個背側接觸之前，將臨時晶圓200接附至第1至4圖中所述的任意結構中。在實施例中，臨時晶圓200可為玻璃晶圓或矽操作晶圓。
在第5B圖中，翻轉結構並移除操作晶圓100，以暴露絕緣體層12。在實施例中，可藉由背側研磨及蝕刻的組合來移除操作晶圓100，如現有技術中所已知者。利用傳統的微影及蝕刻製程圖案化絕緣體層12，接著沉積材料，如上所述，以形成接觸及線路，如現有技術所已知者。在實施例中，執行減蝕刻、鑲嵌或雙鑲嵌蝕刻製程。以此方式，在絕緣體層12中可形成雙鑲嵌開口51，例如接觸及溝槽結構，以及一個或多個單鑲嵌開口51'。基於蝕刻速率，該接觸可部分或完全延伸穿過絕緣體層12，如本文中所述。要注意的是，第3圖中所示的實施例將使用單鑲嵌製程來形成接觸51及減蝕刻製程來形成線路51'(未圖示)。
在第5C圖中，在該些鑲嵌開口內形成金屬材料，以形成背側接觸29(未圖示)、29'以及線路30。在實施例中，該金屬材料可為本文中所述的任意導電材料，例如銅、鎢、鋁、摻雜多晶等。本領域的普通技術人員也應當理解，可形成不止一個背側接觸29、29'及線路30，例如可以本文中所述的方式形成多個此類背側接觸及線路。在實施例中，可藉由傳統的沉積製程(例如CVD)以及後續的清洗製程(例如CMP)來形成該導電材料。
在第5D圖中，可將永久晶圓10與絕緣體層12接合。在實施例中，永久晶圓10可為例如玻璃晶圓或高電阻矽晶圓。利用氧化物-氧化物接合、黏著接合、共晶金屬接合或其它已知技術可接合晶圓10。作為附加或替 代實施例，晶圓10也可經過加工以形成部分或者完全穿過晶圓10的矽穿孔，如本文中所述。
在第5E圖中，可移除該臨時晶圓，以暴露接觸27及線路28，例如源極/汲極接觸及其它線路。接著，如需要，可對層間介電材料26、接觸27及線路28的暴露表面執行清洗製程。可形成額外視需要的線路、過孔、焊料凸塊、銅柱等層面(未圖示)。在晶圓接合及晶圓背側加工之前，這些視需要的額外線路、過孔以及封裝層可能已經形成，如現有技術所已知者。
在替代實施例中，臨時晶圓200可被用作永久操作晶圓，在絕緣體層12上方形成額外線路層。接著，可形成至接觸的視需要之線路連接墊過孔層，設置焊料34連接。在實施例中，焊料連接34可為例如C4焊料連接。隨後，可對晶圓進行傳統的切割，將單獨晶片予以封裝。
上述方法用於積體電路晶片的製造。製造者可以原始晶圓形式(也就是作為具有多個未封裝晶片的單個晶圓)、作為裸晶粒，或者以封裝形式分配所得的積體電路晶片。在後一種情況中，晶片安裝於單晶片封裝件中(例如塑料承載件，其具有附著至母板或其它更高層承載件的引腳)或者多晶片封裝件中(例如陶瓷承載件，其具有表面互連或嵌埋互連之任一者或兩者皆有)。在任何情況下，接著將該晶片與其它晶片、分立電路元件和/或其它信號處理裝置集成，作為(a)中間產品(例如母板)或者(b)最終產品的一部分。該最終產品可為包含積體電路晶片的任意產 品，涉及範圍從玩具及其它低端應用至具有顯示器、鍵盤或其它輸入裝置以及中央處理器的先進電腦產品。
對本揭露的各種實施例所作的說明是出於說明目的，而非意圖詳盡無遺或限於所揭露的實施例。許多修改及變更對於本領域的普通技術人員將顯而易見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進，或者使本領域的普通技術人員能夠理解本文中所揭露的實施例。
5‧‧‧多個背閘極電晶體結構
10‧‧‧基板、下方基板、晶圓、永久晶圓
12‧‧‧絕緣體層、絕緣材料
14‧‧‧半導體材料、半導體層、矽層
16‧‧‧矽化物層
18‧‧‧淺溝槽隔離(STI)結構、STI結構
20‧‧‧閘極介電材料
22‧‧‧閘極結構
24‧‧‧氮化矽層
26‧‧‧層間介電層、層間介電材料
27‧‧‧接觸
27'‧‧‧接觸
28'‧‧‧線路、金屬線路、上線路層
28"‧‧‧線路、金屬線路、上線路層
29‧‧‧接觸、背側接觸
29'‧‧‧接觸、背側接觸
30‧‧‧線路、金屬線路、背側線路
50‧‧‧源汲區、通道邊緣區、邊緣、源區
50'‧‧‧通道、通道區
50"‧‧‧源汲區、通道邊緣區、邊緣、汲區

Claims (20)

  1. 一種結構，包括：電晶體，形成於半導體材料及下方基板上方；以及多個隔離接觸區，位於該電晶體的本體下方，經構造成在不同位置向該電晶體的該本體或通道提供局部電位。
  2. 如申請專利範圍第1項所述的結構，其中，該些隔離接觸區藉由絕緣材料橫向隔開。
  3. 如申請專利範圍第1項所述的結構，其中，該些隔離接觸區藉由與該多個隔離接觸區相反類型的摻雜而橫向隔開。
  4. 如申請專利範圍第1項所述的結構，其中，該不同位置的該局部電位是施加於該電晶體的不同區域的不同電位。
  5. 如申請專利範圍第1項所述的結構，其中，該些隔離接觸區是沿該電晶體的長度。
  6. 如申請專利範圍第1項所述的結構，其中，該些隔離接觸區是沿該電晶體的寬度。
  7. 如申請專利範圍第1項所述的結構，其中，該些隔離接觸區為氧化物層中的導電接觸，位於該半導體材料下方。
  8. 如申請專利範圍第7項所述的結構，其中，該些導電接觸完全延伸穿過該氧化物層，與該半導體材料接觸。
  9. 如申請專利範圍第7項所述的結構，其中，該些導電接觸部分延伸穿過該氧化物層，從而在該些導電接觸的端部與該半導體材料之間留有間隔。
  10. 如申請專利範圍第1項所述的結構，其中，該些隔離接觸區為晶圓中的導電接觸，藉由該氧化物層及該半導體層與該電晶體隔開。
  11. 如申請專利範圍第10項所述的結構，其中，該些導電接觸部分穿過該晶圓而形成。
  12. 如申請專利範圍第10項所述的結構，其中，該些導電接觸為第一摻雜物類型且該晶圓為與該第一摻雜物類型相反的第二摻雜物類型。
  13. 一種結構，包括：電晶體；以及多個背側導電接觸，位於該電晶體下方，向該電晶體的本體提供不同位置的不同偏壓。
  14. 如申請專利範圍第13項所述的結構，其中，該多個背側導電接觸藉由絕緣材料橫向隔開。
  15. 如申請專利範圍第13項所述的結構，其中，該多個背側導電接觸藉由與該多個背側接觸相反類型的摻雜而橫向隔開。
  16. 如申請專利範圍第13項所述的結構，其中，該多個背側導電接觸是沿該電晶體的長度或該電晶體的寬度。
  17. 如申請專利範圍第13項所述的結構，其中，該多個背側導電接觸位於埋置氧化物層中，與該半導體材料接 觸。
  18. 如申請專利範圍第13項所述的結構，其中，該多個背側導電接觸位於埋置氧化物層中，與該半導體材料的底部表面隔開。
  19. 如申請專利範圍第13項所述的結構，其中，該多個背側導電接觸形成於晶圓中，藉由絕緣材料與該半導體材料隔開。
  20. 一種結構，包括：電晶體，設於晶圓上；第一背側導電區，位於該電晶體的第一邊緣下方；第二背側導電區，延伸於該電晶體的第二邊緣下方；一個或多個多背側導電區，位於該電晶體的通道區下方；以及電壓偏壓，自該晶圓的前側與各該第一、第二以及一個或多個多背側導電區連接，向該電晶體的本體提供不同位置的不同偏壓。
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