CN107342258B - 多个背栅极晶体管 - Google Patents

多个背栅极晶体管 Download PDF

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Publication number
CN107342258B
CN107342258B CN201611113782.5A CN201611113782A CN107342258B CN 107342258 B CN107342258 B CN 107342258B CN 201611113782 A CN201611113782 A CN 201611113782A CN 107342258 B CN107342258 B CN 107342258B
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transistor
layer
semiconductor structure
contact
backside
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CN107342258A (zh
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T·B·霍克
R·A·费尔普斯
A·K·斯坦珀
R·A·卡米略-卡斯蒂略
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GlobalFoundries US Inc
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GlobalFoundries Inc
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Abstract

本发明涉及多个背栅极晶体管。本发明是关于半导体结构，尤指多个背栅极晶体管结构以及制造方法。该结构包括：晶体管，形成于半导体材料及下方基板上方；以及多个隔离接触区，位于该晶体管的本体或通道下方，构造成在不同位置向该晶体管的该本体提供局部电位。

Description

多个背栅极晶体管
技术领域
本发明关于半导体结构，尤指关于多个背栅极晶体管结构以及制造方法。
背景技术
已针对类比应用开发了超薄本体及超薄BOX(掩埋氧化物)(ultra-thin body andultra-thin BOX；UTBB)SOI CMOS技术。尤其，UTBB对于以高Id、Gmmax以及Av为特征的类比应用具有良好的应用潜力。不过，这些及其它类型装置受到操作缺陷的影响。例如，UTBB及其它类型装置(例如FET)仅可向装置的本体或通道的单个位置施加单个偏压，因此在其功能性及关键参数上有所限制。在这种情况下，需要针对特定的应用设计特定的结构，从而导致较高的设计及制造成本。
发明内容
在本发明的一个方面中，一种结构包括：形成于半导体材料及下方基板上方的晶体管；以及位于该晶体管的本体下方的多个隔离接触区，构造成在不同位置向该晶体管的该本体或通道提供局部电位。
在本发明的一个方面中，一种结构包括：形成于半导体材料上方的晶体管；以及位于该晶体管下方的多个背侧导电接触，其向该晶体管的本体提供不同位置的不同偏压。
在本发明的一个方面中，一种结构包括：设于晶圆上的晶体管；位于该晶体管的第一边缘下方的第一背侧导电区；延伸于该晶体管的第二边缘下方的第二背侧导电区；位于该晶体管的通道区下方的一个或多个多背侧导电区；以及自该晶圆的前侧与各该第一、第二以及一个或多个多背侧导电区连接的电压偏压，其向该晶体管的本体提供不同位置的不同偏压。
附图说明
通过参照以本发明的示例实施例的非限制性示例方式表示的多个附图，在下面的具体实施方式中说明本发明。
图1显示依据本发明的方面的多个背栅极晶体管结构及相应制程。
图2显示依据本发明的额外方面的多个背栅极晶体管结构及相应制程。
图3显示依据本发明的另外额外方面的多个背栅极晶体管结构及相应制程。
图4显示依据本发明的方面的多个背栅极晶体管结构的顶视图。
图5A至5E显示依据本发明的方面构建多个背栅极晶体管结构的制程。
符号说明
5 多个背栅极晶体管结构
10 基板、下方基板、晶圆、永久晶圆
12 绝缘体层、绝缘材料
14 半导体材料、半导体层、硅层
16 硅化物层
18 浅沟槽隔离(STI)结构、STI结构
20 栅极介电材料
22 栅极结构
24 氮化硅层
26 层间介电层、层间介电材料
27 接触
27’ 接触
28 线路
28’ 线路、金属线路、上线路层
28’’ 线路、金属线路、上线路层
29 接触、背侧接触
29’ 接触、背侧接触
29’’ 接触、背侧接触
30 线路、金属线路、背侧线路
30’’ 线路、背侧线路
34 焊料、焊料连接
50 源汲区、通道边缘区、边缘、源区
50’ 通道、通道区
50’’ 源汲区、通道边缘区、边缘、汲区
51 双镶嵌开口、接触
51’ 单镶嵌开口、线路
100 操作晶圆
200 临时晶圆。
具体实施方式
本发明关于半导体结构，尤指关于多个背栅极晶体管结构以及制造方法。在实施例中，该多个背栅极晶体管结构可为超薄本体及掩埋氧化物(UTBB)晶体管，其允许通过改变BOX(buired oxide；掩埋氧化物)层下方的区域的电位来操控阈值电压。更具体而言，本发明说明具有可通过对特定位置(例如沿宽度尺寸的条纹或沿长度尺寸的条纹)施加特定偏压而独立操控的晶体管的部分的装置。较佳地，通过这样的操控，可调整并匹配关键类比FET参数，例如漏极至源极击穿电压、gds及gm，以及Vt。而且，可详细地调节或者(或许更正确地说)忽略(tune out)装置的宽度变化。另外，可形成并动态地调变不对称装置。
在更具体的实施例中，本文中所述的结构可包括较长或较宽的晶体管，其中，可使用一个或多个浅沟槽隔离(shallow trench isolation；STI)区(接面)来横向隔离或隔开背侧接触。例如，该STI接面最小可为约100纳米。例如，该结构可用于具有100纳米至2000纳米的长度的类比功能中。由于匹配被改进，故本文中所述的结构可为可用于类比功能的宽装置或长装置。在任意这些不同的变化中，通过在晶体管的背侧上设置接触(例如栅极结构)，现在有可能向晶体管提供不同的偏压，并因此针对不同的功能性提供操控装置的能力，如本文中进一步所述。
本发明的多个背栅极晶体管结构可通过若干不同的工具以若干方式制造。不过，一般来说，该些方法及工具用以形成微米及纳米级尺寸的结构。用以制造本发明的多个背栅极晶体管结构的方法(也就是技术)采用集成电路(IC)技术。例如，该结构构建于晶圆上并以通过晶圆的顶部上的光微影制程图案化的材料膜实现。详而言之，该多个背栅极晶体管结构的制造使用三个基本构建块：(i)在基板上沉积材料薄膜，(ii)通过光微影成像而在所述膜的顶部上铺设图案化遮罩，以及(iii)相对于该遮罩而选择性蚀刻所述膜。
图1通过沿图4中所示的线X-X’所作的剖视图显示依据本发明的方面的多个背栅极晶体管结构及相应制程。更具体而言，如图1中所示，多个背栅极晶体管结构5包括形成于基板10上的绝缘体层12。在实施例中，基板10可为例如玻璃基板或高电阻硅(Si)晶圆。绝缘体层12可为氧化物层。在绝缘体层12上形成半导体材料14。在实施例中，半导体材料14可由任意适当的材料组成，包括但不限于Si、SiGe、SiGeC、SiC、GE合金、GaAs、InAs、InP以及其它III/V或II/VI族化合物半导体。半导体材料14可形成约10纳米至约4000纳米的厚度，较佳约30纳米至100纳米，不过本文中考虑其它厚度。
在实施例中，半导体材料14可为绝缘体上硅(silicon-on-insulator；SOI)上的薄硅层，且绝缘层12可为该SOI晶圆上的掩埋氧化物(BOX)。基板10可能已与该SOI晶圆上的初始操作晶圆被移除以后的BOX层12的下侧结合。
在暴露半导体层14上形成硅化物层16。在实施例中，硅化物层16可为例如现有技术中已知的钴、钛、镍、铂或钨硅化物。硅化物层16可通过传统的自对准硅化物(self-aligned silicide；salacide)制程形成。作为非限制性示例，该硅化物制程以沉积薄的过渡金属层例如钴、钛、镍、铂或钨开始。在沉积该材料以后，加热结构，以使该过渡金属与(除其它区域以外)该半导体装置的主动区(例如源极、漏极、栅极接触区)中的暴露硅(或本文中所述的其它半导体材料)反应，从而形成低电阻过渡金属硅化物。在该反应之后，通过化学蚀刻移除任意剩余的过渡金属，保留该装置的主动区中的硅化物。
仍请参照图1，浅沟槽隔离(STI)结构18可形成于半导体材料14中，也就是延伸穿过硅层14而无硅化物形成于表面上。在实施例中，STI结构18可通过现有技术中已知的传统光微影、蚀刻、沉积以及平坦化制程形成。更具体地说，在硅化物层16上方形成的阻剂可暴露于能量(例如光)，以形成一个或多个开口(例如图案)。利用对半导体材料14及硅化物层16具有选择性的化学材料，通过所述开口可执行蚀刻制程，例如反应性离子蚀刻(reativeion etching；RIE)。该蚀刻制程将在半导体材料14中形成开口。接着，利用传统的剥离制程(例如氧灰化)移除该阻剂，随后，在所述开口内沉积绝缘体材料。该沉积制程可为使用氧化物材料的传统化学气相沉积(chemical vapor deposition；CVD)制程。利用传统的化学机械抛光(chemical mechanical polishing；CMP)制程可移除硅化物层16的表面上的任意剩余氧化物材料。以此方式，可形成横向隔离区。
仍请参照图1，在图案化硅层14以后，在半导体层14上形成栅极介电材料20。在实施例中，依据装置所需的性能特征，可利用例如硅的热氧化、低k或高k介电材料的化学气相沉积等任意传统的沉积制程来沉积栅极介电材料20。该高k介电材料可为例如HfO2，不过本文中考虑其它材料。
图1还显示栅极结构22(例如FET栅极结构)的形成。在实施例中，栅极结构22可为通过先栅极(gate first)或后栅极(gate last)制程形成的多晶栅极结构或金属栅极结构。在实施例中，在先栅极或后栅极制程中，利用传统的沉积、微影及蚀刻制程可形成栅极结构22。在任何情况下，栅极结构22都形成于栅极介电材料20上方。
栅极结构22可包括侧壁结构、间隔物、接触等，全部都通过传统制程形成，因此本文中无须为理解当前的结构而作进一步解释。另外，在实施例中，半导体层14可以例如使用砷、锑、硼、磷或现有技术中已知的其它掺杂物的传统方式掺杂或离子注入，以形成栅极结构22的源汲区。例如，砷可用于n型半导体，硼可用于p型半导体。
仍请参照图1，在栅极结构22及硅化物层16上方沉积视需要的氮化硅层24。在实施例中，可利用传统的CVD制程沉积氮化硅层24。氮化硅层24可沉积至约25纳米至约75纳米的厚度，不过本发明考虑其它尺寸。在实施例中，氮化硅层24充当可动离子阻障层。而且，在实施例中，氮化硅层24充当蚀刻停止或标记层以供后续接触27形成。在氮化硅层24上方沉积并平坦化层间介电层26。在实施例中，层间介电层26可为利用传统的沉积制程(例如CVD制程)形成的氧化物或低k介电材料，如现有技术所已知者。
在层间介电层26中形成接触27、27’及金属线路28’、28’’。例如，利用传统的微影、蚀刻制程、沉积及平坦化制程可形成与栅极结构22的源汲区直接接触的接触27及线路28’。接触27、27’及金属线路28’、28’’可通过传统的单或双镶嵌(damascene)制程形成，从而导致接触27、27’及上线路层28’、28’’。在实施例中，接触27、27’及线路28’、28’’可为任意导电材料，例如铜、铝、钨等。在沉积制程以后，可执行CMP制程以自层间介电层26移除任意残余金属。或者，可利用第一单镶嵌制程形成接触27、27’并接着利用单镶嵌制程或第二减蚀刻(subtractive etch)制程形成线路28’、28’’，如现有技术所已知者。
另外，接触29、29’以及线路30可穿过装置的背侧形成，延伸至或穿过绝缘体层12。接触29、29’及金属线路30通过传统的单或双镶嵌或减蚀刻微影、蚀刻制程及沉积制程形成。例如，接触29、29’及线路30可通过传统的双镶嵌制程或者现有技术中已知的任意方法例如单镶嵌或减蚀刻形成。
如图1中进一步所示，在栅极结构22下方的绝缘体层12(例如BOX层)中形成一个或多个背侧接触29、29’及线路30。在实施例中，一个或多个背侧接触29、29’及线路30是通过绝缘材料12横向隔开的隔离区。除位于栅极结构的相对边缘下方以外(例如栅极结构22的源汲区50、50’’)，一个或多个背侧接触29还位于栅极结构22下方。一个或多个背侧接触29及线路30可与由接触27’、线路28’’及接触29’代表性显示的不同电压源连接。接触29’与接触27’、线路28’’电性接触，并且还与该FET下方的其中一个接触29电性连接。该FET下方的所有接触29都可与晶圆前侧连接，从而使预定的电压施加于所述接触。
通过使FET通道及本体背侧接触与不同的电压源连接，现在有可能自装置的背侧获得独立的电压控制，例如独立的偏压或电位，从而提供操控栅极结构22(例如晶体管)的特性的能力。更具体地说，栅极结构22下方(例如栅极结构22的通道区50’中(例如中心))的一个或多个接触29可经偏压以降低晶体管的导通电阻，而晶体管的边缘(源汲区50、50’’)下方的一个或多个背侧接触29可经偏压以改进栅极结构22的边缘处的击穿电压。
例如，通道边缘区50、50’’可经偏压以增加源极至漏极击穿电压，而离开通道边缘区50、50’’的通道区50’可经偏压以降低通道电阻。这将导致NFET开关例如具有改进的击穿电压以及较低的导通电阻。例如，通过仅在源极(例如区50)向背栅极施加不同的电压，有可能改进装置的gds，使装置不对称。通过在漏极端(例如元件符号50’’)施加电压，还有可能提供正向偏压。而且，如需要，通过向一个或多个背侧接触动态地施加电压，有可能提供动态不对称(例如，如果装置为通栅(passgate))。此外，对于高Vt装置，现在有可能仅向如元件符号50’代表性所示的通道的中心部分施加背栅极电压，从而提高Vt而不增加漏极电场并因此把对BTB(带间)的影响最小化。另外，通过在宽装置的边缘50、50’’上施加不同的背栅极电压，有可能消除较宽与较窄装置的Vt变化，从而提供调谐的窄通道效应。
在实施例中，已对本文中所述的结构(例如具有0.01微米BOX厚度的背栅极的装置)进行模拟。在该模拟中，已发现背栅极电压在具有0.75V的漂移时，Vt可获得100mV的漂移。下面是一组电压条件，其应当与BOX厚度成线性比例。
Vg偏压＝1.5V；
Vds偏压＝0.05V(线性区)；
通道LR(左右)边缘电压偏压-0.25V；以及
通道中心电压偏压0.5V。
这些电压条件往往“切断(shut off)”装置的外侧边缘，该外侧边缘通常具有与装置的其余部分相比较低的Vt。
在实施例中，背侧接触29、29’及线路30可为以特定间隔设置的任意导电金属，例如铜、钨、铝、掺杂多晶等。背侧接触29、29’及线路30的导电性与前侧接触27、27’及线路28、28’’相比则不太重要，因为无电流或低电流经过这些接触29、29’及线路30。例如，一个或多个背侧接触29可沿栅极结构22的宽度尺寸而等距离间隔，通过绝缘体层12的绝缘体材料隔开。或者，一个或多个背侧接触29可沿栅极结构22的长度尺寸而间隔，通过绝缘体层12的绝缘体材料隔开。在另外的示例实施例中，一个或多个背侧接触29可为约20至30纳米宽，并隔开约20至30纳米的距离，不过依据栅极结构22的特定技术节点，本文中考虑其它尺寸。例如STI接面可为约100纳米，用于类比功能的装置为约30纳米至2000纳米长。
如图1的实施例中所示，背侧接触29、29’完全穿过绝缘体层12形成，与栅极结构22下方的半导体材料14的背侧接触，不过如本文中所述也考虑其它配置。在实施例中，接触29与控制施加于其的电压偏压的线路例如线路28’’直接电性及物理接触。
背侧接触29、29’可通过传统的微影、蚀刻及沉积方法形成。例如，在移除SOI操作晶圆以后并在接合/形成/接附永久基板10于绝缘体层12之前，当绝缘体层12暴露时，可在绝缘体层12上形成阻剂。如本文中已说明的那样，该阻剂可暴露于能量(例如光)，以形成一个或多个开口(例如图案)。利用对绝缘体层12具有选择性的化学材料，通过所述开口可执行蚀刻制程，例如反应性离子蚀刻(RIE)。该蚀刻制程将在绝缘体层12中形成开口，在利用传统的剥离制程(例如氧灰化)剥离该阻剂以后，用金属材料填充所述开口。该沉积制程可为CVD制程。利用传统的CMP制程可移除绝缘体层12的表面上的任意剩余金属材料。一旦完成背侧接触，即可将基板10接附至绝缘体层12。
图2显示依据本发明的额外方面的多个背栅极晶体管结构及相应制程。在此实施例中，多个背栅极晶体管结构5’包括形成于绝缘体层12中的一个或多个背侧接触29’及线路30。如上所述，一个或多个背侧接触29’及线路30是通过绝缘材料12横向隔开的隔离区。不过，在此实施例中，一条或多条背侧线路30不具有抵达或接触FET通道下方的半导体材料14的接触。换句话说，一条或多条背侧线路30仅部分穿过绝缘体层12形成，在线路30的端部与半导体材料14之间留有间隔。
利用传统的光微影、蚀刻及沉积方法，在实质相同的位置，例如在栅极结构22的边缘50、50’’(例如源汲区)及通道区50’(例如中心)，以与如上所述实质相同的方式可形成一条或多条背侧线路30；不过，该蚀刻制程将经定时以形成仅部分穿过绝缘体层12的厚度的沟槽。如图2中所示，一个或多个接触29’可以与如图1中所述类似的方式通过接触29’、接触27’及线路28’’将FET通道下方的线路30与晶圆前侧上的电压源电性连接。
图3显示依据本发明的另外额外方面的多个背栅极晶体管结构及相应制程。在此实施例中，多个背栅极晶体管结构5’’包括完全穿过绝缘体层12形成的一个或多个背侧接触29’’以及形成于绝缘体层12下方的线路30’’。使用黏着层31将下方基板10与绝缘体层12接合。如上所述，一条或多条背侧线路30’’为隔离区，但现在通过黏着层31横向隔开。
在图3的实施例中，一条或多条背侧线路30’’不抵达或接触半导体材料14。换句话说，一条或多条背侧线路30’’接触绝缘体层12的下侧，从而在线路30的顶部表面与半导体材料14的底部表面之间留有间隔。在实施例中，该间隔可为绝缘体层12的厚度。与其它实施例一样，接触29’’用以将一条或多条线路30与晶圆前侧上的电压偏压连接。
以与如上所述实质相同的方式，例如穿过绝缘体层14并在其表面上通过传统微影、蚀刻及沉积方法可形成一个或多个背侧接触29’’及线路30’’；不过，另外，在用以将绝缘体层12与半导体层14接合的接合回流(reflow)制程中，一条或多条背侧线路30’’将被封装于黏着层31内。在此实施例中，如本文中所述的其它实施例那样，一条或多条背侧线路30’’位于实质相同的位置，例如位于栅极结构22的边缘50、50’’(例如源汲区)及通道区50’(例如中心)。
在额外实施例中，图1至图3中所示的实施例的任意组合可经组合以形成背侧接触及线路。例如，本文中考虑接触可形成于：(i)部分位于绝缘体层12及下方基板10的全部厚度内；(ii)部分位于绝缘体层12内且部分穿过下方基板10或黏着层材料31的厚度；以及/或者(iii)完全位于绝缘体层12及下方基板10的全部厚度内。
图4显示依据本发明的方面的多个背栅极晶体管的顶视图。如图4中所示，一个或多个背侧接触29和/或线路30的每一者设于栅极结构22下方。要注意的是，背侧接触29仅包括于图1的实施例而不包括于图2及图3的实施例。一条或多条背侧线路30设于栅极结构22的源区50、汲区50’’及通道50’下方。一个或多个背侧接触29’及线路30可与线路27(如图1中所示)连接。线路27与电压源连接，以经由一个或多个背侧接触29和/或线路30的每一者向栅极结构的本体提供特定电压(偏压)。因此，以此方式，一个或多个背侧接触29和/或线路30可向栅极结构22的背侧上的特定位置提供偏压。
图5A至图5E显示依据本发明的方面移除SOI操作晶圆、在BOX中或上形成线路及接触，以及将玻璃或其它操作晶圆接附至BOX的下侧从而构建多个背栅极晶体管结构的制程。如图5A中所示，利用临时接附接合制程(例如HD3007聚酰亚胺)，在形成一个或多个背侧接触之前，将临时晶圆200接附至图1至图4中所述的任意结构中。在实施例中，临时晶圆200可为玻璃晶圆或硅操作晶圆。
在图5B中，翻转结构并移除操作晶圆100，以暴露绝缘体层12。在实施例中，可通过背侧研磨及蚀刻的组合来移除操作晶圆100，如现有技术中所已知者。利用传统的微影及蚀刻制程图案化绝缘体层12，接着沉积材料，如上所述，以形成接触及线路，如现有技术所已知者。在实施例中，执行减蚀刻、镶嵌或双镶嵌蚀刻制程。以此方式，在绝缘体层12中可形成双镶嵌开口51，例如接触及沟槽结构，以及一个或多个单镶嵌开口51’。基于蚀刻速率，该接触可部分或完全延伸穿过绝缘体层12，如本文中所述。要注意的是，图3中所示的实施例将使用单镶嵌制程来形成接触51及减蚀刻制程来形成线路51’(未图示)。
在图5C中，在所述镶嵌开口内形成金属材料，以形成背侧接触29(未图示)、29’以及线路30。在实施例中，该金属材料可为本文中所述的任意导电材料，例如铜、钨、铝、掺杂多晶等。本领域的普通技术人员也应当理解，可形成不止一个背侧接触29、29’及线路30，例如可以本文中所述的方式形成多个此类背侧接触及线路。在实施例中，可通过传统的沉积制程(例如CVD)以及后续的清洗制程(例如CMP)来形成该导电材料。
在图5D中，可将永久晶圆10与绝缘体层12接合。在实施例中，永久晶圆10可为例如玻璃晶圆或高电阻硅晶圆。利用氧化物-氧化物接合、黏着接合、共晶金属接合或其它已知技术可接合晶圆10。作为附加或替代实施例，晶圆10也可经过加工以形成部分或者完全穿过晶圆10的硅穿孔，如本文中所述。
在图5E中，可移除该临时晶圆，以暴露接触27及线路28，例如源极/漏极接触及其它线路。接着，如需要，可对层间介电材料26、接触27及线路28的暴露表面执行清洗制程。可形成额外视需要的线路、过孔、焊料凸块、铜柱等层面(未图示)。在晶圆接合及晶圆背侧加工之前，这些视需要的额外线路、过孔以及封装层可能已经形成，如现有技术所已知者。
在替代实施例中，临时晶圆200可被用作永久操作晶圆，在绝缘体层12上方形成额外线路层。接着，可形成至接触的视需要的线路连接垫过孔层，设置焊料34连接。在实施例中，焊料连接34可为例如C4焊料连接。随后，可对晶圆进行传统的切割，将单独芯片予以封装。
上述方法用于集成电路芯片的制造。制造者可以原始晶圆形式(也就是作为具有多个未封装芯片的单个晶圆)、作为裸晶粒，或者以封装形式分配所得的集成电路芯片。在后一种情况中，芯片安装于单芯片封装件中(例如塑料承载件，其具有附着至母板或其它更高层承载件的引脚)或者多芯片封装件中(例如陶瓷承载件，其具有表面互连或嵌埋互连的任一者或两者皆有)。在任何情况下，接着将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成，作为(a)中间产品(例如母板)或者(b)最终产品的一部分。该最终产品可为包含集成电路芯片的任意产品，涉及范围从玩具及其它低端应用至具有显示器、键盘或其它输入装置以及中央处理器的先进电脑产品。
对本发明的各种实施例所作的说明是出于说明目的，而非意图详尽无遗或限于所揭示的实施例。许多修改及变更对于本领域的普通技术人员将显而易见，而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进，或者使本领域的普通技术人员能够理解本文中所揭示的实施例。

Claims (19)

1.一种半导体结构，包括：
晶体管，形成于半导体材料层及下方基板上方；以及
多个隔离接触区，至少位于通道中的该晶体管的本体下方以及该晶体管的源汲区，构造成在不同位置向该晶体管的该本体或该通道提供局部电位，
其中，所述隔离接触区为介电层中的导电接触，并通过该半导体材料层与该晶体管隔开。
2.如权利要求1所述的半导体结构，其中，所述隔离接触区通过绝缘材料横向隔开。
3.如权利要求1所述的半导体结构，其中，所述隔离接触区通过与该多个隔离接触区相反类型的掺杂而横向隔开。
4.如权利要求1所述的半导体结构，其中，该不同位置的该局部电位是施加于该晶体管的不同区域的不同电位。
5.如权利要求1所述的半导体结构，其中，所述隔离接触区是沿该晶体管的长度。
6.如权利要求1所述的半导体结构，其中，所述隔离接触区是沿该晶体管的宽度。
7.如权利要求1所述的半导体结构，其中，所述隔离接触区位于该半导体材料层下方。
8.如权利要求1所述的半导体结构，其中，所述导电接触完全延伸穿过该介电层，与该半导体材料层以及形成在该介电层下方的导线接触，并用黏着层将该下方基板与该介电层接合。
9.如权利要求1所述的半导体结构，其中，所述导电接触部分延伸穿过该介电层，从而在所述导电接触的端部与该半导体材料层之间留有间隔。
10.如权利要求1所述的半导体结构，其中，所述导电接触部分穿过晶圆而形成。
11.如权利要求1所述的半导体结构，其中，所述导电接触为第一掺杂物类型且晶圆为与该第一掺杂物类型相反的第二掺杂物类型。
12.一种半导体结构，包括：
晶体管；以及
多个背侧导电接触，位于该晶体管下方，向该晶体管的本体提供不同位置的不同偏压。
13.如权利要求12所述的半导体结构，其中，该多个背侧导电接触通过绝缘材料横向隔开。
14.如权利要求12所述的半导体结构，其中，该多个背侧导电接触通过与该多个背侧导电接触相反类型的掺杂而横向隔开。
15.如权利要求12所述的半导体结构，其中，该多个背侧导电接触是沿位于该晶体管的通道区中以及源汲区下方的该晶体管的长度或该晶体管的宽度；以及该多个背侧导电接触完全穿过绝缘体层形成并与其中直接形成有该晶体管的一部分的半导体材料层接触。
16.如权利要求12所述的半导体结构，其中，该多个背侧导电接触位于掩埋氧化物层中，与形成有该晶体管的半导体材料层直接接触。
17.如权利要求12所述的半导体结构，其中，该多个背侧导电接触位于掩埋氧化物层中，与形成有该晶体管的半导体材料层的底部表面隔开。
18.如权利要求12所述的半导体结构，其中，该多个背侧导电接触形成于晶圆中，通过绝缘材料与半导体材料层隔开。
19.一种半导体结构，包括：
晶体管，设于晶圆上；
第一背侧导电区，位于该晶体管的第一边缘下方；
第二背侧导电区，延伸于该晶体管的第二边缘下方；
一个或多个多背侧导电区，位于该晶体管的通道区下方；以及
电压偏压，自该晶圆的前侧与各该第一、第二以及一个或多个多背侧导电区连接，向该晶体管的本体提供不同位置的不同偏压。
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Address after: California, USA

Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Patentee before: GLOBALFOUNDRIES Inc.