CN107180815B - 具有分散式配线的芯片结构 - Google Patents

具有分散式配线的芯片结构 Download PDF

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CN107180815B
CN107180815B CN201710135008.2A CN201710135008A CN107180815B CN 107180815 B CN107180815 B CN 107180815B CN 201710135008 A CN201710135008 A CN 201710135008A CN 107180815 B CN107180815 B CN 107180815B
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wiring level
wiring
silicon
chip structure
substrate
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CN107180815A (zh
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安东尼·K·史塔佩尔
兰迪·L·沃夫
马克·D·贾菲
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GlobalFoundries US Inc
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Abstract

本发明涉及具有分散式配线的芯片结构，其包括分散式配线布局的芯片结构，以及用以形成此类芯片结构的制作方法。形成包括多个第一装置区及多个第二装置区的装置结构。形成包括与该多个第一装置区耦合的第一电线的第一配线阶。形成包括与该多个第二装置区耦合的第二电线的第二配线阶。该第一配线阶通过该绝缘体上硅衬底的埋置型氧化物层与该第二配线阶垂直分开。

Description

具有分散式配线的芯片结构
技术领域
本发明大体上关于半导体装置及集成电路制作，而且尤其是有关于包括分散式配线布局的芯片结构，以及用于形成此类芯片结构的制作方法。
背景技术
互补式金属氧化物半导体(CMOS)电路系统是在行动通讯装置(例如：膝上型电脑、行动电话、平板电脑等)中用于处理传送至该等行动通讯装置及/或由其所接收的无线高频信号。该电路系统可包括高频开关，其容许高频信号由天线接收而自低杂讯放大器绕送至其它芯片电路系统，并容许高频信号自功率放大器绕送至该天线。该高频开关可包括通过CMOS制程所形成的场效晶体管堆迭或排组。
后段制程(BEOL)互连结构可用于将信号绕送至及自集成电路的主动装置，诸如CMOS集成电路的开关。此BEOL互连结构可包括嵌埋于介电层堆迭中的配线，用以建立就信号与功率界定互连网路的配线阶堆迭。此BEOL互连结构可使用镶嵌程序来制作，堆迭中的不同配线阶是个别形成。
需要具有改良型配线布局的芯片结构以及用以形成此类芯片结构的制作方法。
发明内容
在本发明的具体实施例中，提供使用绝缘体上硅衬底形成的芯片结构及用于形成芯片结构的方法。形成包括多个第一装置区及多个第二装置区的装置结构。形成包括与该多个第一装置区耦合的第一电线的第一配线阶。形成包括与该多个第二装置区耦合的第二电线的第二配线阶。该第一配线阶通过该绝缘体上硅衬底的埋置型氧化物层与该第二配线阶垂直分开。
附图说明
附图合并于本说明书的一部分并构成该部分，绘示本发明的各项具体实施例，并且连同上述对本发明的一般性说明、及下文对具体实施例提供的详细说明，目的是为了阐释本发明的具体实施例。
图1至3是根据本发明的一具体实施例，用于制作装置结构的处理方法在接连制作阶段时，衬底的一部分的截面图。
图1A是图1所示衬底部分的俯视图。
图4至5是图3后继制作阶段的截面图，其中衬底已倒置，而截面是通过开关的诸漏极区其中一者取看，而不是如图3中诸源极区其中一者。
图6至7根据本发明的一替代具体实施例的图3后继接连制作阶段的截面图。
具体实施方式
请参阅图1、1A并根据本发明的一具体实施例，绝缘体上硅(SOI)衬底可包括操作晶圆14、埋置型氧化物(BOX)层12、以及由BOX层12上薄硅层所形成的装置层10。装置层10是通过中介BOX层12与操作晶圆14分开，并且通过BOX层12与操作晶圆14电隔离。
前段(FEOL)处理是用于在SOI衬底的正面上使用装置层10制作互补式金属氧化物半导体(CMOS)场效晶体管。可配置CMOS场效晶体管以形成具有栅极突指18的RF开关，该多个栅极突指是位于交替的源极区20与漏极区22之间。源极区20是连串地配置成顺着与栅极突指16的长轴平行的方向对准的一行。漏极区22亦连串地配置成顺着与栅极突指16的长轴平行的方向对准的一行。源极区20的任何给定行是通过诸栅极突指16的一对应者下方的通道区与漏极区22的相邻行分开。浅沟槽隔离(STI)氧化物19或任何其它类型的结构及方法(例如：硅局部氧化作用(LOCOS))是用于使装置层10的SOI薄硅区与相离的SOI薄硅区电隔离。
除了CMOS技术以外，可将如本文中所述的方法及结构应用于任何类型的集成电路IC，包括但不局限于BICMOS、BIPOLAR等。可在FEOL处理期间使用装置层10制作其它类型的主动及被动装置结构，诸如双极性接面晶体管、电容器、电阻器等。
可通过沉积一或多层(例如：多晶硅)及利用光微影图型化这些层并进行蚀刻以提供平行突指来形成场效晶体管的栅极突指18。各栅极突指18包括例如金属或与金属硅化物相掺的多晶硅、或这些与其它传导材料的分层组合等导体所组成的栅极电极，并包括例如二氧化硅(SiO2)、诸如氧化铪(HfO2)的高k介电质、或这些与其它介电材料的分层组合等介电或绝缘材料所组成的栅极介电质。场效晶体管可包含NFET装置，其中源极区20与漏极区22掺有用以提供n型传导性的第五族掺质(例如：砷(As)或磷(P))。若场效晶体管装置源极是PFET装置，则源极区20与漏极区22掺有用以提供p型传导性的第三族掺质(例如：硼(B))。
在进行中段处理(MOL)前，可在装置层10的诸如源极区20、漏极区22等薄硅区、以及诸如装置层10与源极接触部36及透通接触部37耦合的区域等装置层10与接触部耦合的其它薄硅区的表面上形成硅化物层24，以降低电阻，并且得以形成包括一或多个介电层34、将电线38与装置层10的源极区20耦合的源极接触部36、以及用于将电线39与装置层10的其它薄硅区耦合的透通接触部37的配线阶。如所属技术领域已知，源极接触部36可以是孔洞或棒体。配线阶32不包括与漏极区22耦合的任何接触部。透通接触部37将会连接至最终将会用于接触源极区20的BOX层12底下的配线。互连结构可供选择地包括后段(BEOL)处理期间制作的一或多个附加配线阶40，并且其可包括用于接触封装材的接合垫42。源极区20与漏极区22可完全硅化，亦即于装置层10的这些薄硅区的整个厚度硅化，一样用以降低其电阻。BEOL配线阶的一或多者包括与透通接触部37耦合的电线39。
请参阅图2，图中相似的附图标记是指图1中相似的特征，而在处理方法的后续制作阶段，暂时操作衬底46是附接至SOI衬底的正面以建立集合体。SOI衬底与暂时操作衬底46的面对表面举例而言，可利用可回焊黏着剂(例如：HD3007聚酰亚胺)、氧化物间接合，共晶金属间接合、或所属技术领域已知的任何其它暂时接合方法来接合在一起。暂时操作衬底46可如所属技术领域已知，由硅、硅土玻璃、铝土、蓝宝石等所构成。
请参阅图3，图中相似的附图标记是指图2中相似的特征，而在处理方法的后续制作阶段，操作晶圆14是自其背面移除以曝露BOX层12。如所属技术领域已知，举例而言，通过研磨，接着进行氢氟酸蒸汽或湿式清洁自硅表面移除氧化物，然后使用氢氧化钾或氢氧化钠进行硅湿蚀刻，可移除操作晶圆14。
请参阅图4，图中相似的附图标记是指图3中相似的特征，而在处理方法的后续制作阶段，衬底倒置且漏极接触部48连至漏极区22，透通接触部50连至硅化薄硅以透通漏极接触部48至装置层10的正面，以及电线52在BOX层12的曝露表面上形成。漏极接触部48及透通接触部50穿过BOX层12及装置层10延展至漏极区22，并且将电线52与漏极区22耦合且将透通接触部50与透通接触部37耦合。可在穿过BOX层12及装置层10蚀刻达到漏极区22的各别贯孔中形成漏极接触部48及透通接触部50。漏极接触部48可延展穿过装置层10及BOX层12的相应整个厚度，以达到与漏极区22相关联的硅化物层24，或可部分蚀刻到装置层10内。漏极区22可垂直穿过装置层10向下完全硅化至BOX层12，使得漏极接触部48延展至硅化物层24。透通贯孔50、装置层10的硅化部分、及透通接触部37提供将背面电线52与SOI衬底的正面上的电线39连接的传导路径。
请参阅图5，图中相似的附图标记是指图4中相似的特征，而在处理方法的后续制作阶段，可使用背面封装。为达此目的，可在SOI衬底的背面上形成一或多个配线阶。SOI衬底的背面是至少通过BOX层12与SOI衬底的正面分开。代表性配线阶可包括一或多个介电层56、在一或多个介电层56中的接垫58、以及形成或置放于接垫58上的封装连接62。封装连接62可以是组配成用来受回焊以将芯片附接至另一衬底、铜柱型连接、或电线接合的凸块。在一具体实施例中，可省略附加配线阶。
根据本发明的具体实施例，与源极区20耦合的配线阶中的配线及与漏极区22耦合的配线阶中的配线是相对于常規布局重分布，其中互连结构的所有配线阶都位于衬底正面上(即包括装置层10的衬底的侧)。在配线布局中，包括与源极区20耦合的配线的配线阶位于SOI衬底的正面上，而包括与漏极区22耦合的配线的配线阶位于SOI衬底的背面上，使得互连配线的这些部分位于BOX层12的对立侧(例如：上面及下面)，并且各别位于栅极突指18、源极区20及漏极区22的对立侧(例如：上面及下面)。根据本发明的具体实施例，配线的重分布的作用在于降低配线密度，在本实例中，与开关的场效晶体管相关联，其降低配线电容对开关的总寄生电容的贡献度。结果是，可改善装置效能。
在一替代具体实施例中，包括与源极区20耦合的配线的配线阶可位于SOI衬底的背面上，而包括与漏极区22耦合的配线的配线阶可位于SOI衬底的正面上。
请参阅图6，图中相似的附图标记是指图4中相似的特征，而根据一替代具体实施例在处理方法的图4的后续制作阶段，衬底68是附接至衬底的背面处的BOX层12以建立集合体。BOX层12与衬底68的面对表面举例而言，可利用可回焊黏着剂(例如：HD3007聚酰亚胺)或上述的其它晶圆接合方法来接合在一起。衬底68可如所属技术领域已知，由硅、硅土玻璃等所构成。任选的介电层66可在附接衬底68前先涂敷及平坦化。
请参阅图7，其中相似的附图标记是指图6中相似的特征，而且在后续制作阶段，从集合体移除衬底46，且未干扰介于衬底68与介电层66间的接合。封装连接62是形成、或置放于接合垫42上。
在代表性具体实施例中，多突指场效晶体管是在以源极下面形成的源极电线及接触部、并以漏极上面形成的漏极电线及接触部的SOI衬底上形成。然而，本发明的具体实施例适用于用以诸如降低电线与接触电容的改善交流特性的任何多突指装置。在此一替代具体实施例中，垂直或水平多突指NPN晶体管无论是同质接面或异质接面，举例而言，都可包括自装置上面(例如：自BOX层的一侧)延展至射极指的射极接触部、以及自装置下面(例如：自BOX层的对立侧)延展至集极区段的集极接触部。在另一此类替代具体实施例中，侧向扩散金属氧化物半导体(LDMOS)装置可包括自装置上面延展的栅极接触部以及自装置下面延展的源极/漏极接触部。
本文中对“垂直”、“水平”等用语的参照属于举例，并非限制，是用来建立参考架构。“水平”一词于本文中使用时，是定义为与半导体衬底的常規平面平行的平面，与其实际三维空间方位无关。“垂直”与“正交”等词是指垂直于水平的方向，如刚才的定义。“侧向”一词是指水平平面内的维度。诸如“上面”及“下面”等词是用于指出元件或结构彼此的相对位置，而不是相对高度。
一特征可连至或与另一元件进行“连接”或“耦合”，其可直接连接或耦合至其它元件，或取而代之，可存在一或多个中介元件。如无中介元件，一特征可“直接连接”或“直接耦合”至另一元件。如有至少一个中介元件，一特征可“间接连接”或“间接耦合”至另一元件。
本发明的各项具体实施例的描述已为了说明目的而介绍，但用意不在于穷举或受限于所揭示的具体实施例。许多修改及变例对于本领域技术人员将会显而易知，但不会脱离所述具体实施例的范畴及精神。本文中使用的术语是为了最佳阐释具体实施例的原理、对市场出现的技术所作的实务应用或技术改良、或让本领域技术人员能够理解本文中所揭示的具体实施例而选择。

Claims (14)

1.一种使用绝缘体上硅衬底形成的芯片结构，该芯片结构包含：
包括多个栅极突指、多个源极区及多个漏极区的装置结构；
包括与该多个源极区耦合的第一电线的第一配线阶；以及
包括第二电线及自该第二电线延伸穿过该绝缘体上硅 衬底的埋置型氧化物层至该多个漏极区的多个接触部的第二配线阶，
其中该第一配线阶通过该绝缘体上硅衬底的该埋置型氧化物层与该第二配线阶垂直分开，该多个源极区及该多个漏极区形成于该绝缘体上硅 衬底的装置层中，各该多个漏极区包括硅 化物层，并且各该多个接触部与该多个漏极区其中一者的该硅 化物层直接耦合。
2.如权利要求1所述的芯片结构，其中该绝缘体上硅衬底的该装置层是位于该第一配线阶与该第二配线阶之间。
3.如权利要求1所述的芯片结构，更包含：
穿过介于该第一配线阶与该第二配线阶间的该绝缘体上硅衬底延展的透通接触部。
4.如权利要求1所述的芯片结构，更包含：
附接至该第一配线阶的衬底。
5.如权利要求1所述的芯片结构，更包含：
附接至该第二配线阶的衬底。
6.如权利要求1所述的芯片结构，其中该多个栅极突指是垂直位于该第一配线阶与该第二配线阶之间。
7.如权利要求6所述的芯片结构，其中该装置层是位于该第一配线阶与该第二配线阶之间，以及该多个栅极突指是通过该装置层与该第二配线阶分开。
8.如权利要求1所述的芯片结构，其中该装置结构是场效晶体管，以及各该多个源极区是通过该多个栅极突指其中一者与该多个漏极区其中一者分开。
9.如权利要求8所述的芯片结构，其中该多个栅极突指是垂直位于该第一配线阶与该第二配线阶之间。
10.一种用于使用绝缘体上硅衬底形成芯片结构的方法，该方法包含：
形成包括多个栅极突指、多个源极区及多个漏极区的装置结构；
形成包括与该多个源极区耦合的第一电线的第一配线阶；以及
形成包括第二电线以及自该第二电线延伸穿过该绝缘体上硅 衬底的埋置型氧化层至该多个漏极区的多个接触部的第二配线阶，
其中该第一配线阶通过该绝缘体上硅衬底的该埋置型氧化物层与该第二配线阶垂直分开，该多个源极区及该多个漏极区形成于该绝缘体上硅 衬底的装置层中，各该多个漏极区包括硅 化物层，并且各该多个接触部与该多个漏极区其中一者的该硅 化物层直接耦合。
11.如权利要求10所述的方法，更包含：
在形成该第二配线阶之前，先移除该绝缘体上硅衬底的操作晶圆以曝露该埋置型氧化物层；以及
形成在该埋置型氧化物层上的该第二电线。
12.如权利要求10所述的方法，更包含：
在形成该第二配线阶之后，将衬底附接至该第二配线阶。
13.如权利要求10所述的方法，更包含：
在形成该第二配线阶之后，将衬底附接至该第一配线阶。
14.如权利要求10所述的方法，其中该装置结构是场效晶体管，各该多个源极区是通过该多个栅极突指其中一者与该多个漏极区其中一者分开，以及该多个栅极突指是垂直位于该第一配线阶与该第二配线阶之间。
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