TW201803019A - 具有分散式配線的晶片結構 - Google Patents

具有分散式配線的晶片結構 Download PDF

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TW201803019A
TW201803019A TW106105902A TW106105902A TW201803019A TW 201803019 A TW201803019 A TW 201803019A TW 106105902 A TW106105902 A TW 106105902A TW 106105902 A TW106105902 A TW 106105902A TW 201803019 A TW201803019 A TW 201803019A
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安東尼Ｋ 史塔佩爾
蘭迪Ｌ 沃夫
馬克Ｄ 賈菲
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格羅方德半導體公司
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Abstract

本發明涉及具有分散式配線的晶片結構，其包括分散式配線佈局的晶片結構，以及用以形成此類晶片結構的製作方法。形成包括多個第一裝置區及多個第二裝置區的裝置結構。形成包括與該多個第一裝置區耦合的第一電線的第一配線階。形成包括與該多個第二裝置區耦合的第二電線的第二配線階。該第一配線階通過該絕緣體上矽襯底的埋置型氧化物層與該第二配線階垂直分開。

Description

具有分散式配線的晶片結構
本發明大體上關於半導體裝置及積體電路製作，而且尤其是有關於包括分散式配線佈局的晶片結構，以及用於形成此類晶片結構的製作方法。
互補式金屬氧化物半導體(CMOS)電路系統是在行動通訊裝置(例如：筆記型電腦、行動電話、平板電腦等)中用於處理傳送至該等行動通訊裝置及/或由其所接收的無線高頻信號。該電路系統可包括高頻開關，其容許高頻信號由天線接收而自低雜訊放大器繞送至其它晶片電路系統，並容許高頻信號自功率放大器繞送至該天線。該高頻開關可包括通過CMOS製程所形成的場效電晶體堆疊或排組。
後段製程(BEOL)互連結構可用於將信號繞送至及自積體電路的主動裝置，諸如CMOS積體電路的開關。此BEOL互連結構可包括嵌埋於介電層堆疊中的配線，用以建立就信號與功率界定互連網路的配線階堆疊。此BEOL互連結構可使用鑲嵌程序來製作，堆疊中的不同配線階是個別形成。
需要具有改良型配線佈局的晶片結構以及用以形成此類晶片結構的製作方法。
在本發明的具體實施例中，提供使用絕緣體上矽襯底形成的晶片結構及用於形成晶片結構的方法。形成包括多個第一裝置區及多個第二裝置區的裝置結構。形成包括與該多個第一裝置區耦合的第一電線的第一配線階。形成包括與該多個第二裝置區耦合的第二電線的第二配線階。該第一配線階通過該絕緣體上矽襯底的埋置型氧化物層與該第二配線階垂直分開。
10‧‧‧裝置層
12‧‧‧埋置型氧化物(BOX)層
14‧‧‧操作晶圓
16‧‧‧柵極突指
18‧‧‧柵極突指
19‧‧‧淺溝槽隔離(STI)氧化物
20‧‧‧源極區
22‧‧‧漏極區
24‧‧‧矽化物層
32‧‧‧配線階
34‧‧‧介電層
36‧‧‧源極接觸部
37‧‧‧透通接觸部
38‧‧‧電線
39‧‧‧電線
40‧‧‧附加配線階
42‧‧‧接合墊
46‧‧‧襯底
48‧‧‧漏極接觸部
50‧‧‧透通接觸部
52‧‧‧電線
56‧‧‧介電層
58‧‧‧接墊
62‧‧‧封裝連接
66‧‧‧介電層
68‧‧‧襯底
附圖合併於本說明書的一部分並構成該部分，繪示本發明的各項具體實施例，並且連同上述對本發明的一般性說明、及下文對具體實施例提供的詳細說明，目的是為了闡釋本發明的具體實施例。
第1至3圖是根據本發明的一具體實施例，用於製作裝置結構的處理方法在接連製作階段時，襯底的一部分的截面圖。
第1A圖是第1圖所示襯底部分的俯視圖。
第4至5圖是第3圖後繼製作階段的截面圖，其中襯底已倒置，而截面是通過開關的諸漏極區其中一者取看，而不是如第3圖中諸源極區其中一者。
第6至7圖根據本發明的一替代具體實施例的第3圖後繼接連製作階段的截面圖。
請參閱第1圖、第1A圖並根據本發明的一具體實施例，絕緣體上矽(SOI)襯底可包括操作晶圓14、埋置型氧化物(BOX)層12、以及由BOX層12上薄矽層所形成的裝置層10。裝置層10是通過中介BOX層12與操作晶圓14分開，並且通過BOX層12與操作晶圓14電隔離。
前段(FEOL)處理是用於在SOI襯底的正面上使用裝置層10製作互補式金屬氧化物半導體(CMOS)場效電晶體。可配置CMOS場效電晶體以形成具有柵極突指18的RF開關，該多個柵極突指是位於交替的源極區20與漏極區22之間。源極區20是串聯地配置成順著與柵極突指16的長軸平行的方向對準的一列。漏極區22亦串聯地配置成順著與柵極突指16的長軸平行的方向對準的一列。源極區20的任何給定列是通過諸柵極突指16的一對應者下方的通道區與漏極區22的相鄰行分開。淺溝槽隔離(STI)氧化物19或任何其它類型的結構及方法(例如：矽局部氧化作用(LOCOS))是用於使裝置層10的SOI薄矽區與相離的SOI薄矽區電隔離。
除了CMOS技術以外，可將如本文中所述的方法及結構應用於任何類型的積體電路IC，包括但不局限於BICMOS、BIPOLAR等。可在FEOL處理期間使用裝置層10製作其它類型的主動及被動裝置結構，諸如雙極性接面電晶體、電容器、電阻器等。
可通過沉積一或多層(例如：多晶矽)及利 用光微影圖型化這些層並進行蝕刻，以提供平行突指來形成場效電晶體的柵極突指18。各柵極突指18包括例如金屬或與金屬矽化物相摻的多晶矽、或這些與其它傳導材料的分層組合等導體所組成的柵極電極，並包括例如二氧化矽(SiO2)、諸如氧化鉿(HfO2)的高k介電質、或這些與其它介電材料的分層組合等介電或絕緣材料所組成的柵極介電質。場效電晶體可包含NFET裝置，其中，源極區20與漏極區22摻有用以提供n型傳導性的第五族摻質(例如：砷(As)或磷(P))。若場效電晶體裝置源極是PFET裝置，則源極區20與漏極區22摻有用以提供p型傳導性的第三族摻質(例如：硼(B))。
在進行中段處理(MOL)前，可在裝置層10的諸如源極區20、漏極區22等薄矽區、以及諸如裝置層10與源極接觸部36及透通接觸部37耦合的區域等裝置層10與接觸部耦合的其它薄矽區的表面上形成矽化物層24，以降低電阻，並且得以形成包括一或多個介電層34、將電線38與裝置層10的源極區20耦合的源極接觸部36、以及用於將電線39與裝置層10的其它薄矽區耦合的透通接觸部37的配線階。如所屬技術領域已知，源極接觸部36可以是孔洞或棒體。配線階32不包括與漏極區22耦合的任何接觸部。透通接觸部37將會連接至最終將會用於接觸源極區20的BOX層12底下的配線。互連結構可供選擇地包括後段(BEOL)處理期間製作的一或多個附加配線階40，並且其可包括用於接觸封裝材的接合墊42。源極區20與漏極 區22可完全矽化，亦即於裝置層10的這些薄矽區的整個厚度矽化，一樣用以降低其電阻。BEOL配線階的一或多者包括與透通接觸部37耦合的電線39。
請參閱第2圖，圖中相似的附圖標記是指第1圖中相似的特徵，而在處理方法的後續製作階段，暫時操作襯底46是附接至SOI襯底的正面以建立集合體。SOI襯底與暫時操作襯底46的面對表面舉例而言，可利用可回焊黏著劑(例如：HD3007聚醯亞胺)、氧化物間接合、共晶金屬間接合、或所屬技術領域已知的任何其它暫時接合方法來接合在一起。暫時操作襯底46可如所屬技術領域已知，由矽、矽土玻璃、鋁土、藍寶石等所構成。
請參閱第3圖，圖中相似的附圖標記是指第2圖中相似的特徵，而在處理方法的後續製作階段，操作晶圓14是自其背面移除以曝露BOX層12。如所屬技術領域已知，舉例而言，通過研磨，接著進行氫氟酸蒸汽或濕式清潔自矽表面移除氧化物，然後使用氫氧化鉀或氫氧化鈉進行矽濕蝕刻，可移除操作晶圓14。
請參閱第4圖，圖中相似的附圖標記是指第3圖中相似的特徵，而在處理方法的後續製作階段，襯底倒置且漏極接觸部48連至漏極區22，透通接觸部50連至矽化薄矽以透通漏極接觸部48至裝置層10的正面，並且電線52在BOX層12的曝露表面上形成。漏極接觸部48及透通接觸部50穿過BOX層12及裝置層10延展至漏極區22，並且將電線52與漏極區22耦合且將透通接觸部50 與透通接觸部37耦合。可在穿過BOX層12及裝置層10蝕刻達到漏極區22的各別貫孔中形成漏極接觸部48及透通接觸部50。漏極接觸部48可延展穿過裝置層10及BOX層12的相應整個厚度，以達到與漏極區22相關聯的矽化物層24，或可部分蝕刻到裝置層10內。漏極區22可垂直穿過裝置層10向下完全矽化至BOX層12，使得漏極接觸部48延展至矽化物層24。透通貫孔50、裝置層10的矽化部分、及透通接觸部37提供將背面電線52與SOI襯底的正面上的電線39連接的傳導路徑。
請參閱第5圖，圖中相似的附圖標記是指第4圖中相似的特徵，而在處理方法的後續製作階段，可使用背面封裝。為達此目的，可在SOI襯底的背面上形成一或多個配線階。SOI襯底的背面是至少通過BOX層12與SOI襯底的正面分開。代表性配線階可包括一或多個介電層56、在一或多個介電層56中的接墊58、以及形成或置放於接墊58上的封裝連接62。封裝連接62可以是組配成用來受回焊以將晶片附接至另一襯底、銅柱型連接、或電線接合的凸塊。在一具體實施例中，可省略附加配線階。
根據本發明的具體實施例，與源極區20耦合的配線階中的配線及與漏極區22耦合的配線階中的配線是相對於常規佈局重分佈，其中互連結構的所有配線階都位於襯底正面上(即包括裝置層10的襯底的側)。在配線佈局中，包括與源極區20耦合的配線的配線階位於SOI襯底的正面上，而包括與漏極區22耦合的配線的配線階則 位於SOI襯底的背面上，使得互連配線的這些部分位於BOX層12的對立側(例如：上面及下面)，並且各別位於柵極突指18、源極區20及漏極區22的對立側(例如：上面及下面)。根據本發明的具體實施例，配線的重分佈的作用在於降低配線密度，在本實例中，與開關的場效電晶體相關聯，其降低配線電容對開關的總寄生電容的貢獻度。結果是，可改善裝置效能。
在一替代具體實施例中，包括與源極區20耦合的配線的配線階可位於SOI襯底的背面上，而包括與漏極區22耦合的配線的配線階可位於SOI襯底的正面上。
請參閱第6圖，圖中相似的附圖標記是指第4圖中相似的特徵，而根據一替代具體實施例在處理方法的第4圖的後續製作階段，襯底68是附接至襯底的背面處的BOX層12以建立集合體。BOX層12與襯底68的面對表面舉例而言，可利用可回焊黏著劑(例如：HD3007聚醯亞胺)或上述的其它晶圓接合方法來接合在一起。襯底68可如所屬技術領域已知，由矽、矽土玻璃等所構成。任選的介電層66可在附接襯底68前先塗敷及平坦化。
請參閱第7圖，其中相似的附圖標記是指第6圖中相似的特徵，而且在後續製作階段，從集合體移除襯底46，且未干擾介於襯底68與介電層66間的接合。封裝連接62是形成、或置放於接合墊42上。
在代表性具體實施例中，多突指場效電晶體是在以源極下面形成的源極電線及接觸部、並以漏極上面 形成的漏極電線及接觸部的SOI襯底上形成。然而，本發明的具體實施例適用於用以諸如降低電線與接觸電容的改善交流特性的任何多突指裝置。在此一替代具體實施例中，垂直或水平多突指NPN電晶體無論是同質接面或異質接面，舉例而言，都可包括自裝置上面(例如：自BOX層的一側)延展至射極指的射極接觸部、以及自裝置下面(例如：自BOX層的對立側)延展至集極區段的集極接觸部。在另一此類替代具體實施例中，側向擴散金屬氧化物半導體(LDMOS)裝置可包括自裝置上面延展的柵極接觸部以及自裝置下面延展的源極/漏極接觸部。
本文中對“垂直”、“水平”等用語的參照屬於舉例，並非限制，是用來建立參考架構。“水平”一詞於本文中使用時，是定義為與半導體襯底的常規平面平行的平面，與其實際三維空間方位無關。“垂直”與“正交”等詞是指垂直於水平的方向，如剛才的定義。“側向”一詞是指水平平面內的維度。諸如“上面”及“下面”等詞是用於指出元件或結構彼此的相對位置，而不是相對高度。
一特徵可連至或與另一元件進行“連接”或“耦合”，其可直接連接或耦合至其它元件，或取而代之，可存在一或多個中介元件。如無中介元件，一特徵可“直接連接”或“直接耦合”至另一元件。如有至少一個中介元件，一特徵可“間接連接”或“間接耦合”至另一元件。
本發明的各項具體實施例的描述已為了說明 目的而介紹，但用意不在於窮舉或受限於所揭示的具體實施例。許多修改及變例對於本領域技術人員將會顯而易知，但不會脫離所述具體實施例的範疇及精神。本文中使用的術語是為了最佳闡釋具體實施例的原理、對市場出現的技術所作的實務應用或技術改良、或讓本領域技術人員能夠理解本文中所揭示的具體實施例而選擇。
10‧‧‧裝置層
12‧‧‧埋置型氧化物(BOX)層
14‧‧‧操作晶圓
18‧‧‧柵極突指
19‧‧‧淺溝槽隔離(STI)氧化物
20‧‧‧源極區
22‧‧‧漏極區
24‧‧‧矽化物層
34‧‧‧介電層
36‧‧‧源極接觸部
37‧‧‧透通接觸部
38‧‧‧電線
39‧‧‧電線
40‧‧‧附加配線階
42‧‧‧接合墊

Claims (20)

  1. 一種晶片結構，使用絕緣體上矽襯底所形成，該晶片結構包含：裝置結構，包括多個第一裝置區及多個第二裝置區；第一配線階，包括與該多個第一裝置區耦合的第一電線；以及第二配線階，包括與該多個第二裝置區耦合的第二電線，其中，該第一配線階由該絕緣體上矽襯底的埋置型氧化物層與該第二配線階垂直分開。
  2. 如申請專利範圍第1項所述的晶片結構，其中，該裝置結構是使用該絕緣體上矽襯底位於該第一配線階與該第二配線階間的裝置層的區域所形成。
  3. 如申請專利範圍第1項所述的晶片結構，復包含：多個接觸部，在自該第一電線延展穿過該埋置型氧化物層至該多個第一裝置區的各別貫孔中，該多個接觸部將該第二電線與該多個第一裝置區耦合。
  4. 如申請專利範圍第3項所述的晶片結構，其中，各該多個第一裝置區復包括與各別該接觸部耦合的矽化物層。
  5. 如申請專利範圍第1項所述的晶片結構，復包含：透通接觸部，在該第一配線階與該第二配線階之間延展穿過該絕緣體上矽襯底。
  6. 如申請專利範圍第1項所述的晶片結構，復包含： 襯底，附接至該第一配線階。
  7. 如申請專利範圍第1項所述的晶片結構，復包含：襯底，附接至該第二配線階。
  8. 如申請專利範圍第1項所述的晶片結構，其中，該裝置結構包括多個突指，並且該多個突指是垂直位於該第一配線階與該第二配線階之間。
  9. 如申請專利範圍第8項所述的晶片結構，其中，該絕緣體上矽襯底包括裝置層，該多個第一裝置區及該多個第二裝置區是於該裝置層中形成，該裝置層是位於該第一配線階與該第二配線階之間，並且該多個突指是由該裝置層與該第一配線階分開。
  10. 如申請專利範圍第8項所述的晶片結構，復包含：多個接觸部，在自該第一電線延展穿過該埋置型氧化物層至該多個第一裝置區的各別貫孔中，該多個接觸部將該第二電線與該多個第一裝置區耦合。
  11. 如申請專利範圍第1項所述的晶片結構，其中，該裝置結構是包括多個柵極突指的場效電晶體，該多個第一裝置區包含多個源極區，該多個第二裝置區包含多個漏極區，並且各該多個源極區是由一個該多個柵極突指與一個該多個漏極區分開。
  12. 如申請專利範圍第11項所述的晶片結構，其中，該多個柵極突指是垂直位於該第一配線階與該第二配線階之間。
  13. 如申請專利範圍第11項所述的晶片結構，復包含： 多個接觸部，在從該第一電線延展穿過該埋置型氧化物層至該多個源極區的各別貫孔中，該多個接觸部將該第二電線與該多個源極區耦合。
  14. 如申請專利範圍第11項所述的晶片結構，復包含：多個接觸部，在自該第一電線延展穿過該埋置型氧化物層至該多個漏極區的各別貫孔中，該多個接觸部將該第二電線與該多個漏極區耦合。
  15. 一種形成晶片結構的方法，該晶片結構使用絕緣體上矽襯底，該方法包含：形成包括多個突指、多個第一裝置區及多個第二裝置區的裝置結構；形成包括與該多個第一裝置區耦合的第一電線的第一配線階；以及形成包括與該多個第二裝置區耦合的第二電線的第二配線階，其中，該第一配線階由該絕緣體上矽襯底的埋置型氧化物層與該第二配線階垂直分開。
  16. 如申請專利範圍第15項所述的方法，其中，該多個第一裝置區與該多個第二裝置區是使用該絕緣體上矽襯底的裝置層所形成，並且復包含：在形成該第一配線階之前，先移除該絕緣體上矽襯底的操作晶圓以曝露該埋置型氧化物層；以及形成在該埋置型氧化物層上的該第一電線。
  17. 如申請專利範圍第16項所述的方法，其中，形成該第 一配線階復包含：形成穿過該埋置型氧化物層延展至該多個第一裝置區的多個貫孔；以及在將該第一電線與該多個第一裝置區耦合的該多個貫孔中形成接觸部。
  18. 如申請專利範圍第15項所述的方法，復包含：在形成該第二配線階之後，將襯底附接至該第二配線階。
  19. 如申請專利範圍第15項所述的方法，復包含：在形成該第二配線階之後，將襯底附接至該第一配線階。
  20. 如申請專利範圍第15項所述的方法，其中，該裝置結構是包括多個柵極突指的場效電晶體，該多個第一裝置區包含多個源極區，該多個第二裝置區包含多個漏極區，各該多個源極區是由一個該多個柵極突指與一個該多個漏極區分開，並且該多個柵極突指是垂直位於該第一配線階與該第二配線階之間。
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