CN115548117A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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CN115548117A
CN115548117A CN202110725291.0A CN202110725291A CN115548117A CN 115548117 A CN115548117 A CN 115548117A CN 202110725291 A CN202110725291 A CN 202110725291A CN 115548117 A CN115548117 A CN 115548117A
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layer
silicon
substrate
dielectric layer
semiconductor structure
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张晟
祁春媛
陈星星
冯健奇
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United Microelectronics Corp
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Abstract

本发明公开一种半导体结构及其制造方法。所述半导体结构包括承载基底、富陷阱层、介电层、内连线结构、元件结构层以及线路结构。所述富陷阱层设置于所述承载基底上。所述介电层设置于所述富陷阱层上。所述内连线结构设置于所述介电层上。所述元件结构层设置于所述内连线结构上，且与所述内连线结构电连接。所述线路结构设置于所述元件结构层上，且与所述元件结构层电连接。

Description

半导体结构及其制造方法
技术领域
本发明涉及一种半导体结构及其制造方法，且特别是涉及一种可改善绝缘层覆硅(silicon-on-insulator，SOI)基底的寄生表面传导(parasitic surface conducting)效应的半导体结构及其制造方法。
背景技术
一般来说。绝缘层覆硅基底由硅基体(silicon base)以及依序设置于硅基体上的介电层以及硅层构成。对于设置于绝缘层覆硅基底上的电子元件(例如金属氧化物半导体(MOS)晶体管)来说，在对所述电子元件进行操作时，在硅基体与绝缘层的界面处往往会聚集过多的载流子(carrier)。举例来说，带正电荷的载流子通常会存在绝缘层的靠近硅基体的区域中，因此在对电子元件的操作过程中，这些带正电荷的载流子会将硅基体中的带负电荷的载流子吸引至硅基体与绝缘层的界面处，造成所谓的寄生表面传导效应。寄生表面传导效应会在硅基体与绝缘层的界面处产生累积导电层(accumulation conductivelayer)，造成电子元件的电信号损失，例如造成总谐波失真(total harmonic distortion，THD)的问题。
发明内容
本发明提供一种半导体结构，其包括设置于基底上的富陷阱层(trap-richlayer)。
本发明提供一种半导体结构的制造方法，其通过将两个基底接合的方式来形成，且富陷阱层形成于一个基底上。
本发明的半导体结构包括承载基底、富陷阱层、介电层、内连线结构、元件结构层以及线路结构。所述富陷阱层设置于所述承载基底上。所述介电层设置于所述富陷阱层上。所述内连线结构设置于所述介电层上。所述元件结构层设置于所述内连线结构上，且与所述内连线结构电连接。所述线路结构设置于所述元件结构层上，且与所述元件结构层电连接。
在本发明的半导体结构的一实施例中，所述富陷阱层包括多晶硅(polysilicon)层、非晶硅(amorphous silicon)层、氮化硅层、氮碳化硅(SiCN)层或其组合。
在本发明的半导体结构的一实施例中，所述富陷阱层的厚度介于
Figure BDA0003138364130000021
至
Figure BDA0003138364130000022
之间。
在本发明的半导体结构的一实施例中，所述介电层包括氧化硅层。
在本发明的半导体结构的一实施例中，所述介电层的厚度介于
Figure BDA0003138364130000023
至
Figure BDA0003138364130000024
之间。
在本发明的半导体结构的一实施例中，所述承载基底包括硅基底。
本发明的半导体结构的制造方法包括以下步骤。在承载基底上形成富陷阱层。在所述富陷阱层上形成第一介电层。将所述第一介电层平坦化。在绝缘层覆硅基底上形成元件结构层，其中所述绝缘层覆硅基底包括硅基体以及依序堆叠于所述硅基底上的绝缘层以及硅层。在所述元件结构层上形成内连线结构，其中所述内连线结构与所述元件结构层电连接。于所述内连线结构上形成第二介电层。以所述第一介电层朝向所述第二介电层的方式接合所述承载基底与所述绝缘层覆硅基底。移除所述绝缘层覆硅基底的所述硅基体。在所述绝缘层上形成线路结构，其中所述线路结构与所述元件结构层电连接。
在本发明的半导体结构的制造方法的一实施例中，所述富陷阱层包括多晶硅层、非晶硅层、氮化硅层、氮碳化硅层或其组合。
在本发明的半导体结构的制造方法的一实施例中，所述富陷阱层的厚度介于
Figure BDA0003138364130000025
至
Figure BDA0003138364130000026
之间。
在本发明的半导体结构的制造方法的一实施例中，经平坦化的所述第一介电层的厚度介于
Figure BDA0003138364130000027
至
Figure BDA0003138364130000028
之间。
在本发明的半导体结构的制造方法的一实施例中，所述第一介电层包括氧化硅层。
在本发明的半导体结构的制造方法的一实施例中，所述第二介电层包括氧化硅层。
在本发明的半导体结构的制造方法的一实施例中，所述承载基底包括硅基底。
在本发明的半导体结构的制造方法的一实施例中，所述第一介电层平坦化的方法包括进行化学机械研磨制作工艺。
在本发明的半导体结构的制造方法的一实施例中，移除所述绝缘层覆硅基底的所述硅基体的方法包括以下步骤。将所述硅基体薄化。对经薄化的所述硅基体进行蚀刻制作工艺。
基于上述，在本发明的半导体结构中，富陷阱层设置于承载基底与介电层之间，因此在对半导体元件进行操作时，可通过富陷阱层捕获来自承载基底中的带负电荷的载流子并降低这些带负电荷的载流子的移动能力，以避免这些带负电荷的载流子与介电层中的带正电荷的载流子聚集而产生累积导电层，进而可有效地避免电信号的损失。
此外，在制造本发明的半导体结构时，在承载基底上依序形成富陷阱层以及第一介电层之后，将第一介电层平坦化。因此，第一介电层可具有较低的表面粗糙度，以利后续接合制作工艺的进行。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1F为本发明实施例所绘示的半导体结构的制造流程剖面示意图。
具体实施方式
下文列举实施例并配合附图来进行详细地说明，但所提供的实施例并非用以限制本发明所涵盖的范围。此外，附图仅以说明为目的，并未依照原尺寸作图。为了方便理解，在下述说明中相同的元件将以相同的符号标示来说明。
关于本文中所提到「包含」、「包括」、「具有」等的用语均为开放性的用语，也就是指「包含但不限于」。
此外，文中所提到「上」、「下」等的方向性用语，仅是用以参考图式的方向，并非用以限制本发明。
当以「第一」、「第二」等的用语来说明元件时，仅用于将这些元件彼此区分，并不限制这些元件的顺序或重要性。因此，在一些情况下，第一元件也可称作第二元件，第二元件也可称作第一元件，且此不偏离本发明的范畴。
在本文中，由「一数值至另一数值」表示的范围是一种避免在说明书中逐一列举所述范围中的所有数值的概要性表示方式。因此，某一特定数值范围的记载涵盖了所述数值范围内的任意数值，以及涵盖由所述数值范围内的任意数值界定出的较小数值范围。
图1A至图1F为依照本发明实施例所绘示的半导体结构的制造流程剖面示意图。
首先，参照图1A，提供承载基底100。在本实施例中，承载基底100例如为硅基底。在一实施例中，承载基底100可为硅晶片。然后，在承载基底100上形成富陷阱层102。在本实施例中，富陷阱层102例如为多晶硅层、非晶硅层、氮化硅层、氮碳化硅层或其组合。富陷阱层102的厚度例如介于
Figure BDA0003138364130000041
至
Figure BDA0003138364130000042
之间。在本实施例中，富陷阱层102的形成方法例如是进行化学气相沉积(chemical vapor deposition，CVD)制作工艺，但本发明不限于此。在对半导体元件进行操作的过程中，富陷阱层102可捕获载流子，并降低这些载流子的移动能力。接着，在富陷阱层102上形成第一介电层104。在本实施例中，第一介电层104例如为氧化硅层。第一介电层104的厚度例如介于
Figure BDA0003138364130000043
至
Figure BDA0003138364130000044
之间。在本实施例中，第一介电层104的形成方法例如是进行化学气相沉积制作工艺，但本发明不限于此。
然后，参照图1B，将第一介电层104平坦化，并同时减少第一介电层104的厚度，以形成第一介电层104a。将第一介电层104平坦化的方法例如是进行学机械研磨(chemicalmechanical process，CMP)制作工艺，但本发明不限于此。第一介电层104a的厚度例如介于
Figure BDA0003138364130000045
至
Figure BDA0003138364130000046
之间。第一介电层104经平坦化之后可具有较低的表面粗糙度(surfaceroughness)，以利后续接合(bonding)制作工艺的进行。特别是，在富陷阱层102为多晶硅层的情况下，由于多晶硅层本身的材料特性会造成上方的膜层具有较高的表面粗糙度，因此在进行上述平坦化制作工艺之后可有效地降低第一介电层104a的表面粗糙度，以利后续接合制作工艺的进行。
接着，参照图1C，提供绝缘层覆硅基底200。绝缘层覆硅基底200包括硅基体200a以及依序堆叠于硅基体200a上的绝缘层200b以及硅层200c。一般来说，硅基体200a可掺杂有P型掺质且较佳具有约
Figure BDA0003138364130000047
的厚度，绝缘层200b较佳具有约大于2μm的厚度，而硅层200c例如可掺杂有P型掺质且较佳具有约大于0.5μm的厚度，但本发明不限于此。在本实施例中，绝缘层200b例如为氧化硅层。在本实施例中，绝缘层覆硅基底200具有彼此相对的第一表面201与第二表面203。在此阶段，第一表面201为半导体元件形成于其上的正面(也可称为主动表面)，亦即硅层200c暴露出来的顶面，而第二表面203则为背面，亦即硅基体200a暴露出来的底面。
然后，在硅层200c中形成隔离结构205，以定义出主动区(active area，AA)。隔离结构205例如是浅沟槽隔离(shallow trench isolation，STI)结构。在本实施例中，隔离结构205的厚度与硅层200c的厚度相同，即隔离结构205贯穿硅层200c，使得相邻的主动区之间能够有效地隔离开来。隔离结构205的形成方法为本领域技术人员所熟知，在此不另行说明。接着，在绝缘层覆硅基底200的第一表面201上形成元件结构层202。元件结构层202包括本领域技术人员所熟知的各种半导体元件，本发明不对此进行限定。举例来说，在本实施例中，元件结构层202包括形成于隔离结构205之间的主动表面(第一表面101)上的晶体管202a以及覆盖晶体管202a的介电层202b，但本发明不限于此。
接着，参照图1D，在元件结构层202上形成内连线结构204。在本实施例中，内连线结构204包括介电层204a、多层线路层204b、导通孔(via)204c以及接触窗(contact)204d。介电层204a形成于元件结构层202上。多层线路层204b以及导通孔204c形成于介电层204a中，其中导通孔204c连接相邻两层的线路层204b。接触窗204d延伸至元件结构层202中而连接晶体管202a与最下层的线路层204b。内连线结构204的详细架构以及形成方法为本领域技术人员所熟知，在此不再另行说明。
然后，在内连线结构204上形成第二介电层206。在本实施例中，第二介电层206例如为氧化硅层。第二介电层206的厚度例如介于
Figure BDA0003138364130000051
至
Figure BDA0003138364130000052
之间。在本实施例中，第二介电层206的形成方法例如是进行化学气相沉积制作工艺，但本发明不限于此。在形成第二介电层206之后，视实际需求，可对第二介电层206进行化学机械研磨制作工艺，以进一步减少第二介电层206的厚度以及表面粗糙度。
接着，参照图1E，以第一介电层104a朝向第二介电层206的方式，将承载基底100与绝缘层覆硅基底200接合在一起。在本实施例中，将承载基底100与绝缘层覆硅基底200接合的方式例如是进行热压合制作工艺。当第一介电层104a与第二介电层206的材料相同时，在接合之后，第一介电层104a与第二介电层206可能不存在界面。当第一介电层104a与第二介电层206的材料不同时，在接合之后，第一介电层104a与第二介电层206则会存在界面。在本实施例中，第一介电层104a与第二介电层206在接合之后的总厚度例如介于
Figure BDA0003138364130000061
至
Figure BDA0003138364130000062
之间。
之后，参照图1F，移除绝缘层覆硅基底200的硅基体200a，以暴露出绝缘层200b。在本实施例中，移除绝缘层覆硅基底200的硅基体200a的方法例如是先将硅基体200a薄化，然后对经薄化的硅基体200a进行蚀刻制作工艺，但本发明不限于此。在其他实施例中，可直接进行研磨(grinding)制作工艺来移除硅基体200a。在一实施例中，将硅基体200a薄化的方法例如是进行研磨制作工艺。此外，在一实施例中，上述的蚀刻制作工艺例如是TEMA湿式蚀刻制作工艺。
接着，于绝缘层200b上形成线路结构208。在本实施例中，线路结构208包括线路层208a以及导通孔208b，但本发明不限于此。线路层208a形成于绝缘层200b上。在本实施例中，导通孔208b与线路层208a连接，且自线路层208a延伸穿过绝缘层200b、硅层200c以及元件结构层202而与内连线结构204的线路层204b连接，但本发明不限于此。因此，线路结构208可与元件结构层202电连接。如此一来，形成了本实施例的半导体结构10。
在本实施例的半导体结构10中，富陷阱层102设置于硅基底(承载基底100)与第一介电层104a之间。由于硅基底(承载基底100)与第一介电层104a之间设置有富陷阱层102，因此在对半导体元件进行操作时，可通过富陷阱层102捕获来自硅基底(承载基底100)中的带负电荷的载流子并降低这些带负电荷的载流子的移动能力，以避免这些带负电荷的载流子与第一介电层104a中的带正电荷的载流子聚集而产生累积导电层，进而可有效地避免电信号的损失。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (15)

1.一种半导体结构，包括：
承载基底；
富陷阱层，设置于所述承载基底上；
介电层，设置于所述富陷阱层上；
内连线结构，设置于所述介电层上；
元件结构层，设置于所述内连线结构上，且与所述内连线结构电连接；以及
线路结构，设置于所述元件结构层上，且与所述元件结构层电连接。
2.如权利要求1所述的半导体结构，其中所述富陷阱层包括多晶硅层、非晶硅层、氮化硅层、氮碳化硅层或其组合。
3.如权利要求1所述的半导体结构，其中所述富陷阱层的厚度介于
Figure FDA0003138364120000011
Figure FDA0003138364120000012
至
Figure FDA0003138364120000013
之间。
4.如权利要求1所述的半导体结构，其中所述介电层包括氧化硅层。
5.如权利要求1所述的半导体结构，其中所述介电层的厚度介于
Figure FDA0003138364120000014
Figure FDA0003138364120000015
至
Figure FDA0003138364120000016
之间。
6.如权利要求1所述的半导体结构，其中所述承载基底包括硅基底。
7.一种半导体结构的制造方法，包括：
在承载基底上形成富陷阱层；
在所述富陷阱层上形成第一介电层；
将所述第一介电层平坦化；
在绝缘层覆硅基底上形成元件结构层，其中所述绝缘层覆硅基底包括硅基体以及依序堆叠于所述硅基体上的绝缘层以及硅层；
在所述元件结构层上形成内连线结构，其中所述内连线结构与所述元件结构层电连接；
在所述内连线结构上形成第二介电层；
以所述第一介电层朝向所述第二介电层的方式接合所述承载基底与所述绝缘层覆硅基底；
移除所述绝缘层覆硅基底的所述硅基体；以及
在所述绝缘层上形成线路结构，其中所述线路结构与所述元件结构层电连接。
8.如权利要求7所述的半导体结构的制造方法，其中所述富陷阱层包括多晶硅层、非晶硅层、氮化硅层、氮碳化硅层或其组合。
9.如权利要求7所述的半导体结构的制造方法，其中所述富陷阱层的厚度介于
Figure FDA0003138364120000021
至
Figure FDA0003138364120000022
之间。
10.如权利要求7所述的半导体结构的制造方法，其中经平坦化的所述第一介电层的厚度介于
Figure FDA0003138364120000023
至
Figure FDA0003138364120000024
之间。
11.如权利要求7所述的半导体结构的制造方法，其中所述第一介电层包括氧化硅层。
12.如权利要求7所述的半导体结构的制造方法，其中所述第二介电层包括氧化硅层。
13.如权利要求7所述的半导体结构的制造方法，其中所述承载基底包括硅基底。
14.如权利要求7所述的半导体结构的制造方法，其中将所述第一介电层平坦化的方法包括进行化学机械研磨制作工艺。
15.如权利要求7所述的半导体结构的制造方法，其中移除所述绝缘层覆硅基底的所述硅基体的方法包括：
将所述硅基体薄化；以及
对经薄化的所述硅基体进行蚀刻制作工艺。
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