FR2894069B1 - Fabrication de transistors mos - Google Patents

Fabrication de transistors mos

Info

Publication number
FR2894069B1
FR2894069B1 FR0553615A FR0553615A FR2894069B1 FR 2894069 B1 FR2894069 B1 FR 2894069B1 FR 0553615 A FR0553615 A FR 0553615A FR 0553615 A FR0553615 A FR 0553615A FR 2894069 B1 FR2894069 B1 FR 2894069B1
Authority
FR
France
Prior art keywords
manufacturing
mos transistors
mos
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0553615A
Other languages
English (en)
Other versions
FR2894069A1 (fr
Inventor
Philippe Coronel
Claire Gallon
Beranger Claire Fenouillet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, STMicroelectronics Crolles 2 SAS filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR0553615A priority Critical patent/FR2894069B1/fr
Priority to US11/604,462 priority patent/US7556995B2/en
Publication of FR2894069A1 publication Critical patent/FR2894069A1/fr
Application granted granted Critical
Publication of FR2894069B1 publication Critical patent/FR2894069B1/fr
Priority to US12/412,381 priority patent/US7915110B2/en
Priority to US13/114,184 priority patent/US8369519B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
FR0553615A 2005-11-28 2005-11-28 Fabrication de transistors mos Expired - Fee Related FR2894069B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0553615A FR2894069B1 (fr) 2005-11-28 2005-11-28 Fabrication de transistors mos
US11/604,462 US7556995B2 (en) 2005-11-28 2006-11-27 MOS transistor manufacturing
US12/412,381 US7915110B2 (en) 2005-11-28 2009-03-27 MOS transistor manufacturing
US13/114,184 US8369519B2 (en) 2005-11-28 2011-05-24 Scrambling of a calculation performed according to an RSA-CRT algorithm

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0553615A FR2894069B1 (fr) 2005-11-28 2005-11-28 Fabrication de transistors mos

Publications (2)

Publication Number Publication Date
FR2894069A1 FR2894069A1 (fr) 2007-06-01
FR2894069B1 true FR2894069B1 (fr) 2008-02-22

Family

ID=36754305

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0553615A Expired - Fee Related FR2894069B1 (fr) 2005-11-28 2005-11-28 Fabrication de transistors mos

Country Status (2)

Country Link
US (2) US7556995B2 (fr)
FR (1) FR2894069B1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006070310A1 (fr) * 2004-12-28 2006-07-06 Koninklijke Philips Electronics N.V. Procede de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur obtenu a l'aide de ce procede
US7759755B2 (en) * 2008-05-14 2010-07-20 International Business Machines Corporation Anti-reflection structures for CMOS image sensors
US8003425B2 (en) * 2008-05-14 2011-08-23 International Business Machines Corporation Methods for forming anti-reflection structures for CMOS image sensors
FR3026561B1 (fr) 2014-09-25 2017-12-15 Commissariat Energie Atomique Procede de realisation d'une structure microelectronique multi-niveaux
FR3030878B1 (fr) 2014-12-17 2016-12-30 Commissariat Energie Atomique Procede de realisation d'un dispositif a effet de champ ameliore.
FR3035541B1 (fr) 2015-04-23 2018-03-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d’un dispositif a effet de champ ameliore.
FR3037716B1 (fr) 2015-06-18 2018-06-01 Commissariat A L'energie Atomique Et Aux Energies Alternatives Transistors superposes avec zone active du transistor superieur auto-alignee
US9786546B1 (en) * 2016-04-06 2017-10-10 International Business Machines Corporation Bulk to silicon on insulator device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670387A (en) * 1995-01-03 1997-09-23 Motorola, Inc. Process for forming semiconductor-on-insulator device
US5807783A (en) * 1996-10-07 1998-09-15 Harris Corporation Surface mount die by handle replacement
US20020045307A1 (en) * 1997-07-03 2002-04-18 Jorge Kittl Method of forming a silicide layer using metallic impurities and pre-amorphization
US6335214B1 (en) * 2000-09-20 2002-01-01 International Business Machines Corporation SOI circuit with dual-gate transistors
JP2003110108A (ja) * 2001-09-28 2003-04-11 Mitsubishi Electric Corp 半導体装置の製造方法及びその構造
US6838332B1 (en) 2003-08-15 2005-01-04 Freescale Semiconductor, Inc. Method for forming a semiconductor device having electrical contact from opposite sides
US6933577B2 (en) * 2003-10-24 2005-08-23 International Business Machines Corporation High performance FET with laterally thin extension
JP5095073B2 (ja) * 2004-04-28 2012-12-12 株式会社イー・エム・ディー 半導体物質の表面改質方法、半導体装置の製造方法
GB0411621D0 (en) * 2004-05-25 2004-06-30 Koninkl Philips Electronics Nv Dual gate semiconductor device
US7241700B1 (en) * 2004-10-20 2007-07-10 Advanced Micro Devices, Inc. Methods for post offset spacer clean for improved selective epitaxy silicon growth
US7465976B2 (en) * 2005-05-13 2008-12-16 Intel Corporation Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions
KR100654002B1 (ko) 2005-11-22 2006-12-06 주식회사 하이닉스반도체 텅스텐-폴리사이드 게이트 및 리세스채널을 갖는반도체소자의 제조방법

Also Published As

Publication number Publication date
US7915110B2 (en) 2011-03-29
FR2894069A1 (fr) 2007-06-01
US20090224295A1 (en) 2009-09-10
US20070122975A1 (en) 2007-05-31
US7556995B2 (en) 2009-07-07

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20130731