FR3037716B1 - Transistors superposes avec zone active du transistor superieur auto-alignee - Google Patents

Transistors superposes avec zone active du transistor superieur auto-alignee Download PDF

Info

Publication number
FR3037716B1
FR3037716B1 FR1555591A FR1555591A FR3037716B1 FR 3037716 B1 FR3037716 B1 FR 3037716B1 FR 1555591 A FR1555591 A FR 1555591A FR 1555591 A FR1555591 A FR 1555591A FR 3037716 B1 FR3037716 B1 FR 3037716B1
Authority
FR
France
Prior art keywords
superposed
transistors
self
active zone
upper transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1555591A
Other languages
English (en)
Other versions
FR3037716A1 (fr
Inventor
Claire Fenouillet-Beranger
Philippe Coronel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1555591A priority Critical patent/FR3037716B1/fr
Priority to US15/184,076 priority patent/US9852950B2/en
Publication of FR3037716A1 publication Critical patent/FR3037716A1/fr
Application granted granted Critical
Publication of FR3037716B1 publication Critical patent/FR3037716B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221Three dimensional integrated circuits stacked in different levels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5283Cross-sectional geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
FR1555591A 2015-06-18 2015-06-18 Transistors superposes avec zone active du transistor superieur auto-alignee Active FR3037716B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1555591A FR3037716B1 (fr) 2015-06-18 2015-06-18 Transistors superposes avec zone active du transistor superieur auto-alignee
US15/184,076 US9852950B2 (en) 2015-06-18 2016-06-16 Superimposed transistors with auto-aligned active zone of the upper transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1555591A FR3037716B1 (fr) 2015-06-18 2015-06-18 Transistors superposes avec zone active du transistor superieur auto-alignee
FR1555591 2015-06-18

Publications (2)

Publication Number Publication Date
FR3037716A1 FR3037716A1 (fr) 2016-12-23
FR3037716B1 true FR3037716B1 (fr) 2018-06-01

Family

ID=54356450

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1555591A Active FR3037716B1 (fr) 2015-06-18 2015-06-18 Transistors superposes avec zone active du transistor superieur auto-alignee

Country Status (2)

Country Link
US (1) US9852950B2 (fr)
FR (1) FR3037716B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11742346B2 (en) * 2018-06-29 2023-08-29 Intel Corporation Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002050767A (ja) * 2000-08-04 2002-02-15 Mitsubishi Electric Corp 半導体装置及びその製造方法
US7364832B2 (en) * 2003-06-11 2008-04-29 Brewer Science Inc. Wet developable hard mask in conjunction with thin photoresist for micro photolithography
KR100678462B1 (ko) * 2004-11-16 2007-02-02 삼성전자주식회사 단결정 박막 트랜지스터들을 갖는 반도체 집적회로 소자들및 그 제조방법들
FR2894069B1 (fr) 2005-11-28 2008-02-22 St Microelectronics Crolles 2 Fabrication de transistors mos
US7666787B2 (en) * 2006-02-21 2010-02-23 International Business Machines Corporation Grain growth promotion layer for semiconductor interconnect structures
US20070257322A1 (en) * 2006-05-08 2007-11-08 Freescale Semiconductor, Inc. Hybrid Transistor Structure and a Method for Making the Same
FR2911721B1 (fr) 2007-01-19 2009-05-01 St Microelectronics Crolles 2 Dispositif a mosfet sur soi
FR2937463B1 (fr) * 2008-10-17 2010-12-24 Commissariat Energie Atomique Procede de fabrication de composants empiles et auto-alignes sur un substrat
US7964916B2 (en) * 2009-04-14 2011-06-21 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8748871B2 (en) * 2011-01-19 2014-06-10 International Business Machines Corporation Graphene devices and semiconductor field effect transistors in 3D hybrid integrated circuits
KR102067122B1 (ko) * 2012-01-10 2020-01-17 삼성디스플레이 주식회사 박막 트랜지스터 및 이의 제조 방법

Also Published As

Publication number Publication date
FR3037716A1 (fr) 2016-12-23
US9852950B2 (en) 2017-12-26
US20160372375A1 (en) 2016-12-22

Similar Documents

Publication Publication Date Title
GB2571652B (en) Vertical transistors with merged active area regions
IL273299B1 (en) Electrode structure for a field effect transistor
HK1244748A1 (zh) 包含橫向/縱向晶體管結構的微流體裝置及其製造和使用方法
TWI560885B (en) Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs
GB201801219D0 (en) Vertical transistor fabrication and devices
GB201809710D0 (en) Variable gate lengths for vertical transistors
DK3149253T3 (da) Gulvafløb
GB2543420B (en) Sensors including complementary lateral bipolar junction transistors
EP3371831A4 (fr) Structure de transistor mos à grille divisée et à drain étendu latéral
FR3030114B1 (fr) Transistor hemt
FR3018952B1 (fr) Structure integree comportant des transistors mos voisins
PL3117465T3 (pl) Heterozłączowy tranzystor polowy
GB201603187D0 (en) Layered vertical field effect transistor and methods of fabrication
GB201913037D0 (en) Fabrication of vertical field effect transistor device with modified vertical fin geometry
GB201411621D0 (en) Organic transistor
EP3347915A4 (fr) Transistor à effet de champ vertical
EP3240042A4 (fr) Transistor bipolaire latéral à grille isolée et son procédé de fabrication
FR3026892B1 (fr) Transistor a effet de champ avec contact de drain mixte optimise et procede de fabrication
DE102015221521A8 (de) Tunneldiode und -transistor
GB201516246D0 (en) Tunnel field effect transistor
FR3037716B1 (fr) Transistors superposes avec zone active du transistor superieur auto-alignee
GB2526316B (en) Production of transistor arrays
GB201418752D0 (en) Lateral field effect transistor device
EP3240039A4 (fr) Transistor bipolaire à grille isolée latérale
DK3330445T3 (da) Gulvafløb

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20161223

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8

PLFP Fee payment

Year of fee payment: 9