TWI330396B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
TWI330396B
TWI330396B TW092136231A TW92136231A TWI330396B TW I330396 B TWI330396 B TW I330396B TW 092136231 A TW092136231 A TW 092136231A TW 92136231 A TW92136231 A TW 92136231A TW I330396 B TWI330396 B TW I330396B
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Taiwan
Prior art keywords
film
integrated circuit
substrate
semiconductor device
electrode
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TW092136231A
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English (en)
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TW200414401A (en
Inventor
Hideaki Kuwabara
Junya Maruyama
Yumiko Ohno
Toru Takayama
Yuugo Goto
Etsuko Arakawa
Shunpei Yamazaki
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Semiconductor Energy Lab
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Publication of TW200414401A publication Critical patent/TW200414401A/zh
Application granted granted Critical
Publication of TWI330396B publication Critical patent/TWI330396B/zh

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Description

1330396 (1) 玖、發明說明 【發明所屬之技術領域】 本發明相關於一種半導體安裝技術，確切地說，本發 明相關於安裝有利用轉移技術製造的積體電路膜的半導體 裝置以及該半導體裝置的製造方法。 【先前技術】 對借助於安裝半導體晶片而形成的半導體裝置來說， 要實現小體積化，薄型化，半導體晶片的薄型化技術是越 來越必要的技術。 一般來說，在半導體安裝技術領域中，對形成有半導 體元件的矽片（silicon wafer)的背面（也就是半導體層 中不作爲元件發生函數的那一部分）執行磨削（背面磨 削）’從而將其厚度加工成幾百μπι» 然而’由於形成在矽片上的絕緣膜和線路等的應力影 響’被加工得很薄的矽片有産生反屈的問題。而矽片的反 屈又會導致類似切割等製程難度變大的問題，這些問題妨 礙了半導體晶片的進一步被減薄。 針對於上述問題，已有人嘗試藉由改進在矽片的背面 磨削製程中粘貼護板（protecting sheet)的粘貼方法從而 抑制矽片的反屈等（比如，專利文件1 )問題的技術。 專利文件1 日本專利公開2000-61785 (第2-4頁，第1圖） 另外’其他的，在實施背面磨削時，在矽片背面形成 -5 - (2) 1330396 的傷痕等也會成爲妨礙半導體晶片的薄型化的問題。
Is上所述’爲了解決這些問題，開發薪新的不依靠石夕 片的背面加工就能夠實現薄型化的半導體安裝技術被迫切 期待。 【發明內容】 所以’針對於此，本發明的一個目的是提供安裝有利 用轉移技術而製成的積體電路膜的半導體裝置以及該半導 體裝置的製造方法。 本發明的半導體裝置的特徵之一是其安裝有利用轉移 技術而製成的積體電路膜。 在基底上形成半導體膜後，藉由將該半導體膜分離成 島的形狀來分離元件，從而形成積體電路，然後將該積體 電路從基底分離出來，這樣製成的膜狀的積體電路在本說 明書書中被稱爲"積體電路膜"。可以採用玻璃基底或石 英基底作爲上述基底。另外，轉移技術，以及只對上述基 底進行選擇蝕刻的技術可以用來作爲從基底將積體電路分 離出來的方法。 另外，安裝在本發明的半導體裝置的積體電路膜具有 分離成島狀的多個元件’構成各個元件的半導體層被分離 成島狀，該半導體層的厚度爲30-6〇nm。由多個元件構成 的積體電路具有邏輯電路’記億體等函數。 習知使用的半導體晶片的厚度取決於半導體層的厚 度。利用轉移技術而製成的積體電路膜是具有厚度爲30- -6 - 1330396 ⑶ 60ηπι的半導體層的膜，跟半導體晶片相比，其厚度是極 薄的》 另外，安裝在本發明的半導體裝置中的積體電路膜 中，構成各個元件的半導體層的膜面有多個平面方位 (plane direction ) 〇 另外，具有如上述的30-60 nm的半導體層的積髏電路 膜的厚度取決於線路以及層間絕緣膜的層疊數量。 另外’本發明的半導體裝置的特徵之一是具有和積體 電路膜連接的導熱率等於或大於l〇W/m.K的膜。 借助於提供如上述那樣的導熱性好的膜，使在積體電 路膜中産生的熱容易被釋放出。 本發明的半導體裝置的另一特徵是積體電路膜藉由突 起電極和線路基底電連接在一起。 另外’上述線路基底利用聚亞胺等絕緣體以及銅等 導電體而形成。該線路基底可以任意使用硬質或柔質的 板。絕緣體具體除了聚 亞胺，環氧玻璃等樹脂材料以 外，還可以使用鋁氧，氮化鋁等的陶瓷材料。另外，導電 體除了銅以外’還可以使用金等材料。突起電極是由厚 10-3Ομιη的焊錫或鍍金屬而形成。 另外’可以在上述基底上將多個積體電路膜多個地， 橫向排列地積載。另外，各個積體電路膜也可以被製成函 數不同的CPU或記憶體等。 此外’本發明的積體電路膜是多邊形。使多邊形成爲 可能的原因是本發明的積體電路膜沒有必要象矽片那樣依 (4) (4)1330396 靠劈開面（cleaved surface)來執行分割。 【實施方式】 以下就本發明的實施例模式進行詳細描述。 實施例模式 下面將用圖1 A -1 C描述本發明的實施例模式。本實 施例模式將對安裝了利用轉移技術製成的積體電路膜的半 導體裝置進行說明。 圖1A中，積體電路膜12和基底13藉由突起電極 (也稱凸塊’ bump) 15電連接在一起。積體電路膜12是 利用轉移技術剝離包括形成在玻璃基底上的TFT以及驅 動TFT的線路的層而形成，也就是說，這個實現了薄型 化的積體電路膜不用/象矽片那樣使用背面磨削製程就可以 j J' 形成。基底1 3是在亞胺膜上佈置了銅等的導電性材 料線路的多層線路基底。 在本實施例模式的半導體裝置中，積體電路膜12和 基底 13是倒裝結構（也就是面朝下的 face- down結 構），即形成在積體電路膜中的交錯式TFT 21的上側 (也就是以半導體層爲中心的閘電極側）和基底1 3被設 計成面對面的結構。 積體電路膜12中形成有多個由分離成島狀的多晶矽 膜的半導體層構成的TFT。
圖1B是表示部分積體電路膜12的橫截面圖。N通道 型TFT 21和P通道型TFT 22形成在絕緣膜23上。TFT (5) (5)1330396 21，22的半導體層厚30-60nm。在覆蓋TFT 21，22的絕 緣膜31上形成有傳遞電信號給TFT 21，22的線路35 » 另外，電極33形成在和線路35相同的層中。電極33在 保護TFT21，22以及線路35的保護膜34的開口部分暴 露出來。線路35由含有1 %的矽的鋁製成，層間絕緣膜 31由氧化矽等的有 25 0°C或更高的耐熱性膜製成。另 外，積體電路膜12是將形成在玻璃基底上的TFT層利用 轉移技術被剝離的厚1 -1 0 μιη的膜。另外，TFT層不但指 TFT，還包括線路，絕緣層的層。 積體電路膜12中，由導熱性好的材料製成的膜16形 成在和電極3 3相反的提供有絕緣膜2 3的那一側。借助於 提供膜16，可以釋放積體電路膜12中産生的熱。膜16 可以採用導熱率是 1〇λν/ιη·Κ或更多的金屬材料（比如鋁 等），或以碳或鋁爲主要成分的陶瓷材料（比如類金剛石 碳的DLC，鋁氧）。 圖1C是圖1Α中表示的積體電路膜12和基底13的 連接部分（用虛線11圍住的部分）的橫截面圖。其中， 導電膜42 ’ 43層疊形成在電極33之上。突起電極形成在 導電膜43之上。另外’積體電路膜12和基底13用粘合 劑粘接在一起。電極41和突起電極15藉由粘合劑中的金 屬顆粒電連接在一起。另外，除了粘合劑，也可以用導電 性膠（conductive paste)來電連接電極 41和突起電極 15 » 如上所述，藉由安裝由TFT形成的厚幾μιη的積體電 1330396 ⑹ 路膜，可以製造出其厚度被飛躍性地減薄的半導體裝置。 另外’本實施例模式雖使用形成有TFT的積體電路 膜，除此以外，也可以使用由形成在玻璃基底或石英基底 上的晶質半導體膜製成的記憶體等作爲積體電路膜來形成 半導體裝置。 下文中將詳細描述本發明的實施例。 實施例1 本實施例將用圖2A-5B描述安裝有利用轉移技術製 成的積體電路膜的半導體裝置的製造方法。 本實施例中製造的積體電路膜的厚度爲幾μιη，跟習 知的半導體晶片相比，其厚度被飛越性地減薄。所以，安 裝該積體電路膜的半導體裝置的體積也被飛越性地減小。 另外，該積體電路膜跟用矽片形成的積體電路膜不同的 是’沒有必要在執行分割時考慮劈開面，所以可以切割成 各種各樣的形狀。甚至可以用和基底一邊基本相同的尺寸 來切割。而且，該積體電路膜跟矽片不同，半導體層被分 離形成爲各自分開的島狀。所以，施加在TFT上的應力 被分散，其對彎曲等壓力的強度高於用矽片形成的積體電 路膜，並且，安裝時以及安裝後的半導體裝置對彎曲等外 來壓力耐壓性好。另外，在製造半導體裝置的過程中，沒 有必要實施背面磨削來實現薄型化，因此可以避免在磨削 製程中産生次品。另外，因爲不需要實施背面磨削，形成 TFT的製程和形成突起電極（凸塊）的製程可以連續地被 -10 - (7) (7)1330396 實施》 首先，在玻璃製成的第一基底700上形成TFT，形成 TFT的具體步驟如下。 在第一基底 700上形成絕緣膜701。本實施例用 PCVD法形成厚l〇〇nm的氧氮化矽膜（SiON)作爲絕緣膜 7 01 〇 然後在絕緣膜701上形成金屬膜702。本實施例用濺 射法形成厚50nm的鎢膜作爲金屬膜702。 接著，在金屬膜702上形成氧化膜703。本實施例用 濺射法形成厚200nm的氧化矽膜作爲氧化膜703。另外， 金屬膜702和氧化膜703的形成是在不暴露於大氣的情況 下連續形成的。另外，雖然氧化膜703的膜的厚度不限於 上述的値，但其厚度較佳是金屬膜702厚度的兩倍。 另外’藉由層疊形成金屬膜702和氧化膜703，在金 屬膜和氧化膜的介面（接觸面）形成了非晶質的氧化金屬 膜7〇4a。另外，由於在本實施例中使用鎢膜作爲金屬膜 7〇2，使用氧化矽膜作爲氧化膜703，所以形成了厚4nm 的氧化鎢（WOx)的氧化金屬膜7〇4a。另外，除了鎢 (W )以外’還可以使用鉬（M〇 )，鎢和鉬的合金 (WxMcm.x)等作爲金屬膜702。另外，也可以在氧化金 屬膜704 a中添加氧，從而促進後繼的剝離製程，或者添 加氮’從而抑制剝離。至於要不要添加上述成分，以及添 加量的多少，可以適當地根據需要進行調整。 接著’用氧灰化法（〇2 ashing)淸除形成在基底邊緣 -11 - (8) (8)1330396 的金屬膜702和氧化膜703 » 然後’在氧化膜703上形成底絕緣膜790。形成厚 lOOnm的氧氮化矽膜（SiON)作爲底絕緣膜790。形成該 底絕緣膜7 90是爲了防止雜質從玻璃基底等混入到後來形 成的半導體層中。 接著’形成晶質半導體膜705。晶質半導體膜705是 在形成厚54ηπι的非晶質矽膜後，將該非晶質矽膜晶化而 形成。另外，用PCVD法形成非晶質矽膜。還有，本實施 例的非晶質矽膜包含氫元素。 本實施例中，上述非晶質矽膜中含有2 1 · 5 % (成分 比）的氫元素。這個値是根據用紅外光譜學（FT-IR )的 定量分析得出的上述非晶質矽膜中的Si-H的密度爲 1.06 X 1022atoms/cm3，Si-H2 的密度爲 8.34 X l〇19atoms/ cm3的結果而算出來的。 隨後，在上述非晶質矽膜的表面添加催化劑的金屬元 素Ni後，進行50(TC，1小時的熱處理。接著，連續實施 55 0°C，4小時的使用爐子的熱處理從而形成第一多晶矽 膜。 另外，借助於實施410。C或更高溫度的熱處理來擴散 包含在非晶矽膜中的氫元素。另外，借助於實施400° C或 更高溫度的熱處理來晶化非晶質的氧化金屬膜704a，使 其成爲晶質氧化金屬膜704b »另外，經過晶化以後，氧 化金屬膜7〇4b的厚度是2nme換句話說’本實施例藉由 實施上述4l〇°C或更高溫度條件下的熱處理不但實現了氫 -12- 1330396 ⑼ 元素擴散，還實現了氧化金屬膜7 Ο 4 a的晶化。 晶質的氧化鎢變成了晶質的氧化鎢。另外’在如 的在形成第一多晶矽膜以外的製程中也可以實施 更高溫度的熱處理。 然後，輻照準分子雷射光束到第一多晶矽膜 晶性’從而形成第二多晶矽膜。 然後，用臭氧水在第二多晶矽膜上形成厚 氧化膜，並且用濺射法在其上形成厚iOOnm 膜。然後實施550°C，4小時的使用爐子的熱處 包含在晶質矽膜中的催化劑金屬元素遷移到非晶 氣處理）。除氣處理後，用TMAH溶液淸除掉 晶矽膜（除氣後，因催化劑金屬元素的效應有可 質矽膜），然後用氫氟酸淸除掉薄氧化膜，並形 導體膜705。 另外，上述晶質半導體膜705的膜的表面有 於<111>帶晶面（crystal zone plane)的結晶面。 另外，除了如本實施例那樣利用Ni作爲催 元素以外，還可以用衆所周知的晶化方法（固相 雷射器晶化法等）形成晶質半導體膜705。 當使用鐳射晶化法形成晶質半導體膜時，使 分子（XeCl)或YAG，YV04的脈衝振盪型或連 的鐳射作爲鐳射介質。當使用受激準分子鐳射時 盪頻率設置爲300Hz並且鐳射能量密度設置I 40OmJ/cm2。當使用Y A G鐳射時，使用它的二次 所以，非 本實施例 410oC 或 來提高結 lnm的薄 的非晶矽 理從而使 矽膜（除 不要的非 能變成晶 成晶質半 多個歸屬 化劑金屬 成長法， 用受激準 續振盪型 ，脈衝振 ! 100 到 諧波，脈 (10) (10)1330396 衝振盪頻率設置爲30到300Hz並且鐳射能量密度設置爲 300到600mJ/cm2。鐳射集中爲寬度1〇〇到ΙΟΟΟμπι的線 形鐳射，用該線形鐳射照射基底的整個表面，將鐳射的覆 蓋率設置爲50到90%。注意，即使在採用鐳射晶化法的 情形中，最好實施4l〇°C或更高溫度的熱處理從而擴散氫 元素以及執行氧化鎢的晶化。 然後，如上述那樣獲得晶質半導體膜7 0 5後，實施形 成圖案以及蝕.刻從而將其加工成所希望的形狀，這樣就形 成了分離成島狀的半導體層706a，70 6b。 另外，在形成半導體層7 06之前，或者形成之後，可 以添加雜質（通道雜質）以便控制TFT的門欄値。添加 的雜質可以是硼或磷。 接著，在半導體層7〇6a，706b上形成閘絕緣膜 707。隨後在閘絕緣膜7〇7上形成閘電極708。形成30 nm 厚的氧化矽膜作爲閘絕緣膜707。另外，在形成厚度分別 爲30nm，370nm的氮化鉅（TiN)膜和鎢膜後，執行圖案 形成以及蝕刻來形成閘電極。 然後，添加η型雜質的磷來形成n型的低濃度雜質區 70 9。並且，添加ρ型雜質的硼來形成ρ型的低濃度雜質 區 710。 接著，在閘電極708的側壁上形成邊牆（side wall ) 711 » 然後’添加η型雜質的磷來形成η型的源極區（或汲 極區）712。並且，添加ρ型雜質的硼來形成ρ型的源極 •14· (11) 1330396 區（或汲極區）7 1 3。 如上所述，用晶質半導體膜705分別形成η通道型 TFT 714，p 通道型 TFT 715。 隨後，形成覆蓋TFT 714’ 715的層間絕緣膜716。 形成氧化矽膜作爲層間絕緣膜7 1 6。並且’使層間絕緣膜 71 6的表面平坦化。在形成層間絕緣膜7 1 6後，實施使添 加了的雜質啓動的製程。
然後，形成貫穿層間絕緣膜716，到達源極區（或汲 極區）712，713的接觸孔。 然後，形成給TFT 714，715傳遞電信號的線路717 以及電極718。線路717以及電極718雙方都形成在和層 間絕緣膜7 1 6上面的層相同的層。另外，本實施例在形成 由鈦（Ti)，含有 1%的矽元素的鋁膜（Al-Si)，鈦 (Ti )組成的疊層後，執行圖案形成以及蝕刻來加工這個 疊層，這樣就形成了線路717和電極718。
然後，形成有開口部分的保護膜719。保護膜719是 在層間絕緣膜716的上方形成500nm厚的氧化矽膜，然 後實施圖案形成和蝕刻形成開口部分後而形成的。注意， 在保護膜719的開口部分，電極718是暴露出來的。 藉由以上步驟形成的從底絕緣膜705到保護膜719的 疊層就是TFT層720。 然後，在電極718上形成導電膜730和突起電極（凸 塊）731。導電膜730藉由層疊鉻（Cr)和銅（Cu)而形 成。另外，突起電極731用PbSn或金（Au)作爲材料藉 -15- (12) (12)1330396 ^接方式而形成。注意’突起電極731的厚度爲 2〇 μΠ1。另外，其他的材料，如果是和突起電極7 3 1的緊貼 性好的材料’也可以被用於導電膜730。 另外’層間絕緣膜7 1 6和保護膜7 1 9最好採用能夠耐 焊接溫度的25 0。C或更高溫度的耐熱性材料。另外，層間 絕邊膜716和保護膜719可以採用有機材料，也可以採用 無機材料。 接下來’將對剝離形成有突起電極73 1的TFT層720 的製程進行說明。 首先’在保護膜719的上方塗敷粘合劑740。注意， 塗敷粘合劑的厚度大約爲60μπι，這樣以便覆蓋突起電極 73 1。塗敷粘合劑74〇後，執行烘烤’然後照射紫外線來 實現硬化。本實施例採用本身有平坦性的水溶性樹脂作爲 粘合劑74〇。另外’粘合劑74〇由環氧基，丙烯酸酯基， 矽基等製成。 然後’在要剝離區域的邊緣的一部分用金剛石筆切入 切口’對該部分進行有意性地損傷。從外部施加局部壓力 來降低金屬膜7〇2，氧化金屬膜7〇4b，氧化膜703之間的 介面（接觸面）的粘接力，這樣就容易從切入的切口部分 實施剝離製程。另外，除了用金剛石筆切入切口的方法以 外，可以使用劃線器具並且將下壓量設在1mm，來切入 切口。或者，用鐳射沿著要剝離區域的周邊部分實施部分 照射，對該部分進行有意損傷，這樣來達到降低金屬膜 702，氧化金屬膜7〇4b，氧化膜703之間的接觸面的粘接 -16 - (13) (13)1330396 力的目的。 然後，用雙面膠帶741在粘合劑740之上粘貼第二基 底7 4 2。在此，因粘合劑74 〇本身具有平坦性，所以粘合 劑7 40的表面和第二基底742的表面可以基本平行地粘接 在一起。並且，用雙面膠帶741也在第一基底700上粘接 第三基底743。第三基底743是爲了防止第一基底700不 受破損而粘接的。 然後，從上述被有意損傷了的金屬膜702，氧化金屬 膜704b，氧化膜703之間的接觸面，用物理方法（如用人 的手、藉由噴嘴噴射的氣壓、超聲波等）剝離第一基底 700 ° 藉由上述步驟，將在第一基底7〇〇上形成的TFT層 7 20轉移到第二基底742。 注意，TFT層720被轉移後，TFT層720下面的氧 化金屬膜704b以及氧化膜703被殘留下來。本實施例只 淸除氧化金屬膜7〇4b。 然後，在氧化膜703上形成導熱性好的膜744。本實 施例用類金剛石碳的DLC形成厚10 μιη的膜744。另外， 除了 DLC以外，也可以使用Α12〇3。 然後，在膜744上粘貼保護片745，使用有粘接層的 保護片745。 隨後，從雙面膠帶741撕剝第二基底742。然後撕剝 該雙面膠帶741，接著浸在純水中以便淸除粘合劑74〇。 藉由這些步驟，TFT層720處於貼附在保護片745的狀 (14) (14)1330396 能〇 接下來，將貼附在保護片745的TFT層720連同保 護片74 5 —起切開，並形成所希望的圖案，最後製成多個 積體電路膜750。 另外，第二基底742也可以在切斷TFT層後再被剝 下。還有，必須考慮在剝離第二基底742時，不使保護片 被同時剝離的粘接性。 另外，本實施例中雖說明瞭利用金屬膜的剝離方法， 但剝離方法並不局限於此，使用其他方法，比如利用溶解 第一基底的方法，以及利用對第一基底的背面照射鐳射的 方法等也無妨。 下面將說明安裝利用轉移技術製成的積體電路膜750 的方法。 在第四基底751上塗敷粘合劑752，其中第四基底中 的聚 亞胺膜上佈置有多層的用銅等導電材料製成的線 路。另外，第四基底751上形成有電極75 3。另外，粘合 劑752中分散有被絕緣膜覆蓋著的金屬顆粒。 然後，安排第四基底75 1的電極75 3上重疊於積體電 路膜750的電極718，在這種狀態下粘合第四基底751和 積體電路膜75 0。粘合時，電極718上形成的突起電極 731藉由粘合劑752中的金屬顆粒和電極753電連接在一 起。另外，覆蓋金屬顆粒的絕緣膜在結合時，因來自突起 電極731和電極7 5 3的壓力被破壞，所以可以是連通的。 另外’沒有形成突起電極731的部分由於絕緣膜沒有被破 -18 - (15) (15)1330396 壞，因此其絕緣性被得以維持。 其次’對積體電路膜75 0照射紫外線，剝離保護片 745。另外，也可以在粘合積體電路膜75〇和第四基底 75 1前剝離保護片745。 藉由以上步驟’完成了半導體裝置的製造。 實施例2 本實施例將用圖6A-6B說明利用不同於實施例1的 方法’藉由粘合積體電路膜750和第四基底751製造半導 體裝置的情況。 塗敷樹脂771到第四基底751上，該基底上的聚亞 胺膜上佈置有多層用銅等導電材料製成的線路。另外，第 四基底751上形成有電極753。 接著’在突起電極731上附著導電性膠772。 然後，安排第四基底751的電極753上重疊於積體電 路膜750的電極718’在這種狀態下貼合電極753和突起 電極7 3 1。 對積體電路膜750施加超聲波振盪，使樹脂771擴散 到積體電路膜7 5 0和第四基底7 5 1之間的空隙整體。然 後，進一步實施加熱處理’使樹脂771硬化。 然後，對積體電路膜750照射紫外線，並剝離保護片 745。另外，也可以在粘合積體電路膜 750和第四基底 751前剝離保護片745。 藉由以上步驟，完成了本發明的半導體裝置的製造。 -19- (16) (16)1330396 根據本實施例製造的半導體裝置和根據實施例1製造的半 導體裝置一樣，積體電路膜的厚度僅有幾μιη，跟習知的 半導體晶片相比，其厚度被飛躍性地減薄了。 實施例3 本實施例將用圖7Α和7Β說明使用利用轉移技術製 成的積體電路膜而製成的多膜模組（multifilm module ) 。 根據實施例1描述的直到形成晶質半導體膜705的方 法，形成晶質半導體膜後，在不同的基底上用該晶質半導 體膜形成 CPU ( Central Processing Unit,中央處理構 件），快閃記憶體（flash memory ) ，SRAM (Satie DRAM,靜態隨機記億體），DRAM (Dynamic Random Access Memory，動態隨機記憶體），邏輯電路（Logic circuit ) 〇 其次，根據和實施例1描述的形成TFT 714，715後 相同的方法，形成分別搭載CPU，快閃記憶體，SRAM， DRAM，Logic 的積體電路膜 7001，7002，7003，7004， 7005 »另外，本實施例中積體電路膜7001-7005中形成有 用導熱性好的材料製成的膜。 然後，利用根據相同於實施例1描述的安裝方法，或 根據相同於實施例2描述的安裝方法，在印刷基底的雙面 形成有多層線路層的第五基底7010上粘貼各個積體電路 膜 700卜70〇5。 -20- (17) (17)!33〇396 圖7B是按圖7A中A-A’線切割的橫截面圖，圖7B 中，在第五基底7010上安裝有積體電路膜7001-7005。 如實施例1中所描述，本發明中的積體電路膜由於不 象矽片那樣受劈開面的限制，所以可以被切割成各種各樣 的形狀。這樣就提高了第五基底上的積體電路膜 7001-7005的佈置以及第五基底 7010上的線路分佈的自由程 度。 根據以上步驟可以製造倒裝晶片（Flip chip)型多膜 模組。另外，本發明的多膜模組由於是使用利用轉移技術 製成的積體電路膜而形成，其厚度被飛躍性地減薄。 實施例4 本實施例將用圖10A-10E說明搭載了本發明的半導體 裝置的電子器具的實例。藉由搭載本發明的半導體裝置可 以製造極薄的電子器具。另外，本發明的半導體裝置如圖 8-9B那樣被安裝，並被搭載到各個電子器具的主體內 部。 圖8中，主印刷電路基底800上安裝有應用本發明而 製成的多膜模組820。多膜模組820上安裝有多個積體電 路膜821 -8 24。各個積體電路膜中安裝有邏輯電路821， 快閃記億體822，SRAM 823，DRAM 824。該各個積體電 路膜是各自在不同的基底上形成後利用轉移技術而製成 的。另外，CPU 810，邏輯電路811也是應用本發明被極 薄地製成的。本發明的半導體裝置可以被安排成如邏輯電 -21 - (18) 1330396 路8 11那樣的L字形等各種各樣形狀。另外，實施例1 -3 中雖然舉出了倒裝（Face-down )型半導體裝置的例子’ 但用線路接合法（Wire_bonding)來安裝也無妨。這種情 形中，同樣可以安裝各種各樣形狀的積體電路膜。
另外，圖9A中，基底903上安裝有驅動器901和控 制器902 »另外，圖9B是按圖9A中B-B’線切割的橫截 '面圖。基底903上安裝有FPC 904，藉由FPC 904，連接 比如顯示裝置等。驅動器901和控制器902是本發明的半 導體裝置。另外，本實施例中的基底903是撓性基底。 圖10A表示應用本發明而製成的筆記本式個人電 腦，由主體3001，框架3002，顯示構件3003，鍵盤3004 等構成。
圖10B表示應用本發明而製成的可攜式資訊端點 (PDA) ’在主體3021上提供有顯示構件3〇23，外部介 面3 025 ’操作按鈕3024等構成。另外，還提供有作爲操 作用的附屬品的觸筆（Stylus) 3022。 圖10 C表示視頻照相機，由主體3 0 3 1，顯示構件 3032，音頻輸入構件3033，操作開關3034，電池3035， 影像接收部分3036等構成。 圖10D表示應用本發明而製成的行動電話，在主餿 3〇41上提供有顯示構件3〇44，音頻輸出構件3〇42，音頰 輸入構件3043，操作按鈕3045，天線3046等。 圖10E表示數位相機，由主體305 1，顯示構件a 305 7 ’目鏡305 3，操作開關3054，顯示構件B 3055，電 -22- (19) (19)1330396 池3 05 6等構成。 安裝在本發明的半導體裝置中的積體電路膜的厚度爲 幾μπι，與習知的積體電路膜相比，其厚度被飛躍性地減 薄。所以，安裝有該積體電路膜的本發明的半導體裝置的 厚度也被飛躍性地減薄。另外，由於可以將積體電路膜切 割成各種各樣的形狀，所以比如在一個多層線路基底上安 裝多個積體電路膜時，可以提高佈局的多樣化和安裝密 度。安裝在本發明的半導體裝置中的積體電路膜，其半導 體層是分離成獨立的島形狀。因此，施加在TFT上的應 力被分散，對彎曲等壓力的強度比用矽片製成的積體電路 膜還要大。另外，在製造半導體裝置的過程中，沒有必要 實施背面磨削來實現半導體裝置的薄型化，因此可以避免 在磨削製程中產生次品，並可以提高成品率。另外，因爲 不需要實施背面磨削，形成TFT的製程和形成突起電極 (凸塊）的製程可以連續地被實施。 【圖式簡單說明】 在圖式中： 圖1A-1C是表示本發明的半導體裝置的視圖； 圖2A-2E是說明製造本發明的半導體裝置的視圖； 圖3 A-3D是說明製造本發明的半導體裝置的視圖 圖4 A-4D是說明製造本發明的半導體裝置的視圖 圖5 A-5B是說明製造本發明的半導體裝置的視圖 圖6 A-6B是說明製造本發明的半導體裝置的視圖 -23 - (20) 1330396 圖7A-7B是說明製造本發明的半導體裝置的視圖； 圖8是表不應用本發明的半導體裝置的模組的視圖； 圖9A-9B是表示應用本發明的半導體裝置的模組的 視圖： 圖10A-10E是應用本發明的半導體裝置的電子器具的 視圖。 本發明的選擇圖爲圖1 主要元件對照表 12 積體電路膜 13 基底 15 突起電極 16 膜 21 交錯式TFT 22 P通道型TFT 23 絕緣膜 3〇0 1 主體 3〇〇2 框架 3003 顯示構件 3〇〇4 鍵盤 3021 主體 3022 觸筆 3023 顯示構件 3 024 操作按鈕 3025 外部介面
-24- (21) 主體 顯示構件 音頻輸入構件 操作開關 電池 影像接收部分 主體 音頻輸出構件 · 音頻輸入構件 顯示構件 操作扭鈕 主體 目鏡
操作開關 顯示構件B 電池 #
顯示構件A 絕緣膜 電極 保護膜 線路 電極 導電膜 導電膜 -25 - (22)1330396 700 第一基底 700 1 積體電路膜 701 絕緣膜 7010 第五基底 702 金屬膜 703 氧化膜 704a 氧化金屬膜 704b 氧化金屬膜 705 晶質半導體膜 706 半導體層 706a 半導體層 707 閘絕緣膜 708 閘電極 709 η型的低濃度雜質區 710 Ρ型的低濃度雜質區 711 邊牆 712 源極區 713 源極區 714 TFT 715 P通道型TFT 716 層間絕緣膜 717 線路 718 電極 719 保護膜
-26 - (23) TFT層 導電膜 突起電極 粘合劑 第二基底 第三基底 膜 保護片 積體電路膜 第四基底 粘合劑 電極 樹脂
導電性膠 基底絕緣膜 印刷電路 CPU 邏輯電路 多膜模組 邏輯電路 快閃記憶體 SRAM DRAM 驅動器 -27 - 1330396 (24) 902 903 904 控制器 基底
FPC

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1330396 於丨/月彳日修正本 - ---| _ 拾、申請專利範圍 第092 1 3 623 1號專利申請案 中文申請專利範圍修正本 民國98年11月 19日修正 1. 一種半導體裝置，包含： 多數的積體電路膜； 包括第一電極的基底，該基底結合至該多數積體電路 膜；以及 突起電極， 其中各個該多數積體電路膜經由該突起電極電連接至 該第一電極。 2. 根據申請專利範圍第1項的半導體裝置，其中構 成所述積體電路的半導體層的厚度在3 0-60nm的範圍內。 3. 根據申請專利範圍第1項的半導體裝置，其中提 供導熱率等於或大於10\ν/ιη·Κ的膜，且使該膜和所述積 體電路膜連接。 4. 一種半導體裝置，包含： 多數的積體電路膜； 包括第一電極的基底，該基底結合至該多數積體電路 膜；以及 突起電極， 其中各個該多數積體電路膜經由該突起電極電連接至 該第一電極，以及 其中各個該積體電路膜包含半導體膜且該半導體膜之 1330396 厚度從30nm至60nm。 5. 根據申請專利範圍第4項的半導體裝置，其中提 供導熱率等於或大於10 W/m.K的膜’且使該膜和所述積 體電路膜連接。 6. 根據申請專利範圍第4項的半導體裝置’其中所 述積體電路膜是多邊形。 7. —種半導體裝置的製造方法，包含以下步驟： 在第一基底上形成晶質半導體膜； 形成包含使用該晶質半導體膜的元件的元件層，傳遞 電信號到該元件的線，路，以及絕緣層； 將該元件層從該第一基底轉移至第二基底； 從該元件層移除該第一基底； 將該元件層轉移至薄板（sheet)上： 從該元件層移除該第二基底；以及 在將該元件層轉移至該薄板後，分割該元件層成爲至 少一個積體電路膜。 8. 根據申請專利範圍第7項的半導體裝置的製造方 法’其中，形成所述元件層，而後’該元件層被轉移到第 二基底前，形成對所述線路傳遞電信號的突起電極。 9. 根據申請專利範圍第7項的半導體裝置的製造方 法，其中在所述元件層被轉移到所述第二基底後，在所述 元件層上形成導熱率等於或大於lOW/m.K的膜。
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