TWI324818B - A microelectronic assembly having thermoelectric elements to cool a die and a method of making the same - Google Patents

A microelectronic assembly having thermoelectric elements to cool a die and a method of making the same Download PDF

Info

Publication number
TWI324818B
TWI324818B TW94102919A TW94102919A TWI324818B TW I324818 B TWI324818 B TW I324818B TW 94102919 A TW94102919 A TW 94102919A TW 94102919 A TW94102919 A TW 94102919A TW I324818 B TWI324818 B TW I324818B
Authority
TW
Taiwan
Prior art keywords
conductive members
support substrate
thermoelectric
microelectronic
electrically conductive
Prior art date
Application number
TW94102919A
Other languages
English (en)
Other versions
TW200529398A (en
Inventor
Shriram Ramanathan
Gregory Chrysler
Steven Towle
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200529398A publication Critical patent/TW200529398A/zh
Application granted granted Critical
Publication of TWI324818B publication Critical patent/TWI324818B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38—Cooling arrangements using the Peltier effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

1324818 * - (1) 九、發明說明 【發明所屬之技術領域】 ' 本發明大體上係有關於一種微電子組件其具有一微電 ' 子晶粒，及更特定地係有關於被用來冷卻此一組件之一微 電子晶粒的系統。 【先前技術】 • 因爲半導體元件，像是處理器及處理元件，以愈來愈 快的資料率及頻率來運作，它們通常會消耗掉更大的電流 及產生更多的熱。爲了可靠度的原因將這些元件的運作保 持在特定的溫度範圍內是所需要的。傳統的熱傳遞機制將 這些元件的運作限制在低功率等級，低資料率，及/或低 運作頻率。傳統的熱傳遞機制由於尺寸及位置的限制以及 熱極限的關係而對熱傳遞容量多所侷限。 1J 式 方 施 實 及 容 內 明 發 一種微電子組件被提供，其具有形成在一晶粒上的熱 電元件’用來在電流流經熱電元件時將熱從該晶粒上帶走 。在一實施例中，該等熱電元件被集成在該晶粒的一主動 側上的互連線線元件之間。在另一實施例中，該等熱電元 件是位在晶粒的背側上且電氣地連接至位在該晶粒的前側 的一載具基材上。在另一實施例中，該等熱電元件是被形 成在一輔助基材上且被轉移到該晶粒上。 第1圖顯不晶圓10中經過部分處理用以依據本發明 -5- (5) 1324818 別的封裝接腳62接觸。 包括晶粒10A及封裝基板60在內之整個微電子組件 • 70然後被插入到一爐子內用以將該導電的互連線元件54 ' 再流焊（reflow)。該等導電的互連線元件54被軟化及被熔 化，接著被冷卻及再次固化。每一導電的互連線元件54 然後被裝附到一各別的封裝接腳62上，藉以將該晶粒 10A固定到該封裝基板60上且電氣地將該晶粒10A及該 φ 封裝基板60互連在一起。 在使用時，電力經由該封裝基板60，經由一封裝接腳 62 A而被提供到該熱電元件3 0。電流流向該晶粒，經過該 η型摻雜的半導體物質44。將被熱電領域的人瞭解的是， 流經該η型摻雜的半導體物質44的電流會造成熱被朝一 方向被抽離，該方向與電流的流動方向相反。因此，熱在 —從該電熱元件30朝向該封裝基板60的方向上被抽離的 。流經電熱元件30的電流被分叉。該電流的一部分提供 φ 電力到某些積體電路元件1 8，而某些電流則流經該電力接 點墊24Ρ，然後經過熱電元件40到達封裝機腳62Β。流經 該Ρ型摻雜的半導體物質34的電流會造成熱從一電流流 動方向上被抽離。流經該Ρ型摻雜的半導體物質34的電 流從積體電路14流離開，因此將熱熱帶離積體電路〗4。 在另一實施例中，提供電力到熱電元件的電力接點墊 可與提供電力至電路之電力接點墊分開來。這可對於熱電 單元有分開來的控制。此一架構在必需保持電壓被提供到 電路上，但不讓該電壓被提供至該熱電模組之電力的影響 -9- (7) 1324818 ，散熱器80包括一底座及複數片從該底步伸出的散熱鰭 片’熱可從該等鰭片被對流至周圍環境中。 ' 打線結合的電線84被提供，電流經過該電線84可被 提供至熱電元件76或從熱電元件76離開。每—條打線結 合的電線84都具有一連接至位在該晶粒74的上表面上的 一個墊’該墊被連接至該等熱電元件76中的第一個該熱 電元件76。該打線結合的電線84的另一相對端則被結合 φ 到該封裝基板72的一封裝接腳上。該電流從該封裝接腳 流經該打線結合的電線84及接點，經過該第一熱電元件 7 6。該電流然後可流經偶數的熱電元件7 6，然後回轉流經 另一打線結合的電線84到達封裝基板72。 第6圖顯示依據本發明的另一實施例之微電子組件86 。該微電子組件8 6與第5圖的微電子組件7 0相同且相同 的標號代表相同的構件。主要的不同處在於，微電子組件 86包括一晶粒88其比第5圖的晶粒薄許多。短的插塞90 φ 被形成穿過該晶粒88。一些熱電元件76與各自的插塞90 及各自之導電的互連線元件82對齊。電流可透過各自之 導電的互連線元件82及各自的插塞90而被提供各自的熱 電元件76。電流然後可流經偶數的熱電元件76並經由另 ' 一插塞90及與其彼此對齊之另一導電的互連線元件82回 轉。 第7至8圖顯示微電子組件的製造，其中熱電元件是 被製造在一分離的基材上，然後被移轉到在晶圓等級的積 體電路上。該結合的晶圓然後被分切成單獨的一片一片° -11 - (8) 1324818 特別参照第7圖，一晶圓94.被提供，其具有一晶圓 基材96，被形成在該晶圓基材96上的積體電路98，及形 • 成在該積體電路98上的墊子1〇〇。第7圖亦顯示出一移轉 • 基材1〇2其具有熱電元件104形成於其上，其形成方式與 第3圖的熱電元件3 0類似。第7圖亦顯示間隔物1 〇6形 式的互連線結構。該等熱電元件104及間隔物106具有導 電的互連線元件108形成於其上。 φ 如第7圖所示’每一導電的互連線元件1〇8都與各自 的接點墊1〇〇相接觸。該等導電的互連線元件108然後藉 由一熱再回焊處理而被裝附到接點墊100上。一組合的晶 圓1 10被提供，其包括該晶圓基材96及102。 現參照第9圖。第8圖的組合晶圓11〇被分切成分離 的—片一片的晶圓片112。晶圓96然後被分離成一片一片 的晶圓片96A及96B’及晶圓1〇2然後被分離成一片一片 的晶圓片102A及102B。晶圓片112都相同且每一片都包 φ 括一各自的積體電路98。金屬被提供在晶圓片102A及 102B的上層。該等晶圓片被安放到支撐基材上且被打線 結合到支撐基材上。或者，晶圓片102A及102B可被變薄 且在晶圓片102A及102B上的介層孔可將該金屬電氣地連 接至該支撐基材。 —整合的熱散布器114然後可被安裝到一晶圓片96A 的晶圓基材部分的背側上，即，與積體電路9 8相反的一 側上’且一散熱器116可緊靠著該熱散布器114被安裝。 第10圖顯示一微電子組件120的構件，該微電子組 -12 - (10) 1324818 且是在會造成對於晶粒122的微電子電路危害之處理條件 下被製造的。然而，藉由首先將熱電元件1 製造在分離 • 的熱散布器124上，然後將熱電元件130放在晶粒122上 - ，如此即可避免掉對晶粒1 22的危害。 第11圖顯示一依據本發明的另一實施例的微電子組 件140，其包括一封裝基板142，一晶粒144，一導熱的金 屬熱散布器145，一銅金屬層146’ 一熱電模組M8，及一 φ 熱介面物質150。 晶粒144具有一形成在一支撐基材的前側上的微電子 電路。晶粒144典型地被變薄至一小於100微米的厚度。 互連線元件1 5 1被形成在晶粒1 44的前側上，且被用來將 晶粒144電氣地及結構地連接至封裝基板142。因此，晶 粒144與封裝基板142與參照第5圖說明之晶粒74及封 裝基板72類似。 金屬層146被電鍍到晶粒144的支撐基材的背側上。 φ 該金屬層146上被形成一開口，且熱電模組148被製造在 該開口內。 在使用時，介於熱電模組1 48與晶粒1 44之間的金屬 層146作用是將來自晶粒144之微電子電路所產生的熱點 的熱散佈開來。第12圖顯示多於一個的熱點152A及 152B會被形成在晶粒144的一區域上。一各自的熱電模 組148A及148B被製造在各自的熱點152A及152B上。 熱電模組148A及148B與熱點152A及152B比較起來是 相對較大’使得它們可移走相對大的熱量。儘管熱電模組 -14- _ (11) Ϊ324818 148A及148B與熱點152A及152B比較起來的尺寸是如此 ，但熱電模組148A及148B的外區域仍能將熱從熱電 * 152A及152B處移走，因爲來自熱電的熱當其流過介於各 • 自的熱電模組148A或148B與各自的熱點152之間的矽及 該部分的金屬層（第11圖中的146)時會橫向地散佈。 一電源線154被連接至該熱電模組148用以提供電力 至該電熱模組。在此實施例中，一開口 156被形成穿過該 φ 熱散布器145，且該電源線154延伸穿過該開口 156。 雖然某些舉例性的實施例已被描述且被示於附圖中， 但應被瞭解的是，這些實施例只是示範性的且不是本發明 的限制，本發明並不侷限於所示所描述的特定結構及安排 ，因爲熟習此技藝者可做出不同的修改。 【圖式簡單說明】 本發明以參照附圖中所示之例子方式來加以說明，其 φ 中： 第1圖爲一晶圓基材的一部分的剖面圖，該晶圓基材 依據本發明的一實施例被部分地處理用以製造一微電子組 件； 第2圖爲一與第1圖類似的圖式，其顯示一開口被蝕 ' 刻在該經過部分處理之晶圓基材的一介電層上及一熱電元 件被形成在該開口內之後的情形； 第3圖爲一與第1圖類似的圖式，其顯示在另一熱電 元件之後，有一相反的摻雜導電性種類及在第2圖中形成 -15- (12) 1324818 的該熱電元件被形成，以及該經過部分處理之晶圓的其它 在一積體電路上的構件的情形； - 第4圖爲一與第3圖類似的圖式，其顯示在該晶圓被 - 終處理之後，該晶圓被分割成一個一個的晶粒，且一個晶 粒被覆蓋在一載體基材上且被固定到該載體基材上用以依 據本發明的一實施例來進行一微電子組件的最後製造； ' 第5圖爲一側視圖，其代表依據本發明的另一實施例 φ 之微電子組件，其具有熱電元件位在與一獨立的晶粒的主 動側相反的一側上，且被打線結合（wirebonded)至一在該 晶粒的主動側上的封裝基板上； 第6圖爲一側視圖，其代表依據本發明的另—實施例 之微電子組件’其不同於第5圖的實施例之處在於短插塞 電氣地連接至在該晶粒的一側上之熱電元件，其中導電性 的互連線元件被形成在該晶粒的一相反的，主動側上； 第7圖爲兩片晶圓基材的側視圖，其中一片晶圓基材 φ 載負主動的積體電路，及另一片晶圓基材載負熱電元件， 其被使用來製造依據本發明的另一實施例的微電子組件； 第8圖爲一與第7圖類似的圖式，其顯示在熱電元件 被放置成緊貼並裝附在該積體電路上的接點墊上之後的情 形； 第9圖爲一與第8圖類似的圖式，其顯示在第8圖的 組件被分割成獨立的_片—片，且—積體電路及一散熱器 被安裝到一片上的情形； 第10圖爲一頂視圖，其顯示一依據本發明的另一實 -16- (13) 1324818 施例的電子組件的構件’其中一熱電模組的某些部分被形 成在一晶粒上及一熱散佈器上’且該熱電模組在該熱散佈 • 器被放在該晶粒上之後即完成； • 第11圖爲一剖面圖，其顯示一依據本發明的另一實 施例的電子組件的構件，其具有一被電鍍在一晶粒的背側 上之金屬層用來將熱從一熱電散佈到—熱電模組上；及 第12圖爲一頂視圖’其顯示熱點及用來冷卻熱點之 Φ 熱電模組的相對尺寸。 【主要元件符號說明】 1 0 :晶圓 1 2 :晶圓基材 14 :積體電路 1 6 :介電物質 1 8 :積體電路元件 φ 20 :電力平面 2 2 :地極平面 24 :接點墊 24P :電力接點 2 4 G :地極接點 _ 241 :訊號接點 26 :電連接 26P1 :電力電連接 26P2:電力電連接 -17- (14) (14)1324818 26G1 :地極電連接 26G2:地極電連接 261 :訊號電連接 3 0 :熱電元件 28 :開口 3 2 :擴散阻障層 34: p型摻雜的熱電元件 3 6 :擴散阻障層 4 0 :熱電元件 42 :擴散阻障層 44 : η型摻雜的熱電元件 4 6 :擴散阻障層 4 8 :導電的間隔構件 5 〇 :導電的間隔構件 5 4 :導電的互連線元件 5 6 :上表面 1 0 A :晶粒 60 :封裝接腳 62 :封裝接腳 70 :微電子組件 62A :封裝接腳 62B :封裝接腳 72 :封裝基板 7 4 :晶粒 -18 (15)1324818 76 :熱電元件 78:整合的熱散佈器 80 :散熱器 82:導電的互連線元件 8 4 :打線結合電線 8 6 :微電子組件
8 8 :晶粒 90 :插塞 94 :晶圓 96 :晶圓基材 98 :積體電路 1 〇 0 :接點墊 1 0 2 :轉印基材 1 〇 4 :熱電元件 1 0 6 :間隔物
108:導電的互連線元件 1 1 0 :晶圓 1 1 2 :分離的晶圓片 1 0 2 A :晶圓片 1 0 2 B :晶圓片 114 :熱散佈器 9 6 A :晶圓片 1 16 :散熱器 120 :微電子組件 -19 (16) (16)1324818 122 :晶粒 124 :熱散佈器 126:第一複數個構件 1 2 8 :第二複數個構件 1 3 0 :熱電元件 130A : P型摻雜的熱電元件 130B : η型摻雜的熱電元件 140 :微電子組件 142 :封裝基板 1 4 4 :晶粒 145 :熱散佈器 146 :銅金屬層 1 4 8 :熱電模組 1 5 0 :熱界面物質 152Α :熱 152Β ：熱電 148Α :熱電模組 148Β :熱電模組 1 5 4 :電源線 1 5 6 :開口 -20

Claims (1)

1324818 十、申請專利範圍 附件3A :第94 1 0 29 1 9號專利申請案 中文申請專利範圍替換本 民國98年8月6日修正 1. 一種製造微電子組件的方法，其包含： 形成一微電子電路於一半導材質的支撐基材上；
直接在該半導體材質之與該微電子電路相反的一側上 的半導體材質上形成複數個接點墊； 形成複數個導電構件於一導熱構件上； 形成複數個熱電元件於該導熱構件的導電構件上；及 將熱電元件設置在該支撐基材之與該微電子電路相對 的一側上且是位在熱電元件會被熱耦合至該支撐基材上的 位置處。 2. 如申請專利範圍第1項之方法，其中該微電子電 %路是在熱電元件被熱耦合至該支撐基材上的接點墊之前被 形成在該支撐基材上。 3. 如申請專利範圍第1項之方法，其更包含形成第 一複數個導電的構件於該支撐基材上，成對的導熱構件藉 •由該等第一複數個導電構件而電氣地彼此連接。 4. 如申請專利範圍第3項之方法，其更包含形成第 二複數個導電的構件於該支撐基材上，成對的導熱構件藉 由該等第二複數個導電構件而電氣地彼此連接，該等導熱 構件與該支撐基材朝向彼此之相對運動可將該等導熱構件 1324818 朝向該等第二複數個導電構件移動。 5. 如申請專利範圍第4項之方法，其中該等第一及 第二複數個導電構件共同地將熱電元件串聯地連接起來。 6. —種製造微電子組件的方法，其包含： 形成一微電子電路於一支撐基材上； 形成第一複數個導電構件於一導熱構件上； 形成第二複數個導電構件於該支撐基材之與該微電子 電路相反的一側上； 形成複數個熱電元件於該導熱構件上的至少一些導電 構件上；及 將其上帶有該等電熱元件的該等導熱構件與該支撐基 材一起轉移（moving)，使得該等第一及第二複數個導電 構件共同地將熱電元件串聯地連接起來。 7. 如申請專利範圍第6項之方法，其中該等熱電元 件被形成在該等第一複數個導電構件上。 8. 如申請專利範圍第6項之方法，其更包含形成複 φ 數個接點墊於該微電子電路之與支撐基材相反的一側上。 9. 一種微電子組件，其包含： 一晶粒，其包括一半導體材質的支撐基材及一形成在 該半導體材質支撐基材上的微電子電路； —導熱構件；及 一熱電電路，其包括在該導熱構件上之第一複數個導 電構件，直接在該支撐基材之與該微電子電路相反的一側 上的半導體材質上的第二複數個導電構件，及複數個熱電 -2- 1324818 元件其串聯地連接在各對導電構件之間。 10. 如申請專利範圍第9項所述之微電子組件，其中 第一複數個導電構件係直接位在該導熱構件的金屬上。 11. 一種形成一微電子組件的方法，其包含： 直接在一支撐基材的半導體材質上及在一晶粒的一支 撐基材的第一側上形成一金屬層，該晶粒具有一微電子電 路其被形成在該支撐基材的一第二側（相反側）上； H 形成一開口於該金屬層中； 形成熱電模組於該金屬層中，該金屬層介於該熱電模 組與該晶粒之間； 設置一熱散佈器，其熱耦合至該熱電模組； 形成一開口穿過該熱散佈器；及 設置一散熱器的底座，該散熱器具有從該底座延伸出 的鯧片，使得該底座被熱耦合至該熱電模組。 12. 如申請專利範圍第11項所述之方法，其中該金 φ屬層是被電鑛的。 13. 如申請專利範圍第11項所述之方法，其中該金 屬層包括銅。 14. 如申請專利範圍第1 1項所述之方法，其中該熱 電模組只被形成在該支撐基材的第一區域上，用以選擇性 地冷卻與該支撐基材的一與第二區域相反的該第一區域。 15. 如申請專利範圍第14項所述之方法，其中當該 微電子電路被操作時，其會在該第一區域內產生一熱點。 16. 如申請專利範圍第15項所述之方法，其中該金 -3- 1324818 屬層將熱從該熱點散佈到該熱電模組上。 1 7 . —種微電子組件，其包含： 一半導體材質的支撐基材； 一微電子電路，其被直接形成在該支撐基材的半導體 材質上； 一金屬層，其被直接形成在該支撐基材的半導體材質 上及形成在該支撐基材之與該微電子電路相反的一側上， 該金屬層具有一開口 ： φ 一熱電模組，其位在該金屬層的該開口內，該金屬層 介於該熱電模組的第一側與該晶粒之間；及 一金屬熱散佈器，其被形成在該熱電模組的第二側上 ’該第二側與該第一側相反，其中該金屬熱散佈器具有一 開口。 1 8 ·如申請專利範圍第1 7項所述之微電子組件，其 中該金屬層包括銅。 1 9 ·如申請專利範圍第1 7項所述之微電子組件，其 φ 中該熱電模組只被形成在該支撐基材的第一區域上，用以 選擇性地冷卻與該支撐基材的一第二區域相反的該第一區 域。 20.如申請專利範圍第19項所述之微電子組件，其 中當該微電子電路被操作時’其會在該第一區域內產生一 熱點。 2 1.如申請專利範圍第20項所述之微電子組件，其 中該金屬層將來自該熱點的熱散佈到該熱電模,組上。 -4-
TW94102919A 2004-02-12 2005-01-31 A microelectronic assembly having thermoelectric elements to cool a die and a method of making the same TWI324818B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/778,514 US7589417B2 (en) 2004-02-12 2004-02-12 Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same

Publications (2)

Publication Number Publication Date
TW200529398A TW200529398A (en) 2005-09-01
TWI324818B true TWI324818B (en) 2010-05-11

Family

ID=34838194

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94102919A TWI324818B (en) 2004-02-12 2005-01-31 A microelectronic assembly having thermoelectric elements to cool a die and a method of making the same

Country Status (5)

Country Link
US (1) US7589417B2 (zh)
JP (1) JP4464974B2 (zh)
CN (1) CN1914725B (zh)
TW (1) TWI324818B (zh)
WO (1) WO2005081313A2 (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100257871A1 (en) * 2003-12-11 2010-10-14 Rama Venkatasubramanian Thin film thermoelectric devices for power conversion and cooling
US7523617B2 (en) * 2004-10-22 2009-04-28 Nextreme Thermal Solutions, Inc. Thin film thermoelectric devices for hot-spot thermal management in microprocessors and other electronics
US8063298B2 (en) * 2004-10-22 2011-11-22 Nextreme Thermal Solutions, Inc. Methods of forming embedded thermoelectric coolers with adjacent thermally conductive fields
WO2006113607A2 (en) * 2005-04-18 2006-10-26 Nextreme Thermal Solutions Thermoelectric generators for solar conversion and related systems and methods
US20060243315A1 (en) * 2005-04-29 2006-11-02 Chrysler Gregory M Gap-filling in electronic assemblies including a TEC structure
SG139573A1 (en) * 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
JP5522943B2 (ja) * 2008-01-29 2014-06-18 京セラ株式会社 熱電モジュール
TWI405361B (zh) * 2008-12-31 2013-08-11 Ind Tech Res Inst 熱電元件及其製程、晶片堆疊結構及晶片封裝結構
US8035218B2 (en) * 2009-11-03 2011-10-11 Intel Corporation Microelectronic package and method of manufacturing same
US20110132000A1 (en) * 2009-12-09 2011-06-09 Deane Philip A Thermoelectric Heating/Cooling Structures Including a Plurality of Spaced Apart Thermoelectric Components
CN102194811B (zh) * 2010-03-05 2012-12-05 中芯国际集成电路制造(上海)有限公司 热电装置
FR2963165A1 (fr) 2010-07-22 2012-01-27 St Microelectronics Crolles 2 Procede de generation d'energie electrique dans un dispositif semi-conducteur, et dispositif correspondant
US8492788B2 (en) * 2010-10-08 2013-07-23 Guardian Industries Corp. Insulating glass (IG) or vacuum insulating glass (VIG) unit including light source, and/or methods of making the same
FR2966268B1 (fr) * 2010-10-18 2013-08-16 St Microelectronics Rousset Procédé comprenant une détection d'une remise en boitier d'un circuit intégré après une mise en boitier initiale, et circuit intégré correspondant.
US8816494B2 (en) * 2012-07-12 2014-08-26 Micron Technology, Inc. Semiconductor device packages including thermally insulating materials and methods of making and using such semiconductor packages
CN102800636B (zh) * 2012-08-28 2015-02-18 中国科学院微电子研究所 电子元件封装体及其制造方法
DE102012110021A1 (de) * 2012-10-19 2014-04-24 Bpe E.K. Multifunktions-Mikroelektronikbauteil und Herstellungsverfahren dafür
WO2014159572A1 (en) * 2013-03-14 2014-10-02 Gmz Energy Inc. Thermoelectric device fabrication using direct bonding
US9559283B2 (en) 2015-03-30 2017-01-31 International Business Machines Corporation Integrated circuit cooling using embedded peltier micro-vias in substrate
US9941458B2 (en) * 2015-03-30 2018-04-10 International Business Machines Corporation Integrated circuit cooling using embedded peltier micro-vias in substrate
US10068875B2 (en) 2015-10-22 2018-09-04 Micron Technology, Inc. Apparatuses and methods for heat transfer from packaged semiconductor die
US11152279B2 (en) * 2018-03-26 2021-10-19 Raytheon Company Monolithic microwave integrated circuit (MMIC) cooling structure
US20230268244A1 (en) * 2022-02-21 2023-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal dissipation in power ic using pyroelectric materials

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4483341A (en) * 1982-12-09 1984-11-20 Atlantic Richfield Company Therapeutic hypothermia instrument
US5284287A (en) * 1992-08-31 1994-02-08 Motorola, Inc. Method for attaching conductive balls to a substrate
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
US5435482A (en) * 1994-02-04 1995-07-25 Lsi Logic Corporation Integrated circuit having a coplanar solder ball contact array
US5543661A (en) * 1994-05-31 1996-08-06 Sumitomo Metal Ceramics Inc. Semiconductor ceramic package with terminal vias
JP2937791B2 (ja) * 1995-03-14 1999-08-23 日本電気株式会社 ペルチエクラーク
US5712448A (en) * 1996-02-07 1998-01-27 California Institute Of Technology Cooling device featuring thermoelectric and diamond materials for temperature control of heat-dissipating devices
JPH10200208A (ja) * 1997-01-09 1998-07-31 Nec Corp 半導体レーザーモジュール
US5821168A (en) * 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
SE515158C2 (sv) 1999-02-10 2001-06-18 Ericsson Telefon Ab L M Halvledaranordning med jordanslutning via en ej genomgående plugg
US6230497B1 (en) 1999-12-06 2001-05-15 Motorola, Inc. Semiconductor circuit temperature monitoring and controlling apparatus and method
US6455930B1 (en) * 1999-12-13 2002-09-24 Lamina Ceramics, Inc. Integrated heat sinking packages using low temperature co-fired ceramic metal circuit board technology
US6614109B2 (en) * 2000-02-04 2003-09-02 International Business Machines Corporation Method and apparatus for thermal management of integrated circuits
US6528907B2 (en) * 2000-04-07 2003-03-04 Mirae Corporation Linear motor
US6424533B1 (en) * 2000-06-29 2002-07-23 International Business Machines Corporation Thermoelectric-enhanced heat spreader for heat generating component of an electronic device
US6700053B2 (en) 2000-07-03 2004-03-02 Komatsu Ltd. Thermoelectric module
US6548894B2 (en) 2000-11-30 2003-04-15 International Business Machines Corporation Electronic module with integrated programmable thermoelectric cooling assembly and method of fabrication
US6512291B2 (en) * 2001-02-23 2003-01-28 Agere Systems Inc. Flexible semiconductor device support with integrated thermoelectric cooler and method for making same
US6634770B2 (en) * 2001-08-24 2003-10-21 Densen Cao Light source using semiconductor devices mounted on a heat sink
DE10238843B8 (de) * 2002-08-20 2008-01-03 Infineon Technologies Ag Halbleiterbauelement
US7034394B2 (en) * 2003-10-08 2006-04-25 Intel Corporation Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same

Also Published As

Publication number Publication date
US20050178423A1 (en) 2005-08-18
WO2005081313A3 (en) 2005-11-24
JP4464974B2 (ja) 2010-05-19
CN1914725B (zh) 2011-11-23
JP2007523478A (ja) 2007-08-16
CN1914725A (zh) 2007-02-14
TW200529398A (en) 2005-09-01
US7589417B2 (en) 2009-09-15
WO2005081313A2 (en) 2005-09-01

Similar Documents

Publication Publication Date Title
TWI324818B (en) A microelectronic assembly having thermoelectric elements to cool a die and a method of making the same
JP4903048B2 (ja) ダイを冷却するための熱電素子を有するマイクロエレクトロニクスアセンブリ及びその製造方法
JP5846894B2 (ja) 内蔵熱電冷却機を備えるマイクロエレクトロニクス・アセンブリおよびその製造方法
JP4979768B2 (ja) 熱伝導性複合インタフェース、それを用いた冷却型電子アセンブリ、及び、冷却アセンブリと熱発生電子デバイスとの結合方法
JP5442368B2 (ja) 直付リード線を備えるｉｃチップパッケージ
TW200818427A (en) Thermal improvement for hotspots on dies in integrated circuit packages
TW200425439A (en) Thermally enhanced electronic flip-chip packaging with external-connector-side die and method
TWI292611B (en) Bottom heat spreader
JP2982126B2 (ja) 半導体装置およびその製造方法
TWI325617B (en) Chip package and method of manufacturing the same
TWI825118B (zh) 半導體裝置及半導體裝置的製造方法
JP2006216642A (ja) 熱電素子
US20170273185A1 (en) Fabrication method of circuit structure
TW200418161A (en) Semiconductor chip package and method for manufacturing the same
JPH10233473A (ja) 半導体素子の放熱構造とその放熱方法
CN111987052A (zh) 半导体封装
TW200933839A (en) Packaged integrated circuits and methods to form a stacked integrated circuit package
JP5289921B2 (ja) 半導体装置、及び、半導体装置の製造方法
TWI270964B (en) Package structure
JP4371946B2 (ja) 半導体装置及びその基板接続構造
TWI261887B (en) IC substrate structure and fabrication method
CN112786555A (zh) 一种功率模块封装结构及功率模块制造方法
JP2022078004A (ja) 半導体素子パッケージ及びその製造方法
JPH11163229A (ja) 半導体装置およびその製造方法
CN113035802A (zh) 半导体封装结构及其形成方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees