TWI261887B - IC substrate structure and fabrication method - Google Patents

Abstract

The present invention provides an IC substrate, in which a plurality of separated bumps are formed on the substrate by a number of etching/deep-forming, and a connection object disposed on a surface of the bump and is used to make the bumps mutually isolated and to form a patterned alignment. At least a metal layer is disposed inside the connection object, and the metal layer is electrically connected with the bumps as the contact for chip connection. The present invention possesses both the plural conductive bumps and the chip substrate having good heat dissipation performance, and the present invention directly mounts chips on the metal substrate so as to provide the chip with good heat-dissipating path.

Description

1261887 Five% invention description U), [Technical field to which the invention belongs]

The invention relates to a structure and manufacturing technology of a Christie 4, a JL, a slab, and a slab, and a semiconductor carrier board of the 3 ancient layer and a multi-conductor having a plurality of metal bumps. Method [Prior Art] According to the rapid change of the electronic f, the electronic product is oriented toward the weight _ and the small size of the design 4 in the semiconductor post-packaging process jLead frame) and the semiconductor carrier (IC substrat The _槠, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , However, as the power is clamped to its pin count, the helmet is forcing the user to "supplement" the "add" makes it connect and the simple line k is sufficient for the pin; and the lead frame can only be used for ▲• In this case, another BGA package structure with multiple pins has been developed. The 糸 糸 uses a printed circuit board (PCB) as a way to carry the pins around the metal lead frame, 2;; i: To the 4th episode of the slice caused the dispersion of this BGA package Strong, making < * ° and the cooling effect due to multi-functional oven wafer bump encapsulation process and the number of pads connected to the rapid engagement five ^ 1,261,887, described the invention (2)

This causes disadvantages such as an increase in manufacturing cost, a decrease in manufacturing process yield, and an excessively high manufacturing cost. In view of the above, the present invention is directed to an upper body carrier plate and a method for manufacturing the same, and an effective solution; a semi-guided problem is proposed. The double solution is to solve the above-mentioned conventional packaging technology. The wafer of the present invention is directly pre-formed as a bump according to a conductive layer, and the bumps are mutually metal-layered, and the light-emitting layer of the present invention is formed by a light-resisting layer or a deep-controlled capacitor. And this jinming semi-guided on the following table, for the purpose of the first, is to provide _ plug-in JL if H stomach & kind of conductor carrier board, using the recording of multiple conductive & 嫂, bulge and exothermic wafer loading The purpose of filling the surface of the connecting layer and the metal plate with the photoresist layer and the first light is on the carrier plate, so that the manufacturing cost, a semi-conductive surface is arranged to form a pattern layer electrical connection body carrier manufacturing surface system Forming a patterned light to form a plurality of resistive layers, respectively, in the gold, and the surface is provided under the joint, and the crystal and the step carrier are connected to form a bump, and a half piece is reduced. According to the method of connecting, the first pattern is formed as a cover of a cover, and the rear conductor carrier can provide a good heat dissipation path and structure. The inner wafer is stepped with a plurality of spacers of the photoresist metal plate to provide at least a contact point for each of the electrodes. A gold layer and a first button are provided to remove the first patterned upper surface and each of the gold and the second layer The first recess of the photoresist layer is formed in the metal and forms a 1261887. The invention (3) " a second patterned photoresist layer, wherein the first recess is opposite to the lower surface of the metal plate without a second pattern The photoresist layer is etched or deeply controlled by the second patterning as a mask to form a wire layer and a bump layer, respectively, as a connecting wafer or a printed circuit board. The purpose of the present invention, the technical content, the features and the realization thereof are more easily understood by the specific embodiments in conjunction with the accompanying drawings. The invention is a semiconductor carrier, please Referring to the first figure, the surname structure includes a plurality of spaced apart bumps 10, and a joint & 12 is disposed on the surface of the bump 1〇, which is disposed on the surface of each bump 1 and each bump 1 The ruthenium is also disposed in the conjugate 12 by means of the 'links 1 2 spaced apart from each other and forming a patterned arrangement, such as a matrix arrangement' followed by multiple selective etching processes. Electrically connected to the bump 1 , as a contact for connecting the wafer, and the surface of each bump 10 can be further treated by electroless plating or electroplating for surface treatment to provide a conductive layer 16 and further in the bump A surface of the crucible and a solder mask layer 18 are formed on the surface of the joint 12 to provide protection for the metal material 1 2 and the metal layer 14 from being damaged. Thus, the description of the first basic structure of the present invention is completed. In addition, another basic type structure, as shown in the second figure, the semiconductor carrier structure is different from the above basic type in that the connector 丨 2 is disposed at a position of the protrusion J 0 , as shown in the figure. The two ends, and the middle of the carrier board can be set for the wafer. In addition, there are semi-conductors with multiple layers (three or more layers)

1261887

The body carrier plate structure, as shown in the third figure, the carrier plate of this type is a structure in which the connecting body 1 2 and the metal layer 14 are alternately stacked in the original first basic type structure by using multiple selective residual methods. Made on the top. Therefore, in the process of fabricating the multilayer semiconductor carrier structure, the system of the basic semiconductor carrier structure is used, so the following fabrication process is explained by the basic semiconductor carrier plate being Φ. The manufacturing method of the semiconductor carrier board is as shown in the fourth (3) to the fourth ((in the figure, a metal plate 20 is first provided, and the first and second surfaces of the metal plate 2 are divided into two to form a first patterned light). The resist layer 22 and a first photoresist layer 24 are followed by a mold-patterned photoresist 22 as a mask, and the metal plate 2 is etched or deeply controlled to form a plurality of first grooves 26, and then the first layer is removed. The patterned photoresist layer and the first photoresist layer 24 are shown. Then, on the metal plate 20, the connector 28 can be one of or a combination thereof, and then the portion is removed on the metal plate. In the manner of forming a plurality of second recesses 3 2, 'the metal as the metal layer portion is divided by the phenotype of the plurality of metal layers 34 and the joint 28, the joints 28 and the gold solder mask layer 3 6 The joints 28 8 slots 35 can be protected, so that some of the metal layers 30 are filled with the surface of each of the fourth (e) and fourth (h) and each of the first recesses 26 as insulation, conductivity and The electrical material is provided on the joint 28 with a metal layer 3, a surface 28 of the joint 28 and the metal layer 30, and in each of the second grooves 32. The inner wall is electrically connected to the metal plate 20, and the layer 30 is transferred by image transfer or deep grooved to form a groove 3 0 ' to expose the joint 2 8 . Please refer to the fourth (i) to the fourth (1) A solder mask layer 36 is further disposed on the genus layer 30, and the solder mask layer 36 is provided with a plurality of connections.

Page 8 1261887 V. Description of the invention (5) 'Exposure, as electrical', the surface is reshaped separately, and is placed on the surface of the solder mask layer 36 and the metal layer 2, but in the resistive layer 38 and - The second patterned photoresist is not provided with the second pattern. The opposite surface of the metal plate 2 is a mask, and the butt is then patterned with a second patterned photoresist to form an ίί=2° plate. The lower surface is subjected to (4) or deep control - the metal is further electrolessly electroplated, "electroplating, metal surface treatment, 4 吏 bump Ί for packaging process wire bonding or welding. The conductive layer 44 is made of an insulating material of the above-mentioned carrier structure, and the spacers; the fef·coarse bumps 42 are non-conductive bumps 42 and the connectors 28 are electrically conductive. If the material is the material, the bump 42 corresponding to the spacer is electrically conductive, and when the material 28 is a special electrical material, the corresponding bump 42 has special conductivity. The bumps 42 can be connected to the layers by the metal layers 30, 34 to make the lines have different electrical properties. When the wafer is mounted, the first basic type is first described. As shown in FIG. 5, a wafer 46 is placed on the surface of the solder mask layer 36, and then wire bonding or flip chip bonding is performed. The Flip Chip method is electrically connected to the contact slot g, and then the bump 42 is soldered to a circuit board, and a protective layer 48 is further disposed on the I wafer 46 to prevent the wafer from being damaged by external force. Then, the second basic type is used in the wafer assembly. Referring to the sixth figure, the wafer 46 is placed on the bump 42 and electrically connected to the contact slot 35 by wire bonding. Description of the first and second basic seven states of the invention.

Page 9 1261887 V. DESCRIPTION OF THE INVENTION (6) The carrier layer of the layer structure is applied to the wafer structure. Similarly, the wafer 46 is placed on the metal layer of the solder mask layer 46, and the wafer 46 is connected by wire bonding. The dot slot 35 is electrically connected. As shown in the seventh figure, the arrangement and the manner of use are the same, and will not be discussed here. Alternatively, the wafer 46 may be disposed on the bump 42 by a plurality of solder balls 50. On the other side, solder the other side of the carrier board to the circuit board, as shown in the eighth figure. Therefore, in the present invention, each bump 42 is electrically conductive/non-conductive and electrically conductive by the material of the joint 28. Therefore, the present invention utilizes variations in the properties of the bonding material 28 to make the wiring of the wiring sheet more diverse, and thus can be applied to various semiconductor packages, and the present invention directly mounts the wafer 44 to the metal carrier board, so that the wafer 44 is good. The heat dissipation path and pre-made conductive bumps by the metal carrier plate reduce manufacturing costs and steps. In addition, by changing the material of the joint material 28, the application of the Ϊ 结构 结构 结构 , , , 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属Replace the carrier board of the existing wafer package. The description of the present invention is by way of example, and the purpose of the present invention is to determine the preferred embodiment of the present invention from the present and the present according to Besch, rather than the limit of 'Θ神所-点少楚围, Therefore, all other modifications or modifications that do not depart from the disclosure of the present invention are still included in the scope of the following, +, and 丄 patents. Still should be included in the application of 3 below

1261887 Brief description of the schema [Simplified description of the diagram] The first diagram is the first basic semi-conducting of the invention. The first figure is the second basic type semi-conducting to solid-state of the present invention. The three figures are applied to the multi-layer patterned carrier board according to the invention; the fourth (a) to fourth (!) pictures are respectively in the NN + i (one) surface Do not think about it. The step constructs a cross-sectional view.乍+Conductor Carriers Each of the fifth figures is a publication of the first basic type of the invention applied to the wafer assembly. "/, thought ^ = figure is the second schematic diagram of the invention applied to the wafer structure. FIG. 7 is a cross-sectional view of the multi-layer patterned carrier applied to the wafer structure of the present invention: Another multilayer patterned carrier is not intended for use in wafer facets.咄 咄 咄 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Plate 24 first photoresist layer 28 link 32 second groove 3 5 contact groove 3 8 second photoresist layer

Page 11 1261887

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Claims (1)

1261887 ^------ /, λ application patent range 1 A semiconductor carrier board, the structure comprising: a plurality of spaced apart bumps; a multiplier ~ linker, which is disposed on the surface of the bumps, the bump The junctions are spaced apart from each other to form a patterned arrangement; and at least one metal layer is disposed in the connector, electrically connecting the f' as a junction of the connection wafer. For example, the semiconductor carrier board according to claim 1 of the patent scope, the direct medium & master /, τ, the niche surface can be subjected to a surface treatment for providing a conductive layer. 4. The semiconductor carrier according to claim 2, wherein the electrical layer is selected from the group consisting of electroless plating or electroplating, and the surname is as described in item 1 of the patent application. The semiconductor carrier board, wherein the junction is an insulating material, the corresponding bump is non-conductive, and the semiconductor carrier is as described in the scope of the patent application. The conductive material corresponds to the bump which is electrically conductive. The semiconductor carrier according to the first aspect of the invention, wherein the connector is a special electrical material, corresponding to Μ special conductivity. The semiconductor carrier board of the invention of claim 1, wherein the surface and the joint are further formed with a solder mask ('Solde: M cl S Κ ) 〇8, The semiconductor carrier of claim 1, wherein the 'layer' is formed by multiple selective etching methods. ^ 9. The semiconductor carrier board as described in claim i of the patent scope, 兀. In 1261887, the patent application scope is that the metal layer and the joint are disposed on the surface of the joint and the metal layer a plurality of times, and the multilayer patterned carrier is completed by multiple etching or deep manner. The semiconductor carrier of claim 1, wherein the wafer is electrically connected to the wiring layer by wire bonding or FI ip chip. The semiconductor carrier according to claim 10, wherein the wafer is provided on the bump by flip chip. U. The semiconductor carrier of claim 10, wherein a protective layer is further disposed on the electric wafer to prevent the wafer from being damaged by external force. 13 The semiconductor carrier board according to claim 1, wherein the pattern arrangement is a matrix arrangement. "14 manufacturing methods of semiconductor carrier boards, including the following steps: photoresist ί: a slab" whose upper and lower surfaces are respectively formed - a - patterning. The photoresist layer and a first photoresist layer; 'The photoresist is a mask, the metal plate is etched or a plurality of grooves are formed, and then the first pattern is removed: the layer and the first photoresist layer; Lu is on the metal plate: # -XlriA- surface and a mother inserts a joint in the groove, and a metal layer is disposed on the joint; initially forming a second surface on the surface of the metal layer and the +厪 photoresist layer and forming a lower surface of the -0j plate The gold; the photoresist layer is located in the region of the lower surface of the recess relative to the 53⁄4 I plate, the second patterned photoresist A ^, and - 9 is the mask, the metal layer And the metal surface Η Page 14! 261887 ^----------- - VI. Application for patent scope: -------- $ The lower surface is subjected to residual or deep control to form a wire layer. And a plurality of convex ghosts respectively as connecting chips or connecting printed circuit boards. The method for fabricating a semiconductor carrier as described in claim 14 of the invention, wherein the step of forming the bumps further comprises disposing a solder mask layer on the metal layer. The method for producing a semiconductor carrier according to claim 14 wherein the connector is one of an insulating material, a conductive material, and a special electrical material. ^ The manufacturing method of the semiconductor carrier board of claim 14, wherein the bonding material, the metal layer and the wiring layer are repeatedly disposed before or after the dream of forming the bumps. And the steps of multiple etching/deep-controlled molding are performed to achieve a multi-bump multi-layer patterned carrier. 18. The method of fabricating a semiconductor carrier according to claim 14, wherein the semiconductor carrier is available, and the wafer is provided by wire bonding or flip chip. The method of fabricating a semiconductor carrier according to claim 18, wherein the wafer is provided on the bump in a flip chip manner. 20. The manufacturer of a semiconductor carrier as described in claim 14 wherein the 'after forming the plurality of bumps' is subjected to a surface treatment step to form a conductive layer on the surface of the bumps. 21. The method of fabricating a semiconductor carrier according to claim 2, wherein the conductive layer is selected from the group consisting of electroless plating or electroplating. Page 15