TWI310241B - Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer - Google Patents

Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer Download PDF

Info

Publication number
TWI310241B
TWI310241B TW092133982A TW92133982A TWI310241B TW I310241 B TWI310241 B TW I310241B TW 092133982 A TW092133982 A TW 092133982A TW 92133982 A TW92133982 A TW 92133982A TW I310241 B TWI310241 B TW I310241B
Authority
TW
Taiwan
Prior art keywords
layer
strained
mis mis
strain
germanium
Prior art date
Application number
TW092133982A
Other languages
English (en)
Chinese (zh)
Other versions
TW200421608A (en
Inventor
Haihong Wang
Paul R Besser
Jung-Suk Goo
Minh Van Ngo
Eric N Paton
Qi Xiang
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200421608A publication Critical patent/TW200421608A/zh
Application granted granted Critical
Publication of TWI310241B publication Critical patent/TWI310241B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3254—Graded layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
TW092133982A 2002-12-31 2003-12-03 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer TWI310241B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/335,447 US6730576B1 (en) 2002-12-31 2002-12-31 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer

Publications (2)

Publication Number Publication Date
TW200421608A TW200421608A (en) 2004-10-16
TWI310241B true TWI310241B (en) 2009-05-21

Family

ID=32176300

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092133982A TWI310241B (en) 2002-12-31 2003-12-03 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer

Country Status (8)

Country Link
US (1) US6730576B1 (https=)
EP (1) EP1579485A2 (https=)
JP (1) JP2006512766A (https=)
KR (1) KR20050091051A (https=)
CN (1) CN100365766C (https=)
AU (1) AU2003286810A1 (https=)
TW (1) TWI310241B (https=)
WO (1) WO2004061920A2 (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657276B1 (en) * 2001-12-10 2003-12-02 Advanced Micro Devices, Inc. Shallow trench isolation (STI) region with high-K liner and method of formation
US6902991B2 (en) * 2002-10-24 2005-06-07 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
US6657223B1 (en) * 2002-10-29 2003-12-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
US6787423B1 (en) * 2002-12-09 2004-09-07 Advanced Micro Devices, Inc. Strained-silicon semiconductor device
US7001837B2 (en) * 2003-01-17 2006-02-21 Advanced Micro Devices, Inc. Semiconductor with tensile strained substrate and method of making the same
US20040164373A1 (en) * 2003-02-25 2004-08-26 Koester Steven John Shallow trench isolation structure for strained Si on SiGe
WO2004081982A2 (en) * 2003-03-07 2004-09-23 Amberwave Systems Corporation Shallow trench isolation process
US6924182B1 (en) * 2003-08-15 2005-08-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having reduced leakage and method of its formation
US7175966B2 (en) * 2003-09-19 2007-02-13 International Business Machines Corporation Water and aqueous base soluble antireflective coating/hardmask materials
US7462549B2 (en) * 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
US7005302B2 (en) * 2004-04-07 2006-02-28 Advanced Micro Devices, Inc. Semiconductor on insulator substrate and devices formed therefrom
US20060052947A1 (en) * 2004-05-17 2006-03-09 Evelyn Hu Biofabrication of transistors including field effect transistors
JP2006108365A (ja) * 2004-10-05 2006-04-20 Renesas Technology Corp 半導体装置およびその製造方法
KR100707654B1 (ko) * 2005-07-26 2007-04-13 동부일렉트로닉스 주식회사 반도체 장치의 소자 분리 구조 및 그 형성방법
KR100707882B1 (ko) * 2005-12-14 2007-04-13 삼성전자주식회사 선택적 에피택시얼 성장 방법
EP1833094B1 (en) * 2006-03-06 2011-02-02 STMicroelectronics (Crolles 2) SAS Formation of shallow SiGe conduction channel
US7709331B2 (en) * 2007-09-07 2010-05-04 Freescale Semiconductor, Inc. Dual gate oxide device integration
US20090152590A1 (en) * 2007-12-13 2009-06-18 International Business Machines Corporation Method and structure for semiconductor devices with silicon-germanium deposits
US20100109044A1 (en) * 2008-10-30 2010-05-06 Tekleab Daniel G Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer
US20110062492A1 (en) * 2009-09-15 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. High-Quality Hetero-Epitaxy by Using Nano-Scale Epitaxy Technology
US20110068368A1 (en) * 2009-09-18 2011-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device comprising a honeycomb heteroepitaxy
CN102683210B (zh) * 2011-03-18 2020-01-24 中国科学院微电子研究所 一种半导体结构及其制造方法
US9059321B2 (en) * 2012-05-14 2015-06-16 International Business Machines Corporation Buried channel field-effect transistors
CN103730404B (zh) * 2013-12-31 2018-10-16 上海集成电路研发中心有限公司 浅沟槽隔离的制造方法
CN108281353B (zh) * 2018-01-15 2019-04-23 西安交通大学 一种扫描式高能微束x射线制备应变硅的方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982944A (ja) * 1995-09-18 1997-03-28 Toshiba Corp 歪シリコン電界効果トランジスタ及びその製造方法
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
DE19720008A1 (de) * 1997-05-13 1998-11-19 Siemens Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
US6013134A (en) * 1998-02-18 2000-01-11 International Business Machines Corporation Advance integrated chemical vapor deposition (AICVD) for semiconductor devices
JP3607194B2 (ja) * 1999-11-26 2005-01-05 株式会社東芝 半導体装置、半導体装置の製造方法、及び半導体基板
JP4406995B2 (ja) * 2000-03-27 2010-02-03 パナソニック株式会社 半導体基板および半導体基板の製造方法
US6969875B2 (en) * 2000-05-26 2005-11-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
JP4269541B2 (ja) * 2000-08-01 2009-05-27 株式会社Ｓｕｍｃｏ 半導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
JP2004519090A (ja) * 2000-08-07 2004-06-24 アンバーウェーブ システムズ コーポレイション 歪み表面チャネル及び歪み埋め込みチャネルｍｏｓｆｅｔ素子のゲート技術
US6724008B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
AU2002322105A1 (en) * 2001-06-14 2003-01-02 Amberware Systems Corporation Method of selective removal of sige alloys
US6916727B2 (en) * 2001-06-21 2005-07-12 Massachusetts Institute Of Technology Enhancement of P-type metal-oxide-semiconductor field effect transistors
JP4296726B2 (ja) * 2001-06-29 2009-07-15 株式会社Ｓｕｍｃｏ 半導体基板の製造方法及び電界効果型トランジスタの製造方法
US6974735B2 (en) * 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US6492216B1 (en) * 2002-02-07 2002-12-10 Taiwan Semiconductor Manufacturing Company Method of forming a transistor with a strained channel
US6649492B2 (en) * 2002-02-11 2003-11-18 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
JP2003249641A (ja) * 2002-02-22 2003-09-05 Sharp Corp 半導体基板、その製造方法及び半導体装置
FR2842349B1 (fr) * 2002-07-09 2005-02-18 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置

Also Published As

Publication number Publication date
WO2004061920A3 (en) 2005-01-27
CN100365766C (zh) 2008-01-30
CN1732556A (zh) 2006-02-08
WO2004061920A2 (en) 2004-07-22
EP1579485A2 (en) 2005-09-28
TW200421608A (en) 2004-10-16
AU2003286810A1 (en) 2004-07-29
US6730576B1 (en) 2004-05-04
JP2006512766A (ja) 2006-04-13
KR20050091051A (ko) 2005-09-14

Similar Documents

Publication Publication Date Title
TWI310241B (en) Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
US6902991B2 (en) Semiconductor device having a thick strained silicon layer and method of its formation
TWI338367B (en) Mosfets incorporating nickel germanosilicided gate and methods of their formation
TW497203B (en) Semiconductor device and method of manufacturing the same
TW535260B (en) Method of manufacturing semiconductor device
US7071065B1 (en) Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
TWI359464B (en) Semiconductor transistor having structural element
TWI248121B (en) A method for making a semiconductor device that includes a metal gate electrode
US20050054164A1 (en) Strained silicon MOSFETs having reduced diffusion of n-type dopants
JP2004134753A (ja) 多重の誘電率と多重の厚さを有するゲート絶縁体層を形成する方法
TW201616603A (zh) 利用佈植的可流動膜性質調諧
TW200843110A (en) Semiconductor device manufacturing method and semiconductor device
KR20110113761A (ko) 스트레인 유도 합금 및 그레이드형 도펀트 프로파일을 포함하는 인 시츄 형성되는 드레인 및 소스 영역들
TW200910467A (en) Strained channel transistor
TW200814317A (en) Semiconductor device and fabrication method thereof
TW200414374A (en) Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers
TWI362076B (en) Semiconductor structure and method for forming a semiconductor device
JP2001326352A (ja) ゲート酸化物の上側表面の窒化物形成により向上した信頼性を有する薄いゲート酸化物を形成してゲート酸化物の上側表面に窒素原子のバリヤを形成する方法及びその結果得られる製品
TWI478287B (zh) 用於在電晶體中形成含矽／鍺之汲極／源極區域以減少矽／鍺損失之方法
TW200822235A (en) Method for forming a strained channel in a semiconductor device
TW200416898A (en) Semiconductor component and method of manufacture
TWI270146B (en) Semiconductor-on-insulator (SOI) strained active areas
TWI345272B (en) A method of forming a semiconductor structure
TWI360166B (en) Method for forming a notched gate insulator for ad
JP5010589B2 (ja) 半導体デバイス製造方法及びその方法により製造した半導体デバイスを備えた半導体集積回路チップ

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees