AU2003286810A1 - Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer - Google Patents

Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer

Info

Publication number
AU2003286810A1
AU2003286810A1 AU2003286810A AU2003286810A AU2003286810A1 AU 2003286810 A1 AU2003286810 A1 AU 2003286810A1 AU 2003286810 A AU2003286810 A AU 2003286810A AU 2003286810 A AU2003286810 A AU 2003286810A AU 2003286810 A1 AU2003286810 A1 AU 2003286810A1
Authority
AU
Australia
Prior art keywords
silicon layer
strained silicon
thick strained
forming
semiconductor structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003286810A
Other languages
English (en)
Inventor
Paul R. Besser
Jung-Suk Goo
Minh Van Ngo
Eric N. Paton
Haihong Wang
Qi Xiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2003286810A1 publication Critical patent/AU2003286810A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3254—Graded layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
AU2003286810A 2002-12-31 2003-10-30 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer Abandoned AU2003286810A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/335,447 US6730576B1 (en) 2002-12-31 2002-12-31 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
US10/335,447 2002-12-31
PCT/US2003/034673 WO2004061920A2 (en) 2002-12-31 2003-10-30 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer

Publications (1)

Publication Number Publication Date
AU2003286810A1 true AU2003286810A1 (en) 2004-07-29

Family

ID=32176300

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003286810A Abandoned AU2003286810A1 (en) 2002-12-31 2003-10-30 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer

Country Status (8)

Country Link
US (1) US6730576B1 (https=)
EP (1) EP1579485A2 (https=)
JP (1) JP2006512766A (https=)
KR (1) KR20050091051A (https=)
CN (1) CN100365766C (https=)
AU (1) AU2003286810A1 (https=)
TW (1) TWI310241B (https=)
WO (1) WO2004061920A2 (https=)

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US6902991B2 (en) * 2002-10-24 2005-06-07 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
US6657223B1 (en) * 2002-10-29 2003-12-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
US6787423B1 (en) * 2002-12-09 2004-09-07 Advanced Micro Devices, Inc. Strained-silicon semiconductor device
US7001837B2 (en) * 2003-01-17 2006-02-21 Advanced Micro Devices, Inc. Semiconductor with tensile strained substrate and method of making the same
US20040164373A1 (en) * 2003-02-25 2004-08-26 Koester Steven John Shallow trench isolation structure for strained Si on SiGe
WO2004081982A2 (en) * 2003-03-07 2004-09-23 Amberwave Systems Corporation Shallow trench isolation process
US6924182B1 (en) * 2003-08-15 2005-08-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having reduced leakage and method of its formation
US7175966B2 (en) * 2003-09-19 2007-02-13 International Business Machines Corporation Water and aqueous base soluble antireflective coating/hardmask materials
US7462549B2 (en) * 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
US7005302B2 (en) * 2004-04-07 2006-02-28 Advanced Micro Devices, Inc. Semiconductor on insulator substrate and devices formed therefrom
US20060052947A1 (en) * 2004-05-17 2006-03-09 Evelyn Hu Biofabrication of transistors including field effect transistors
JP2006108365A (ja) * 2004-10-05 2006-04-20 Renesas Technology Corp 半導体装置およびその製造方法
KR100707654B1 (ko) * 2005-07-26 2007-04-13 동부일렉트로닉스 주식회사 반도체 장치의 소자 분리 구조 및 그 형성방법
KR100707882B1 (ko) * 2005-12-14 2007-04-13 삼성전자주식회사 선택적 에피택시얼 성장 방법
EP1833094B1 (en) * 2006-03-06 2011-02-02 STMicroelectronics (Crolles 2) SAS Formation of shallow SiGe conduction channel
US7709331B2 (en) * 2007-09-07 2010-05-04 Freescale Semiconductor, Inc. Dual gate oxide device integration
US20090152590A1 (en) * 2007-12-13 2009-06-18 International Business Machines Corporation Method and structure for semiconductor devices with silicon-germanium deposits
US20100109044A1 (en) * 2008-10-30 2010-05-06 Tekleab Daniel G Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer
US20110062492A1 (en) * 2009-09-15 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. High-Quality Hetero-Epitaxy by Using Nano-Scale Epitaxy Technology
US20110068368A1 (en) * 2009-09-18 2011-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device comprising a honeycomb heteroepitaxy
CN102683210B (zh) * 2011-03-18 2020-01-24 中国科学院微电子研究所 一种半导体结构及其制造方法
US9059321B2 (en) * 2012-05-14 2015-06-16 International Business Machines Corporation Buried channel field-effect transistors
CN103730404B (zh) * 2013-12-31 2018-10-16 上海集成电路研发中心有限公司 浅沟槽隔离的制造方法
CN108281353B (zh) * 2018-01-15 2019-04-23 西安交通大学 一种扫描式高能微束x射线制备应变硅的方法

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Also Published As

Publication number Publication date
WO2004061920A3 (en) 2005-01-27
CN100365766C (zh) 2008-01-30
CN1732556A (zh) 2006-02-08
WO2004061920A2 (en) 2004-07-22
EP1579485A2 (en) 2005-09-28
TW200421608A (en) 2004-10-16
TWI310241B (en) 2009-05-21
US6730576B1 (en) 2004-05-04
JP2006512766A (ja) 2006-04-13
KR20050091051A (ko) 2005-09-14

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