TWI304646B - Method of manufacturing electronic component and electronic component - Google Patents
Method of manufacturing electronic component and electronic component Download PDFInfo
- Publication number
- TWI304646B TWI304646B TW095118027A TW95118027A TWI304646B TW I304646 B TWI304646 B TW I304646B TW 095118027 A TW095118027 A TW 095118027A TW 95118027 A TW95118027 A TW 95118027A TW I304646 B TWI304646 B TW I304646B
- Authority
- TW
- Taiwan
- Prior art keywords
- electronic component
- substrate
- electrode
- hole
- outer casing
- Prior art date
Links
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- QKSKPIVNLNLAAV-UHFFFAOYSA-N bis(2-chloroethyl) sulfide Chemical compound ClCCSCCCl QKSKPIVNLNLAAV-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- G—PHYSICS
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- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P1/00—Details of instruments
- G01P1/02—Housings
- G01P1/023—Housings for acceleration measuring devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0045—Packages or encapsulation for reducing stress inside of the package structure
- B81B7/0048—Packages or encapsulation for reducing stress inside of the package structure between the MEMS die and the substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/0802—Details
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- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/12—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by alteration of electrical resistance
- G01P15/123—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by alteration of electrical resistance by piezo-resistive elements, e.g. semiconductor strain gauges
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- B81—MICROSTRUCTURAL TECHNOLOGY
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- G01P2015/0805—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration
- G01P2015/0822—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass
- G01P2015/0825—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass for one single degree of freedom of movement of the mass
- G01P2015/0831—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass for one single degree of freedom of movement of the mass the mass being of the paddle type having the pivot axis between the longitudinal ends of the mass, e.g. see-saw configuration
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
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1304646 九、發明說明: 【發明所屬之技術領域】 本發明關於作為電子零件菸揎 干I揮功旎之疋件基板被以接著 劑貼合於外殼板上之具有積層體 谓嘈體之電子零件,更詳細而 言,關於元件基板上之電極與外殼板上之電極的電性連接 構造及與電子零件之外部的電性連接部分之構造改良之電 子零件之製造方法及電子零件。 【先前技術】
以往,已有各種㈣在半導體基板上形成由三次元構造 體形成之感測器之半導體感測器裝置的提案。此種半導體 感測裝置具有可動部分,必須以可動部分之動作不受妨礙 之方式產品化且安裝。為此,採用了例如將上述半導體基 板裝入陶瓷封裝體内,將該陶瓷封裝體搭載於安裝基板 上,並藉由焊接線加以接合的方法。然而,依此方法,有 必要使用陶瓷封裝體,因此,無法避免大型化。此外,在 女1基板上以焊接線安裝時,無法避免安裝空間變大。尤 其,在與外部之電性連接部分多之半導體感測裝置的情況 中,安裝基板上因焊接線而必要有大的安裝空間。 相對於此’在下述之專利文獻1中,揭示有如圖丨〇所示 之半導體裝置101具有底基板102。底基板1〇2上固定有包 含半導體感測器之半導體基板103。半導體基板103具有包 含電極103 a之可動部。在圖1〇中,雖以簡圖方式顯示,具 有電極103 a之感測部分被作為可動部分。從而,為了設置 面向半導體基板103之可動部分的空隙A,在半導體基板 110654.doc 1304646 103之一面l〇3b側設有凹部。以設有凹部之面1〇3b作為下 面,半導體基板103被固定在底基板1〇2上。 另一方面’半導體基板1〇3上所設之電極1〇3c、1〇3(1被 接合於且電性連接於底基板上之電極102a、102b。電極 102a、102b中介底基板1〇2内所設之通孔電極而電性連接 於底基板102下面所設之電極i〇2c、i〇2d。並且,電極 102c、102d上接合有焊錫凸塊104、1〇5。 另一方面’半導體基板1 〇3之侧面及上面被藉由封膠樹 月曰106封裝。亦即’半導體基板1〇3被以底基板ι〇2及封膠 樹脂106氣密封裝。 在女裝於安裝基板上時,藉由上述焊錫凸塊1〇4、1〇5, 可t裝於女裝基板上之電極平面上。從而,能以小的安裝 空間來將半導體裝置1〇1搭載於安裝基板上。 [專利文獻1]特開2004-34073 0號公報 【發明内容】 專利文獻1所記載之半導體裝置1〇1中,如上所述,具有 可動部分之半導體基板1〇3被以底基板1〇2及封膠樹脂1〇5 氣密封裝,且可利用焊錫凸塊104、105藉由倒裝晶片壓焊 法而搭載於基板上。在此情況中,藉由焊錫凸塊1〇4、1〇5 之接合強度較弱。因此,有必要在安裝基板與底基板1〇2 間充填稱為底膠(under fill)之環氧樹脂等之接著劑,以提 高接著強度。 依此結果,安裝基板與底基板102之間的間隙不僅有焊 錫凸塊104、105,亦被上述底膠所充滿,因此,安裝基板 110654.doc 1304646 上被施加應力時,不僅焊錫凸塊104、105,經由底膠,亦 易於傳V至底基板1〇2’甚至於半導體基板1〇3。從而,半 導體基板103所包含之半導體感測器會因上述應力的影響 而有錯誤動作發生之虞。 本發明之目的在於提供一種電子零件之製造方法及電子 零件,其可解決上述先前技術之缺點,抑制在安裝於安裝 基板等後之由外部應力之傳達,可以比較小之安裝空間進 行表面安裝,並構造簡單,且可提高複數個外部連接用端 子間之絕緣電阻。 依本發明,提供—種電子零件之製造方法,其包含:準 備已設有作為電子零件而使之發揮功能的功能部、及為了 使該功能部與外部電性連接之形成於一面上之外部連接用 石電極=元件基板之步驟;在上述㈣基板上利用相對耐喷 石’丨生南之接著劑貼合相對耐喷砂性低之外殼板之步驟,·在 上=殼=利用喷砂加工,對下面存在有上述外部連接 步=二T部分!使上述接著劑露出之方式形成孔之 接著叫” 1述孔露出而藉由上述噴砂加工無法去除之 接者劑部分,#由钱刻加以去除而 露出之步驟;由上述外殼板之外表面=接用電極 與藉由上述接著劑去除且以此 之方式,形成電極膜之步驟;及藉=用電極電性連接 驟。 、之大起形成於上述外殼板之外表面上之步 本發明之電子零件之萝 上 件之“方法之特定態樣中,在形成 H0654.doc 1304646 述電極膜之前,更肖I# ^ _ 使上述外设板之至少形成有上述電 極膜之部分粗糙之步驟。 上述 依本發明之電子零件 卞又i以方去之其他特定態樣 餘刻藉由乾式蝕刻來進行。 作為 依本發明之電子零件 卞<i以方去之其他特定態樣 上述接著劑,使用聚醯亞胺系接著劑。 在本發明之電子零件之衆j ;生古土 1千之Ik方法之其他特定態樣中,更
包含以分割上述孔之方4 a m 之方式S曰囡切割上述元件基板及上述 外设板之積層體’並在上述突 你上$犬趣之側面上形成以上述孔之 内周面之一部分形成之凹部之步驟。 人依本發明之電子零件之製造方法之其他較態樣,更包 含在上述元件基板之接著有上料殼板之侧之相反侧之面 上層疊第二外殼板之步驟。 、在本u之電子零件之製造方法之其他特定態樣中,上 述第二外殼板藉由接著劑而貼合於上述元件基板上。 本發明之電子零件具有:元件基板,其係設有作為電子 零件元件而使之發揮功能之功能部;接著劑層,其係設於 上述元件基板之單面;及外殼板,其係由比上述接著劑層 财喷砂性低之材料形成,並藉由上述接著劑層貼合於上述 外Λ又板,上述元件基板之層疊有上述外殼板之面上形成有 與外部電性連接之外部連接用電極,上述外殼板上具有使 上述外邛連接用電極之至少一部分露出而底部未配置上述 接著劑層之孔,在上述外殼板之層疊有上述元件基板之側 相反側之面上,形成有外表面被賦予上述電極膜之突起, 110654.doc 1304646 二,側:之一部分由上述孔之内周面形成,並形成由上述 2已之前端面經由突起之側面至在上述孔内露出之外部連 接用電極之電極膜。 依本發明之電子零件之製造方法,可備妥已設有作為電 • &零件而使之發揮功能的功能部、及為了使該功能部與外 、彳電性連接㈣成於單面上之外料接帛電極的元件基 板,在元件基板之設有上述外部連接用電極之側的面上二 φ I用相對耐噴砂性南之接著劑貼合外殼板後,利用喷砂加 节“子下面存在有外部連接用電極一部分之部分以使接著 j路+出之方式形成孔。在此情況中,由於接著劑耐喷砂性 兩,藉由以接著劑層不會被完全去除且外殼板上會形成孔 之方式灵%噴砂加工,可實施喷砂加工成接著劑層於孔之 底部露出之狀態。 —接者’在上述孔露出而藉由上述噴砂加卫無法去除之接 ^劑部分,被藉由㈣而加以去除。如此—來,底部之接 • $劑層被去除,而使上述外部連接用電極之-部分露出。 從而,由上述外殼板之外表面至上述孔内,以能與藉由 上述接著劑去除而露出之外部連接用電極電性連接之方式 形成電極媒,可將元件基板之功能部電性連接於外殼板之 外表面上所設之電極膜。此外,藉由機械加工,在外殼板 之外表面上,形成有由上述孔之内周面形成側面之一部分 且前端面可達上述電極膜之突起’因此,利用突起之前端 面之電極媒部分’可將本發明之電子零件電氣性地連接於 安裝基板之電極平面等。 110654.doc -10- 1304646 從而’依本發明,可得到能以使上述突起抵接於元件基 板上之電極平面之方式進行表面安裝之電子零件。在此情 况中,不需要底膠等,便可利用外殼板及設於一端上之上 述突起來進行安裝。 不僅可彳于到南密度安裝,並可抑制由安裝基板側 之應力傳達。 、亦即,上述突起乃藉由加工外殼板而與外殼板一體地構 • 成,因此,不易與外殼板分離。從而’可省略底膠。據 此,^發生經由底膠之應力料,且僅由突起部分傳來 來自安裝基板側之應力。依此,可抑制對元件基板之功能 部的來自安裝基板側之應力傳達。 再加上,由於不需要底膠,因此,可實現安裝於安裝基 板上時之步驟簡化,且因上述突起係藉由機械加工形成, 可簡易地以均勻之高度形成複數個突起。從而,可提供安 裝品質優異的晶片尺寸封裝(CSP)型電子零件。 • 再者,在上述喷砂加工時,將以接著劑不會被完全去除 之方式實施喷砂加工。從而,元件基板不會被喷砂加工, 因此,不會有孔達到元件基板之虞。據此,由外殼板外表 面至孔内之電極膜將難以達到元件基板之侧面等。例如在 凡件基板為半導體基板之情況中,當半導體基板側面之不 適當之位置上形成電極時,絕緣電阻會變動,失去橋接平 衡,有偏移電壓變動,或有因電阻之絕對值變化而對加逮 度之感度變化,或有特性劣化之虞。相對於此,依本發明 則難以發生上述般之特性變動。 110654.doc 11 1304646 依此’依本發明,可簡易地提供一種csp型之電子零 件’其難以發生因外部應力所致之對偏移電壓及加速度之 感度特性變動,此外,可對安裝基板等以小的安裝空間進 行安裝,並且可省略底膠。 在形成上述電極膜之前,更包含使外殼板之至少會形成 電極膜之部分粗糙之步驟時,將可提高電極膜對外殼板表 面之密合強度。 在蝕刻以乾式蝕刻方式進行的情況中,可在防止元件基 板上所α之包含外部連接用電極及功能部之部分受到不必 要之腐蝕的狀態下,進行上述接著劑層之局部性去除。 作為上述接著劑使用聚醯亞胺系接著劑的情況中,聚醯 亞胺系接著劑耐喷砂性佳,因此,在進行噴砂加工時,易 於a又疋成不完全去除接著劑之加工條件。 在以分割上述孔之方式來晶圓切割元件基板及外殼板之 積層體,而在上述突起之側面形成以孔之内周面之一部分 形成之凹部的情況中,依本發明可提供突起之外側面設有 凹部且凹部内形成有電極膜之電子零件。並且,設有上述 突起之部分為接合於安裝基板等之電極平面上之部分,該 突起被配置於電子零件之外緣附近,因此,可提供可進= 小型之表面安裝之電子零件。 在與元件基板之外殼板接著之側為相反側之面上層疊第 一外殼板的情況,元件基板之兩面會被外殼板及第二外殼 板所封裝,因此,可提供耐環境特性及耐濕性佳之電子跫 件。 " 110654.doc •12- 1304646 ,第二外殼板以接㈣貼合於元件基板上的情況中,可 使第一外殼板易於層疊並貼合於元件基板。 本發明之電子零件中,在元件基板上乃中介接著劑層貼 合外殼板,且與該接著劑層之耐喷砂性相比,外殼板之耐 噴砂性較低,因此,在依本發明之電子零件之製造方法, 藉由噴砂加工形成孔的情況中,易於以接著劑層會在孔之 底部殘存之方式實施喷砂加工。接著,易於依本發明藉由 蝕刻而僅去除在孔之底部露出之接著劑部分。從而,在外 设板之外表面上形成電極膜時,將電極膜形成至孔之底 部,可使電極膜接合於在孔之底部上露出之外部連接用電 極。 從而,在本發明之電子零件中,在突起形成後,會形成 由突起之前端面至上述外部連接用電極之電極膜,因此, 可提供能利用該突起而表面安裝於安裝基板等,並難以受 到來自安裝基板側之應力之影響的CSP型之電子零件。 【實施方式】 以下’藉由參照圖式來說明本發明之具體之實施方式, 闌述本發明。 在本實施方式中’作為電子零件,製造了圖2以立體圖 顯示之半導體感測裝置。圖3係圖2所示之半導體裝置之分 解立體圖。在說明本實施方式之製造方法之前,首先說明 上述半導體感測裝置之概略構造。 半導體感測裝置1具有:作為元件基板之半導體基板2、 半導體基板2之單面上層疊之外殼板3、及半導體基板2之 110654.doc -13- 1304646 另一面上形成之第二外殼板4。 半導體基板2在本實施方式中,具有作為具有可動部之 半導體感測器的加速度感測器。該加速度感測器可分別檢 測出相互垂直之X軸、γ轴及Z軸之三軸方向上之加速度。 在此,將與矩形板狀之半導體基板2垂直之方向作為2轴, 並將平面觀察半導體基板2時之長邊方向作為γ軸,短邊方 向作為X軸。半導體基板從而具有與χγ平面平行之上面及 下面。 此外,半導體基板2内之半導體感測器之構造本身並無 特別之限制,因此,稍後簡單地說明半導體基板2内之加 速度感測器之構造。 外设板3藉由接著劑層5而被接著於半導體基板2上。作 為該接著劑,使用比外殼板3耐喷砂性高之接著劑。此係 為了藉由噴砂加工在外殼板3上開孔時,避免接著劑5在孔 之底部被完全去除。亦即,接著劑層5在喷砂加工時會發 揮權板之功能。作為構成上述般之接著劑層5的接著劑, 使用聚酿亞胺系接著劑或環氧系接著劑,在偏好上,則使 用耐噴砂性高之聚醯亞胺系接著劑。 此外’如圖3所示,在第二外殼板4之上面,形成有凹部 凹。卩4a乃為了形成不妨礙半導體基板2之加速度感測 器之可動部分2a之動作之空隙而設。 雖無法由圖2及圖3看出,外殼板3的下面亦設有同樣的 凹部。從而,半導體基板2之加速度感測器之上下,確保 有為了不妨礙半導體感測器之可動部分2 a之動作之空隙。 110654.doc 1304646 外殼板3及第二外殼板4具有與半導體基板相同的平面形 狀,亦即具有相同的矩形形狀、外殼板3及第二外殼板4在 本實施方式中,由耐熱玻璃所構成。 此外,外殼板3、4並不限於耐熱玻璃,亦可由鋁土等之 絕緣性陶瓷及合成樹脂等之適當的合成材料來構成。此 外’在本發明中’外殼板3在耐噴砂性上有必要比上述之 接著劑層5還低。 此外,由於偏好在使用時以迴焊法等來搭載於安裝基板 上,因此,以耐熱性優異之耐熱玻璃或陶瓷來形成外殼板 3、4為佳。 此外,對於外殼板4,並無必要以耐喷砂性低之材料來 構成。 外豉板3具有矩形形狀,然而,在與被層疊於半導體基 板2之側為相反側之面3a上有複數個突起扑。突起儿由與 外殼板3—體地以相同材料所構成。上述般之複數個突起 3b,如後述般地,藉由機械加工構成外殼板3之材料來形 成。複數個突起3b由於與外殼板3以相同之材料一體構 成,因此,難以由外殼板3脫落。 另方面,在外设板3之一對長邊側上延伸之侧面3c、 3d上,設有複數個凹部3ee複數個凹部“分別對應於複數 個突起3bL設β突_之前端面上形成有端子電極 7並且,凹部36内形成有連接電極8。連接電極8被連接 於端子電極7,經由突起讣之側面而延伸至凹部“内,達 到外殼板3之下面側。 110654.doc 1304646 另一方面,如圖3所示,半導體基板2之上面形成有為了 使上述加速度感測器與外部電性連接之複數個外部連接用 電極9。並且,各外部連接用電極9連接於各連接電極 從而,上述加速度感測器被電性連接於外殼板3之突起 3b上所形成之端子電極7。 此外,上述端子電極7及連接電極8所形成之面以被粗糙 化成面粗度在#200至2000之範圍佳,並以#6〇〇左右為更 佳。在上述般之粗面時,可提高被形成之端子電極7及連 接電極8之密接強度。 接著,參照圖1(a)至(e)來說明上述半導體裝置丨之製造 方法。 如圖1(a)所示,首先備妥作為元件基板之半導體基板 2A。在此半導體基板2A之上下,中介接著劑層5、6,先 層疊外殼板3A及外殼板4A而貼合。 接著,如圖1(b)所示,由外殼板3A之上面,藉由喷砂法 在下方存在外部連接用電極9之部分形成孔3f。在此情況 中’硬化後之接著劑層5之财喷砂性會比外殼板3 a之耐喷 砂性還高。從而,以藉由喷砂而接著劑層5在孔3f之底部 不會被完全去除之方式進行喷砂加工。據此,如圖丨(b)所 示’雖藉由喷砂加工而形成孔3f,惟孔3f之底部殘留有接 著劑層5。 此外’在孔3 f中’被賦予了錐度而成為孔徑由外殼板3 a 之上面側向下面側縮小之狀態。此係因為藉由喷砂加工來 形成孔3f,自然會賦予錐度之故。進一步而言,孔3f中沒 110654.doc -16- 1304646 有職予上述錐度亦可。然而,藉由形成錐度,在孔奵的上 方開口緣處將難以發生後述之電極膜之斷線。 士接著’藉由㈣去除在㈣之底部露出之接著劑層5。 。亥钕刻乃藉由乾式蚀刻或濕式餘刻來進行,然而,為了防 止在孔3f之底部露出之作為外部連接用電極9及功能部分 之半導體感須J器等之腐# ’以使用乾式钱刻為佳。
藉由此乾式姓刻,如圖i⑷所示,在孔3f之底部露出之 接著劑層部分會被去除,使得外部連接用電極9露出。 亦即,孔3f被配置於在底部露出之接著劑層下方配置有 上述外部連接用電極9之部分。從而,當藉由上述蝕刻去 除接著劑層之一部分時,原本位於接著劑層5下方之外部 連接用電極9便會露出。 從而之後,在外殼板3A之上面形成如圖1(d)所示之電極 膜7A。在此情況中,電極膜7八乃藉由濺鍍或蒸鍍等之適 當之方法所形成。 如圖1(d)所示,上述電極膜7入由外殼板3A之上面至上述 孔3 f内,設置成與在孔3 f底部露出之外接電極9電性連接。 如上所述,由於,孔3f内賦予有錐度,因此,在孔3f之上 方開口緣處難以發生上述電極膜7A之斷線。從而,如上所 述,孔3f内以賦予有錐度為佳。 此外,在如上所述般地形成電極膜7A後,亦可在孔芥内 進一步充填導電性接著劑等,以補強電性連接部分,且提 高電性連接之可靠性。 之後,以在形成上述電極膜7A後,在電極膜7A上形成 110654.doc -17- 1304646 鍍膜為佳。此鍍膜以鍍上Sn或焊錫之方式來進行,為提高 在表面安裝本實施方式之半導體裝置時之焊接性所形成。 然而,上述鍍膜並不一定需要形成,例如使用導電漿料來 安裝時,並不一定需要設置鍍膜。 接著,如圖1(e)所示,進行使用晶圓切割機之研磨等之 機械加工,在母板之積層體之上面形成複數個突起3b。該 突起3b乃以在外殼板3A之上面殘留突出之複數個突起儿之 方式研磨而形成。從而,突起补乃藉由與外殼板3A相同之 材料一體地構成。 此外,上述突起3b之前端面上,殘留有上述電極膜7八之 一部分,以電極膜7A由突起3b之前端面經由侧面而至孔3f 般地形成突起3b。亦即,突起3b被形成於設有上述孔奵之 部分的内側側面。此外,在此之内側係指在最終經由切割 所得到之半導體感測裝置!中,由於,突起3b會被設在外 殼板3之外圓側邊所開口之凹部3e之内側,因此,内側意 指在最終得到之各個半導體感測裝置丨中之内側。 接著切割母板之積層體,如圖1 (e)所示般地,得到各 個半導體感測裝置i。切割以沿著孔^之中央部分而去除 母板之積層體之一部分之方式來進行。藉由切割,上述電 極膜7A會被切斷’形成端子電極7及與端子電極了連接之連 接電極8。藉此,可得到在突起补之外側上配置有藉由上 述孔3f之切割而形成之凹部“,且該凹部>内配置有上述 連接電極8之構造。亦即,㈣易地得到突起3b之外侧面 上配置有凹部3e之半導體感測裝置1。 110654.doc -18- 1304646 由上述製造方法可知,在本實施方式中,對於耐喷砂性 相對較低之外殼板3使用喷砂性相對較高之接著劑層5,因 此,在孔3f之形成時,易於以藉由喷砂加工不會完全去除 接著劑層之條件進行喷砂加工。亦即,可使接著劑層5在 喷砂加工時發揮作為檔板之功能。 藉此,可防止因為噴砂加工而使加工及於半導體基板 2。如孔3f達到半導體基板2的話,在形成上述電極膜7a 時,電極膜7A會及於半導體基板2上所形成之孔的内周 面。如電極膜7A達到及於半導體基板2之孔之内周面的 話,最終源自於電極膜7A之連接電極8會達到半導體基板 之側面,半導體感測裝置1之特性恐有變動之虞。 亦即,如連接電極8達到半導體基板2之側面的話,該半 導體基板2恐因連接電極8施加電場而有特性發生變化之 虞。相對於此,上述實施方式中,上述接著劑層5發揮作 為擋板之功能,以不及於半導體基板2之方式形成孔3f, 因此’連接電極8不會達到半導體基板2之側面。 接著,參照圖5來說明藉由上述實施方式得到之半導體 感測裝置1可利用端子電極7來表面安裝於安裝基板上之 旨。 如圖5所示,在安裝時,以端子電極7、7抵接於安裝基 板51上之電極平面52、53上之方式,半導體感測裝置1會 上下顛倒地載置於安裝基板5 1上。並且,例如使用焊錫 54、55,使上述端子電極7、7接合於電極平面52、53上。 在此情況中,如上所述,突起3b與外殼板3以相同材料一 110654.doc -19· 1304646 體構成,因此,即使受到焊錫加熱時之熱時,突起3b不會 由外殼板3脫落。因此,即使未用底膠,亦可如圖$所示i 將半導體感測裝置1堅固地接合於安裝基板51上。依此, 可省略底膠之使用。 從而,可提供安裝空間小且在安裝基板51上可得到充分 之接合強度的半導體感測裝置1。此外,在上述半導體感 測裝置1中不需要底膠’因此,亦不會發生中介底膠而來 自安裝基板5 1側之應力傳達。此外,即使安裝基板5丨側發 生變形等,由安裝基板51側之應力僅會經由突起%傳達至 半導體感測裝置1側,因此,上述應力難以傳達至半導體 基板2之半導體感測器。從而,可提供即使安裝基板$工側 變形時亦難以發生錯誤動作之半導體感測裝置1。 接著,說明在上述半導體基板2上所設之加速度感測器 之概略構造。 如圖6以平面圖所示,半導體基板2内有框形之樑部被以 浮動狀態配置。設有該樑部21之部分及設有後述之錘部分 之部分的放大平面圖如圖7所示。樑部21由平面來看時, 具有角環形之形狀。以由樑部21之上述χ軸方向兩端,以 分別沿著X軸方向向外側沿伸之方式連有支持部22a、 22b。與支持部22a、22b之樑部以相連之側為相反側之端 部則與半導體基板2之主體部分相連。亦即,藉由支持部 22a、22b,樑部21處在浮動狀態。 此外’樑部21之γ轴方向兩側上配置有錘部23&、23b。 錘部23a、23b乃藉由相對於樑部21由Y軸方向兩側與γ軸 110654.doc •20- 1304646 方向外側相連之連結部24a、24b而與樑部21連結。從而, 錘部23a、23b與樑部21同樣地相對於半導體基板2之主體 部被配置成浮動狀態。藉由樑部21翹曲變形,錘部23a、 23b可在X軸方向、Ύ轴方向及z轴方向之3軸方向位移。 本實施方式中,上述半導體基板2乃對SOI (SiliCon-〇n-Insulator,絕緣層上覆石夕)基板以使用微細加工技術進行加 工之方式形成。此外’ SOI基板為Si層、SiO層、及Si層依 此順序層疊之多層基板,然而,本發明所用之半導體基板 t 並不限於上述SOI基板。 此外,上述樑部21中,如圖6以概圖所示,例如為了檢 測出X轴方向之加速度,配置有4個壓電電阻部尺幻至汉以。 該4個壓電電阻部尺^至尺以構成了用來檢測χ軸方向加速度 之X軸方向加速度檢測部。並且,藉由半導體基板2上所形 成之佈線圖案,壓電電阻部rx1至rX4構成了圖8所示之電 橋電路。藉由該電橋電路之輸出變化,檢測出X方向之加 ,速度。亦即,如圖8所示,該電橋電路中,壓電電阻部 Rxi、Rx2電性連接,形成電壓檢測部Ρχι。同樣地,壓電 電阻部Rxs、Rh電性連接,形成電壓檢測部ρχ2。 此外,壓電電阻部RX1、RX3電性連接,此連接部成為與 外一之電壓電源連接之電壓輸入部vs。再者,藉由外部佈 線圖案’壓電電阻部RX1、Rd電性連接,該連接部被連接 於接地電位。 此外’為了檢測出γ軸方向及Z轴方向之加速度,同樣 地’分別配置有4個壓電電阻部,且與如圖8所示之電橋電 110654.doc •21 - 1304646 佈 路相同之電橋電路;5以藉^在半導體基板2上所形成之 線圖案來連接4個壓電電阻部之方式構成。 在半導體基板2中,如發生乂軸方向之加速度的話,加速 度所致之X軸方向之力會作用於可動部“之錘部Ua、 23b。藉由錘部23a、23b之於乂軸方向之作用力,鐘部 23a、23b由圖9之虛線所示之基準狀態,如圖9之實線所示 般地向X軸方向位移。藉由錘部23a、2补之乂軸方向之位 移,介隔連結部而樑部21翹曲變形,藉此樑部21產生應 力。藉由樑部21產生之應力,上述χ轴方向加速度檢測部 中之壓電電阻部之電阻值發生變化。因此,發生χ軸方向 之加速度時,X軸方向加速度檢測部所包含之如圖8所示之 電橋電路之輸出會發生變化,從而檢測出χ軸方向之加速 度。在此情況中,當γ轴方向及2軸方向上沒有加速度作 用時’ Υ軸方向加速度檢測部及Ζ軸方向加速度檢測部所 包含之各電橋電路之輸出不會有變化。藉此,檢測出χ轴 方向之加速度。 Υ軸方向上發生加速度時,或Ζ轴方向上發生加速度 時’同樣地,亦會檢測出γ軸方向及Ζ軸方向之加速度。 此外’在本實施方式中,上述般之加速度感測器在半導 體基板上作為具有可動部之半導體感測器而被構成,惟本 發明並不限於使用上述般之加速度感測器之半導體感測 器’可使用形成有具可動部之半導體感測器的半導體基 板。作為半導體感測器,除了加速度感測器,舉例來說有 角速度感測器、角加速度感測器、及壓電迴轉儀感測器等 110654.doc -22· 1304646 各種使用半導體之具有可動部之感測器。 此外,在上述實施方式中,將上述半導體基板2使用作 為元件基板’惟在本發明之電子零件之製造方法中,元件 基板並不限於半導體基板’亦可為由半導體以外之材料所 形成之基板,此外,關於功能部,亦不限於上述般之感測 器’廣泛地包含可作為各種電子零件而發揮功能的功能 部。 再者,在上述實施方式中,第二外殼板4被層疊於半導 體基板2之下面,惟在本發明中,並不―定需要使用第二 外殼板4 H可不㈣第二外殼板4,在安裝後使上面 成為開放狀態。 然而’藉由層疊第二外殼板4,可確實地氣密封裝元件 基板上所I成之功此部。此外,亦可提高電子零件之機械 強度。 此外帛一外设板4側亦可形成上述複數個突起及端子 電極在此^ ;兄中’可得能夠由外殼側來搭載在安裝基板 上之電子零件。亦即,亦可㈣電子零件之上下方向性。 此外’亦可不在外殼板3、4上設凹部4a等。在此情況 中藉由支曰加佈塗成框形之接著劑之厚度來形成空隙即 '5rJ~ 〇 【圖式簡單說明】 、圖1(a)至⑷係說明第一實施方式之半導體感測裝置之製 造步驟之各部分剖面圖。 圖2係本發明之雷工帝丄 電子零件之實施方式的半導體感測裝置 110654.doc -23- 1304646 之外觀之立體圖。 圖3係圖1所示之實施方式之半導體裝置之分解立體圖。 圖4係圖1所示之實施方式之半導體裝置使用之半導體基 板之平面圖。 圖5係圖1所示之實施方式之半導體感測裝置之縱向剖面 圖。 圖6係說明將圖1所示之實施方式之半導體感測裝置安裝 於安裝基板時之狀態之部分正面剖面圖。 圖7係模式性地顯示圖4所示之半導體基板之主要部分之 部分剖面平面圖。 圖8係圖4所示之半導體基板上所包含之X轴方向加速度 檢測電路之圖。 圖9係說明圖4所示之半導體基板上所設之加速度感測器 之位移狀態之模式性立體圖。 圖10係以往之半導體裝置之一例之正面剖面圖。 ^ 【主要元件符號說明】 2、 2A 3、 3A 3b 3c、3d 3e 4、 4A 4a 半導體感測裝置 半導體基板 外殼板 突起 側面 凹部 第二外殼板 凹部 110654.doc -24 - 1304646 7 端子電極 7A 電極膜 8 連接電極 9 外部連接用電極 21 樑部 110654.doc -25
Claims (1)
1304646 十、申請專利範圍: h 一種電子零件之製造方法,其特徵為包含: 準備已δ又有作為電子零件而使之發揮功能的功能部、 及為了使該功能部與外部電性連接而形成於一面上之外 部連接用電極的元件基板之步驟; 在上述7〇件基板上利用相對耐喷砂性高之接著劑,貼 合相對耐喷砂性低之外殼板之步驟; a在上述外殼板上利用f砂加I,對下面存在有上述外 部連接用電極-部分之部分,以使上述接著劑露出之方 式形成孔之步驟; 對於在上述孔露出而藉由上述喷砂加工無法去除之接 著劑部分’藉由_加以去除而使上述外部連接用電極 露出之步驟; 由上述外殼板之外表面至上述孔内,且以能與藉由上 述接著劑去除^與露出之外部連翻電極電性連接之方 式,形成電極臈之步驟,·及 藉由機械加工,將箭、土 冑“ ®可達·㈣之突起形成 ;,卜Λ又板之外表面上之步驟。 2. 如請求項1之電子零件之製造方法,其中在形成上述電 極膜之前,更包含佶μ、+、从* 风上4電 膜之部八心* 述外威板之至少形成有上述電極 胰之。卩分粗糖之步驟。 3. 如睛求項1或2之雷早费/生^也丨止 由乾式餘刻進行。 方法’其中上述韻刻藉 4. 如請求項1之電子零件之製造方法,其中作為上述接著 110654.doc 1304646 劑,使用聚醯亞胺系接著劑。 之内周面之 5·如請求項!之電子零件之製造方法,其中更包含以分割 上述孔之方式,切割上述元件基板及上述外殼板之積層 體,並在上述突起之側面上形成以上述孔 部分形成之凹部之步驟。 6·如請求〜之電子零件之製造方法,其中更包含在上述 :件基板之接著有上述外殼板之側之相反側之面上層疊
第二外殼板之步驟。 •如請求項6之電子零件之製造方法,其中上述第二外殼 板藉由接著劑貼合於上述元件基板上。 8· —種電子零件,其特徵為: 其具有·· 70件基板,其係設有作為電子零件元件發揮功能之功 能部; 接著劑層’其係設於上述元件基板之單面;及 、外Λ又板’其係、由比上述接著劑層耐喷砂性低之材料形 成,並藉由上述接著劑層貼合於上述外殼板; 上述元件基板之層#有上述外殼板之面上形成有盘外 部電性連接之外部連接用電極; j述外殼板上具有使上述外部連接用_之至少一部 分露出而底部未配置上述接著劑層之孔; 在與上述外殼板之層疊有上述元件基板之側相反側之 面上’形成有外表面被賦予上述電極膜之突起,突起侧 面之一部分由上述孔之内周面形成,並形成由上述突起 110654.doc 1304646 之前端面經由突起之側面至在上述孔内露出之外部連接 用電極之電極膜。
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JP5378106B2 (ja) * | 2009-08-20 | 2013-12-25 | 日本シイエムケイ株式会社 | プリント配線板の製造方法 |
JPWO2012137714A1 (ja) * | 2011-04-04 | 2014-07-28 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
JP6217870B2 (ja) * | 2015-09-30 | 2017-10-25 | 住友ベークライト株式会社 | 構造体、配線基板および配線基板の製造方法 |
WO2017061374A1 (ja) * | 2015-10-06 | 2017-04-13 | 住友電工プリントサーキット株式会社 | プリント配線板及び電子部品 |
CN108290730A (zh) | 2015-11-30 | 2018-07-17 | W.L.戈尔及同仁股份有限公司 | 用于裸芯片的保护环境阻隔件 |
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JPH11201788A (ja) * | 1998-01-19 | 1999-07-30 | Mitsubishi Electric Corp | 半導体カルマン渦流量センサ及びその製造方法 |
JP3994262B2 (ja) | 1999-10-04 | 2007-10-17 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2001124794A (ja) * | 1999-10-26 | 2001-05-11 | Matsushita Electric Works Ltd | マイクロ加工センサの実装構造及びその実装方法 |
JP4260339B2 (ja) * | 2000-04-27 | 2009-04-30 | 三菱電機株式会社 | 加速度センサの製造方法 |
US6476415B1 (en) * | 2000-07-20 | 2002-11-05 | Three-Five Systems, Inc. | Wafer scale processing |
JP4330367B2 (ja) * | 2003-04-03 | 2009-09-16 | 新光電気工業株式会社 | インターポーザー及びその製造方法ならびに電子装置 |
JP2004340730A (ja) * | 2003-05-15 | 2004-12-02 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6953990B2 (en) * | 2003-09-19 | 2005-10-11 | Agilent Technologies, Inc. | Wafer-level packaging of optoelectronic devices |
US6926592B2 (en) * | 2003-11-25 | 2005-08-09 | Motorola, Inc. | Surface treatment of mechanically abraded glass |
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2006
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- 2006-05-16 WO PCT/JP2006/309724 patent/WO2007017980A1/ja active Application Filing
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TW200742009A (en) | 2007-11-01 |
DE112006001844T5 (de) | 2008-06-12 |
DE112006001844B4 (de) | 2012-07-05 |
JPWO2007017980A1 (ja) | 2009-02-19 |
US20080113164A1 (en) | 2008-05-15 |
JP4613958B2 (ja) | 2011-01-19 |
CN101218669A (zh) | 2008-07-09 |
WO2007017980A1 (ja) | 2007-02-15 |
CN100565848C (zh) | 2009-12-02 |
US7507346B2 (en) | 2009-03-24 |
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