TWI286750B - Vertical elevated pore phase change memory - Google Patents

Vertical elevated pore phase change memory Download PDF

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TWI286750B
TWI286750B TW092112708A TW92112708A TWI286750B TW I286750 B TWI286750 B TW I286750B TW 092112708 A TW092112708 A TW 092112708A TW 92112708 A TW92112708 A TW 92112708A TW I286750 B TWI286750 B TW I286750B
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phase change
layer
lower electrode
change memory
hole
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TW092112708A
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TW200410245A (en
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Tyler Lowrey
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Ovonyx Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/008—Write by generating heat in the surroundings of the memory material, e.g. thermowrite
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/52—Structure characterized by the electrode material, shape, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/13—Hollow or container type article [e.g., tube, vase, etc.]

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Inert Electrodes (AREA)
  • Battery Electrode And Active Subsutance (AREA)

Description

1286750 玫、發明說明： 【發明戶斤屬之技術領域3 發明領域 本發明大致上係關於電子裝置以及特別是關於使用相 5 變材料之電子裝置。 C先前技術;3 發明背景 相變材料可呈現至少二不同的狀態。此等狀態可稱為 非晶形及結晶狀態。在此等狀態之間的轉變可選擇性地引 ίο 發。由於非晶形狀態一般呈現出比結晶狀態高之電阻率， 因此可區分此等狀態。非晶形狀態涉及較無次序的原子結 構。一般而言，可利用任何相變材料。然而，在一些具體 實施例中，薄膜硫屬化物（chalcogenide)合金材料可能特別 適用。 15 相變可以可逆地引發。因此，回應温度改變，記憶體 可由非晶形狀態改變成結晶狀態以及之後可回到非晶形狀 態，反之亦然。實際上，每個記憶體晶胞可視為一可程式 化的電阻器，其可逆地在較高及較低電阻狀態之間改變。 相變可藉由電阻性加熱引發。 20 現有的相變記憶體可呈現各種不同的缺點。因此，仍 需要較佳的方式來形成熱相變記憶體。 C發明内容3 發明概要 本發明提供一種相變記憶體（1 〇)之垂直升高孔結構，該 1286750 結構可包括一孔洞（46)，該孔洞具有位在該孔洞下方，與孔 洞（46)中的相變材料（18)接觸的下部電極（24, 26)。下部電極 可由較高電阻率之下部電極（24)及位在較高電阻率之下部 電極（24)下方之較向電阻率電極（26)組成。結果，在本發明 5之一些具體實施例中，可達到相變材料（18)之較均句加熱且 在一些情況下可產生較佳的接觸。 1式之簡單說明 第1圖為根據本發明之一具體實施例的相變記憶體之 一部分的放大截面圖；以及 10 第2圖為使用根據本發明之一具體實施例的相變記憶 體之系統的概要說明圖。 t實施方式3 參考第1圖，相變記憶體10可包括多數相變記憶體晶 胞12 ’包括位在鄰近位元線14上的鄰近晶胞及i2b。 15每一位元線14係定位在一隔離材料16上。隔離材料16可 延伸入位在相變材料18之頂部的孔洞46中，根據本發明 之一具體實施例，該相變材料可為硫屬化物（chalc〇genide) 材料。 雖然本發明之範圍不限於此，但相變記憶體材料的例 2〇子包括’但不限制於碲-鍺-銻（TexGeySbz)材料或GeSbTe 合金類之硫屬化物（chalc〇genide)成分組成物。或者，可 使用其他的相變材料，該材料的電氣性質（例如電阻及電 谷等）可藉由施與能量而改變，該能量例如光、熱或電流。 在一具體貫施例中，孔洞46可藉由側壁分隔器22來 1286750 定義。孔洞46及側壁分隔器22可藉由形成於介電或絕緣 材料20中的開口來定義。材料2〇可為氧化物、氮化物或 任何其他的絕緣材料。 L洞4 6下方為一對下部電極’該電極包括一相對較 5高電阻率的下部電極24以及一相對較低電阻率的下部電極 26。較高電阻率之電極24可負責加熱相變材料46之鄰近 區域，以及因而可具有較大的垂直範圍。較低電阻率電極 材料26係作用於有效地分布電流橫越較高電阻率電極材料 24的整個寬度。 在具體實施例中，電流係由較低電阻率電極材料％ 接收且通過基座直線形導體3〇。在本發明之一具體實施例 中導體3〇可為杯形以及可充填有絕緣體28,該絕緣體亦 圍繞該基座直線形導體3〇。 氮化物層32可被基座直線形導體3()穿透。氮化物層 15 32可定位在—絕緣層35上，該絕緣層⑽彡成在包括p+區 域38的半導體基板上。 月豆貫施例中，p+區域38可鄰近矽化: 接觸區域34。在p+區域38下方為_ n_财層4G。n+區土 36可定位在鄰近位元線14之間。位在η-型石夕層40下方 &型外延（ΕΡΙ)石夕層42及广型石夕基板44。 於本發明之-具體實施例巾，相龍高電阻率電極2 t電阻率範圍可為1至500毫歐姆-公分，較佳為30至n 人姆A刀。較低電阻率的下部電極％的電阻率範圍為 0.01至1.0毫歐姆-公分，較佳為〇 〇5_〇 15毫歐姆_公分^ 20 1286750 可使用於作為電極2 4及2 6之電阻性材料的例子包括氮化 石夕及氮化I旦。 以處理器為主的系統，如第2圖所示，可包括一處理 器50,該處理器的二個例子例如通用的處理器或數位訊號 5處理器。處理器5〇可例如藉由匯流排52轉合至記憶體1〇。 在一些具體實施例中，可提供無線界面54。舉二個例子來 說，無線界面54可包括一無線電收發機或一天線。 雖然本發明已描述相關的數目有限之具體實施例，熟 習該項技術者將可由該等實施例瞭解到許多的改良及變 10化。本發明之意圖為後附的申請專利範圍涵蓋所有落於本 發明之精神及範疇内的此等改良及變化。 t圖式簡明]| 苐1圖為根據本發明之一具體實施例的相變記惊體之 一部分的放大截面圖；以及 15 第2圖為使用根據本發明之一具體實施例的相變記憶 體之系統的概要說明圖。 【圖式之主要元件代表符號表】 11 相變記憶體 20 介電或絕緣材彳彳 12 相變記憶體晶胞 22 分隔器 12a 晶胞 24 下部電極 12b 晶胞 26 下部電極 15 位元線 28 絕緣體 16 隔離材料 30 導體 18 相變材料 32 氮化物層 矽化物接觸區域 絕緣體 η區域 ρ+區域 η-型;&夕層 ρ-型外延(ΕΡΙ)石夕層 P#型矽基板 孔洞 處理器 匯流排 無線界面 9

Claims (1)

  1. Lj28675|〇 1L :」第92112708號專利申請案申請專利範圍修正本96.05.15 拾、申請專利範圍： 胙艾^ 1. 一種相變記憶體，包含： 一絕緣材料； 一相變材料，該相變材料係位在該絕緣材料上，以及 5 —下部電極，其係耦合至該相變材料，該下部電極包 括一較高電阻率層，該較高電阻率層位在一較低電阻率層 上。 2. 如申請專利範圍第1項之相變記憶體，其中該較高電阻率 層係與該相變材料接觸。 10 3. 如申請專利範圍第2項之相變記憶體，其中該較低電阻率 層比該較高電阻率層薄。 4. 如申請專利範圍第3項之相變記憶體，包括一杯形導體， 該導體與該較低電阻率層接觸。 5. 如申請專利範圍第4項之相變記憶體，包括一絕緣體，該 15 絕緣體位在該相變材料層及該下部電極之間，以及在該絕 緣體中形成一孔洞。 6. —種相變記憶體的製造方法，包含下述步驟： 形成一下部電極，該下部電極具有第一層及第二 層，該第二層的電阻率比該第一層的電阻率高；以及 20 形成一相變材料，該相變材料係位在該第二層上。 7. 如申請專利範圍第6項之方法，包括將該較少的電阻性層 與一導體接觸。 8. 如申請專利範圍第7項之方法，包括形成一絕緣體在該下 部電極上，以及形成一孔洞在該絕緣體中。 10 1286750 9. 如申請專利範圍第8項之方法，包括於該孔洞中形成該相 變材料，以與該下部電極接觸。 10. 如申請專利範圍第9項之方法，包括形成一下部電極，該 下部電極比該孔洞寬。 5 11. 一種相變記憶體，包含： 一絕緣層，其係界定一孔洞； 一相變材料，其係位於該孔洞中；
    一下部電極，其係位在該孔洞下方，且與該相變材 料接觸，該下部電極包括第一層及第二層，該第一層係與 10 該相變材料接觸以及具有比該第二層高的電阻率。 12. 如申請專利範圍第11項之相變記憶體，其中該較低電阻 率層比該較高電阻率層薄。 13. 如申請專利範圍第12項之相變記憶體，包括一杯形導 體，其係與該較低電阻率層接觸。 15 14. 如申請專利範圍第11項之相變記憶體，其中該下部電極
    係比該孔洞寬。 11
TW092112708A 2002-12-13 2003-05-09 Vertical elevated pore phase change memory TWI286750B (en)

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JP (1) JP4446891B2 (zh)
KR (1) KR100669312B1 (zh)
CN (1) CN1714461B (zh)
AU (1) AU2003225226A1 (zh)
MY (1) MY135245A (zh)
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WO (1) WO2004055915A2 (zh)

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US20060054878A1 (en) 2006-03-16
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US7364937B2 (en) 2008-04-29
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US7049623B2 (en) 2006-05-23

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