TWI284396B - Semiconductor component - Google Patents

Semiconductor component Download PDF

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Publication number
TWI284396B
TWI284396B TW091123732A TW91123732A TWI284396B TW I284396 B TWI284396 B TW I284396B TW 091123732 A TW091123732 A TW 091123732A TW 91123732 A TW91123732 A TW 91123732A TW I284396 B TWI284396 B TW I284396B
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Taiwan
Prior art keywords
channel
semiconductor
pattern
rewiring pattern
electrode
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TW091123732A
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English (en)
Inventor
Tsuyoshi Kobayashi
Shigetsugu Muramatsu
Takuya Kazama
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Shinko Electric Ind Co
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Publication of TWI284396B publication Critical patent/TWI284396B/zh

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

1284396 玖、發明說明 (發明說明應敘明：發明所厠之技術領域、先前技術、內容、實施方式及圖式簡單說明） 【發明所屬之技術領域3 發明領域 本發明係有關於一種半導體組件，其特徵為再佈線圖 案設置在一半導體晶片上，且其中以細微間隔配置電極端 5 子。 L· lltr ]| 發明背景 晶圓級封裝件係為在半導體晶圓階段處理晶圓表面所 獲得之半導體組件，進行晶圓級的預定處理之後分成各別 10 的塊件，這些半導體組件隨後安裝在主板上或以晶片互疊 式構造加以堆疊。 當製造此等半導體組件時，半導體晶圓上所形成的各 別晶片係設有從其電極端子至形成外部電極處的預定位置 或由打線接合來連接導線的其他位置用以安裝在主板上等 15 之導線（稱為“再佈線(rerouting)”）。 第6圖係為一半導體晶圓10的表面設有一電絕緣層12且 絕緣層12表面形成有經由一通道15電性連接至一電極端子 14的一再佈線圖案16之狀態圖。再佈線圖案譬如在一端點 與電極端子14電性連接、並在另一端點形成有一岸面部藉 20 以接合一外部連接端子或一打線接合用的接合部。再佈線 圖案16可在絕緣層12表面上形成任何圖案，使得再佈線圖 案16從電極端子14適當地引出以配置岸面部或接合部。 第5圖顯示再佈線圖案的習知形態之一範例，其顯示電 極端子14與再佈線圖案16之間的連接部的平面配置。電極 0續次頁（發明說明頁不敷使用時，請註記並使用續頁） 1284396 _ 、發明說明 發明說明續® 端子14以正方形呈現固定間隔形成於半導體晶圓1〇的表面 上，通道孔18形成於電極端子14的平面中，通道孔18内側 的導體層則形成為通道。通道墊20在通道孔18周緣形成有 特疋寬度’上述作用係用於確保再佈線圖案1 6與通道之間 5 的電性連接。 但是，近來的半導體晶片正在縮小尺寸及增加端子數 ’造成電極端子14的配置間隔變窄且在相鄰通道墊2〇之間 不再能獲得足夠空間S之問題。第5圖所示的範例中，將通 道墊20的直徑尺寸r設為比電極端子14的寬度尺寸更大，但 10當電極端子14的配置間隔變窄時，可能藉由使通道孔18變 得更小及降低通道墊20的直徑尺寸R來確保通道墊2〇的配置 間隔。但是’形成較小的通道孔丨8將導致處理精確度的問 題及較高接觸阻抗的問題。並且，如果形成較小的通道墊 20 ’將具有與再佈線圖案16的電性連接可靠度降低之問題 15 〇 並且’當將接合部設置於再佈線圖案上及藉由打線接 σ與主板或其他半導體晶片連接時，需要將接合部設置於 半導體晶片的電極端子鄰近處，此情形將產生當半導體晶 片之電極端子具有狹窄的配置間隔時難以在電極端子鄰近 20處確保足夠接合部之問題。 【發明内容】 發明概要 本發明之目的係提供一種半導體組件，其即使當電極 端子以細微間隔配置時亦能夠容易且可靠地形成再佈線圖 次頁（發明說明頁不敷使用時，請註記並使用續頁） 1284396 玖、發明說明 讎明續賣 案而不縮小通道塾直徑或使再佈線寬度變窄，並能夠使接 合部固定在電極端子鄰近處，且能夠容易地處理藉由打線 接合的連接。 為了達成上述目的，本發明具有下列構造·· 5 Φ即提供-種半導體組件，此半導體組件係具有平行 配置於一半導體晶片的一電極形成表面上構成長方平面形 之電極端子並形成有經由覆蓋住電極形成表面之一電絕緣 層的表面上的通道與該等電極端子電性連接之再佈線 (rerouting)圖案’其特徵為··形成於電絕緣層的表面上之通 H)道塾的平面性配置係製成交錯式偏移至電極端子的縱方向 之-側與另一側之一種配置，並且再佈線圖案係設置為連 接至通道墊。 並且，組件的特徵為：藉由形成較寬且以打線接合所 連接的再佈線圖案產生之接合部係設置於該等再佈線圖案 15 的通道塾鄰近處之部份。 並且、°且件的特徵為：藉由從通道塾引出至相鄰電極 端子的區域上來設置該等接合部。 並且，提供一種半導體組件，其形成於覆蓋住一半導 體ΒΘ片的電極端子形成表面之一電絕緣層的表面上，其 20中再佈線圖案經由通道與電極端子電性連接，其特徵為： 藉由形成較寬且以打線接合連接的再佈線圖案所產生之接 合部係設置於該等再佈線圖案的通道墊鄰近處之部份。 並且"且件的特彳玫為：該等接合部係設置於該等通道 塾鄰近處部份不互相干涉之位置。 _頁（發明說明頁不敷使用時，請註記並_頁） I284396 mmmm 發明說明續頁 ；' ' 'v"" ·： . , . 圖式簡單說明 第1圖顯示形成於再佈線圖案上之電極端子及通道墊的 平面性配置； 第2圖顯示再佈線圖案及接合部之平面性配置； 第3 A及3 B圖顯示再佈線圖案及接合部的平面性配置之 其他範例； 第4圖顯示安裝一形成有再佈線圖案的半導體晶片之一 範例； 第5圖顯示習知技藝之電極端子及再佈線圖案的平面性 10 配置； 第6圖為一再佈線圖案的構造之剖視圖。 【資施方式3 較佳實施例之詳細說明 下文參照圖式詳細描述本發明的較佳實施例。 第1圖為根據本發明之一半導體組件中的再佈線圖案的 形態之範例’圖式中14代表形成於一晶圓上的電極端子， 16顯示電性連接至電極端子14之再佈線圖案，本實施例的. 半導體組件之特徵特性在於：配置為電性連接至構成長方 平面形且水平配置的電極端子14之通道墊20係偏移至電極 20 端子Μ縱方向中的一側及另一側。 若半導體晶片變小且電極端子14的配置間隔變窄，則 電極端子的接合面積將變小，所以電極端子14形成長卫窄 的長方形以確保接合面積。在本實施例的半導體組件中， 設有構成此長方形的電極端子14之半導體晶片的特徵係為 0續次頁（發明說明頁不敷使用時，請註記並使用續頁） 1284396 __ 玖、發明說明 發明說明續頁 ••通道墊20配置為鋸齒形式以在相鄰通道墊2〇之間保留空 間’並且即使電極端子14的配置間隔變窄仍能夠再佈線而 不縮小通道墊20直徑或縮小再佈線圖案16的寬度尺寸。 請注意用於形成電性連接至電極端子14的再佈線圖案 5 16之方法係類似於習知用於形成第6圖所示的再佈線圖案16 之方法，亦即，一電絕緣層12形成於一半導體晶圓1〇表面 上’然後通道孔18形成為與電極端子14的配置位置相匹配 ，且通道孔18的内壁及絕緣層12表面係電鍍形成一導體層 並形成再佈線圖案16。本實施例中，因為通道墊2〇配置為 10 鋸齒狀構造，當通道孔18形成於絕緣層12中時，通道孔18 父錯式开> 成於偏移至電極端子14的縱方向的一侧與另一侧 之位置。 形成通道孔18之後，通道孔18的内壁及絕緣層12表面 係滅鍍形成有一電鍍籽層。接下來，電鍍籽層的表面覆蓋 15有一感光性阻劑，然後感光性阻劑暴光且顯影以形成一阻 劑圖案以供用於形成再佈線圖案16及通道墊2〇之部份暴光 所使用。接下來利用電鍍籽層作為電鍍電源層將銅電解性 電鑛，以在電鍍籽層的暴光部份上形成導體層，然後溶解 並移除阻劑圖案，且蝕除電鍍籽層的暴光部份以形成藉由 20 通道電性連接至電極端子14之再佈線圖案16。 請注意對於半導體晶圓的整個電極形成表面進行用於 形成再佈線圖案16之程序，實際的半導體晶圓係形成有很 多個配置為在垂直與水平方向連接之各別半導體晶片，所 以藉由對應於這些半導體晶片配置的一預定圖案來形成再 0續次頁（發明說明頁不敷使用時，請註記並使用續頁） 10 1284396 _ 玖、發明說明 發明說明續頁 佈線圖案16。 並且，在形成再佈線圖案16之後，半導體晶圓可分割 成各別塊件以獲得設有再佈線圖案16的各別半導體晶片。 一般而言，通道墊20的直徑變成比再佈線圖案16寬度 5 更大，因此如第1圖所示，若將通道整20的排列位置配置在 平面性區中且其中電極端子14形成為交錯式偏移至電極端 子14的一側與另一側，可以避免令相鄰電極端子14上所形 成的通道墊20彼此重疊之配置，並可在相鄰通道墊2〇之間 保留額外的空間。因此，即使通道墊2〇及再佈線圖案“配 1〇置為彼此相鄰，仍可以在通道墊20與再佈線圖案16之間保 留足夠空間。因此，即使當電極端子14的配置間隔變窄時 ，亦變成為可容易地形成再佈線圖案16而不縮小通道墊2〇 的直徑尺寸。 15 一種習知用於形成再佈線圖案之方法中，若電極端子 14的寬度尺寸為8G微求且電極端子14的配置間隔為微米（ 亦即電極端子14的間距為90微米），若將通道墊的直徑製成 8〇微米且再佈線圖案的寬度製成5〇微米，通道墊的間隔將 變成ίο微米，但根據本發明的方法可能保留25微米的間隔 作為通道墊與相鄰再佈線圖案之間隔（第i圖中的Μ)。 再佈線圖案16從電極 藉由將通道墊2〇偏移 將可以形成用於打 請注意在第1圖所示的實施例中， 端子14直線狀引出，但如第2圖所示， 式配置在電極端子14的平面性區域中 線接合在再佈線圖案16上之接合部。 _::===置的特徵在於:為了使 20 1284396 發明說明$賣頁 玖、發明說明 通道塾20a配置於電極端子的一側（前端侧），藉由從通道塾 20a引出以形成再佈線圖案16並藉由在從通道墊20a的相鄰 電極端子14上方空間部份從通道墊20a直接延伸以形成接合 部22a ;為了使通道墊20b配置於電極端子14的另一側（後端 5 側），在通道墊20b所引出的圖案上從通道墊20b直接形成寬 廣的接合部22b。 當再佈線圖案16由打線接合與另一半導體晶片或一主 板（封裝件）電性連接時，形成於再佈線圖案16上的接合部 22a及22b係變成銲線接合的部份，第2圖顯示另一半導體晶 10 片或主板（封裝件）的電極端子30藉由銲線32與接合部22a及 22b連接之一範例。 若如同此實施例般地在電極端子14的平面性區域中將 通道墊配置為偏移至一側與另一側，將可以有效使用絕緣 層12的表面空間來形成接合部22a及22b。 15 請注意根據本發明，用於形成以打線接合連接再佈線 圖案的接合部之方法亦適用於過去以相同方式將通道墊序 列式配置之情形。第3 A及3B圖顯示習知的通道墊配置之情 形中將接合部22形成於再佈線圖案16上之情形，第3A圖中 ，對於一個通道墊20a而言，寬廣的接合部22a係在後端側 20 從通道墊20a直接延伸且狹窄的再佈線圖案16從接合部22a 引出；但對於另一通道墊20b而言，接合部22b在不與接合 部22a干涉的一位置處延伸朝向面對的再佈線圖案16，且一 狹窄的再佈線圖案16從接合部22b引出。 並且，第3B圖所示的實施例中，對於通道墊20a而言， 0續次頁（發明說明頁不敷使用時，請註記並使用續頁） 12 1284396 發明說明$賣Μ 玖、發明說明 接合部22a形成為從再佈線圖案的側緣延伸朝向位於通道墊 20a的一鄰近位置處之面對的通道墊20b ;但對於通道墊20b 而言，接合部22b形成為從通道墊20引出的再佈線圖案延伸 朝向位於不與接合部22b發生干涉的一位置處之面對的再佈 5 線圖案。‘ 第3 A及3B圖所示的實施例將靠近通道墊20a及20b的部 份構成寬廣狀以形成銲墊22a及22b。特定言之，藉由選擇 使接合部22a及22b在通道墊20a及20b附近不產生干涉之位 置，可以保留所需要的接合區並將再佈線圖案可靠地打線 10 接合。 第4圖顯示安裝一形成有具備第2圖所示的接合部22a及 22b的再佈線圖案16之半導體組件40的一項範例，此範例中 ，另一半導體晶片42安裝在半導體組件40上，且半導體組 件40安裝在一主板44上。半導體晶片42覆晶式連接經過凸 15 塊42a而電性連接至半導體組件40之再佈線圖案16的岸面部 16b，半導體組件40則打線接合式電性連接至主板44。 請注意，若不用主板44，亦可能將半導體組件40安裝 在另一半導體晶片上。並且，若不用主板44,可能將半導 體組件40安裝在另一半導體封裝件上。 20 藉*此方式將接合部22a及22b設置於再佈線圖案16上 ，可能使半導體組件藉由打線接合與另一半導體晶片或一 主板或半導體封裝件電性連接，且可能提供各類型的電子 元件。 請注意在通道墊附近形成的接合部可依據通道墊及再 0續次頁（發明說明頁不敷使用時，請註記並使用續頁） 13 1284396 — 玖、發明說明 mmrnmw 佈線圖案的配置而形成一適當的圖案，再佈線圖案及接合 部的配置並不侷限於上述實施例。 產業適用性 根據本發明之半導體組件，如上述，將可能使連接至 5 電極端子的通道墊產生一種鋸齒狀平面性配置，並有效地 確保用於配置通道墊及再佈線圖案的空間，並變成為即使 當電極端子以細微間隔配置時仍可能容易地形成再佈線圖 案。並且，藉由在再佈線圖案上形成寬廣部份以提供接合 部，所呈現的顯著效果係為：此等接合部變成可以作為打 10 線接合式電性連接再佈線圖案之部份。 I：圖式簡皁說明2 第1圖顯示形成於再佈線圖案上之電極端子及通道墊的 平面性配置； 第2圖顯示再佈線圖案及接合部之平面性配置； 15 第3A及3B圖顯示再佈線圖案及接合部的平面性配置之 其他範例； 第4圖顯示安裝一形成有再佈線圖案的半導體晶片之一 範例； 第5圖顯示習知技藝之電極端子及再佈線圖案的平面性 20 配置；. 第6圖為一再佈線圖案的構造之剖視圖。 0續次頁（發明說明頁不敷使用時，請註記並使用續頁) 14 1284396 發明說明#頁 玖、發明說明 【圖式之主要元件代表符號表】 ίο…半導體晶圓 12…電絕緣層 14,30···電極端子 16…再佈線圖案 16b···岸面部 18…通道孔 20…通道墊 20a，20b···通道墊 22a，22b···接合部 3 2…鲜線 40…半導體組件 42…半導體晶片 42a…凸塊 44···主板
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Claims (1)

  1. ⑻正本 ίο、申日靑專利範廛 第〇川23732號專利再審查案申請專利範圍修正 修正日期·· 93年3月 1· Γ種半㈣組件，其具有平行配置於—半導體晶片的 5 10 15 20 電料成表面上構成長方平面形之電極端子，並妒 成有經由覆蓋住該電極形成表面之一電絕緣層的表面 上的通道與該等電極端子電性連接之再佈線圖案，該 半導體，且件之特徵為：形成於該電絕緣層的表面上之 通道墊的平面性配置係製成交錯式偏移至該等電極端 Γ縱方向之—側與另-侧之—配置，並且該等再佈 _案設置為連接至該等通道塾，其中藉將該等再佈 2圖案形成較寬且以打線接合連接所獲得之接合部係 D又置於*近該等再佈線圖案的通道墊之部份上，以及 、藉從及等通道墊引出到該等相鄰電極端子的區域 上以提供該等接合部。 2·―種半㈣組件’其形成於覆蓋住—半導體晶片的一 電極端子形成表面之一電絕緣層的表面上，其中再佈 線圖案經由通道與電極端子電性連接，該半導體組件 的特徵為：藉由形成較寬且以打線接合連接的再佈線 圖案所獲得之接合部係設置於靠近該等再的 通道塾之部份。 ㈣ 人：巧專利靶圍第2項之半導體組件，其特徵為該等接 卩係叹置於在靠近該等通道塾的部份處不互相干步 之位置。 ’ 請註記並使用續頁） 0續次頁（申請專利範釀不敷使用時， 16 1284396 拾、申請專利範圍 4·如申請專利範圍第i、2 徵為 另-半導體曰片心 半導體組件，其特 ^體曰曰片女裝至該半導體晶片。 5· -種半導體封裝件，其特徵為根據”專利範圍第 之半導體組件係安裝在-主板、另—半導體晶片或另 一半導體封裝件中之任一者上。 17
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JP2007123665A (ja) * 2005-10-31 2007-05-17 Ricoh Co Ltd 半導体装置用電気回路
JP5082036B2 (ja) * 2005-10-31 2012-11-28 株式会社リキッド・デザイン・システムズ 半導体装置の製造方法および半導体装置
JP5056082B2 (ja) * 2006-04-17 2012-10-24 日亜化学工業株式会社 半導体発光素子
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CN101419634B (zh) * 2007-10-24 2010-10-20 中芯国际集成电路制造(上海)有限公司 一种可增大工艺窗口的金属层版图布图方法
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US8110931B2 (en) 2008-07-11 2012-02-07 Advanced Semiconductor Engineering, Inc. Wafer and semiconductor package
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
US20150075849A1 (en) * 2013-09-17 2015-03-19 Jia Lin Yap Semiconductor device and lead frame with interposer
JP6329059B2 (ja) 2014-11-07 2018-05-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP7263039B2 (ja) * 2019-02-15 2023-04-24 キヤノン株式会社 液体吐出ヘッドおよび液体吐出ヘッドの製造方法
CN113690258B (zh) * 2021-09-13 2024-06-21 上海天马微电子有限公司 显示面板及显示装置

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