1272419 A71272419 A7
發明背景 (a) 發明領域 本發明係關於供液晶顯示器用之薄膜電晶體陣列面板之 製法。 (b) 相關技藝之敘述 液晶顯示器（liquid cryStai display)係最普遍之FPDs (平面 顯示器）。液晶顯示器具有兩個具有電極之面板以供產生電 場且液晶層介衿其中。入射光之透過率係由施加於液晶層 之包％強度所控制。於最廣泛使用之液晶顯示器中，產生 電場之電極被提供於兩面板上，且兩面板之一具有諸如薄 膜電晶體之開關構件^ 一般而言，薄膜電晶體陣列面板係使用多個光罩藉光飫 刻法所製成，且應用了五次或六次光蝕刻步驟。因為光蝕 刻製法會造成高成本，光蝕刻步驟之次數必須予以減少。 甚至也有建議僅使用四次光蝕刻步驟之製法，而此等方法 不易於實現。 以下將描述使用四次光蝕刻步驟以製造薄膜電晶體陣列 面板之傳統方法。 首先，鋁或鋁合金閘極導線屬藉使用第一光罩被形成於 基材上’接著閘極絕緣層，非晶系矽層，n+非晶系矽層與 金屬層依序被沉積。金屬層，n+非晶系矽與非晶系矽層藉 使用第二光罩被製成圖案。在此時，閘極導線之閘極襯墊 僅被閘極絕緣層所遮蓋。一 ITO (氧化銦錫）層被沉積且藉 使用第三光罩製成圖案。在此時，於閘極襯墊上之ITO層部 73308-951102.doc 本紙張尺度適用中國國家標準(CNS) Α4規格(21〇χ297公釐） 1272419 A7 B7 五、發明説明（2 ) 伤被移除。在其下方之金屬層與非晶系矽層藉使用ιτο 層$為蚀刻光罩而被製成圖案之後，一鈍化層被沉積。藉 =第四個光罩以使在其下方之鈍化層與閘極絕緣層製成圖 案，即獲得完整的薄膜電晶體陣列面板，進而移除鈍化層 與在閘極襯墊上之閘極絕緣層之部份。 結果’鋁或鋁合金之閘極襯墊於採用四次光罩之傳統製 法下即被暴露出。該鋁與鋁合金因無法承受物理與化學刺 激，以致於極容易被破壞，縱使其具有低電阻係數之優勢 以補償前述事實，所製得之閘極線具有多層結構或由可承 受物理與化學刺激之材料所製得。然而，前者使製程複雜 彳匕’而後者具有諸如彼等材料具有高電阻係數之問題。 發明概要 所以本發明之目地係提供減少光罩次數之液晶顯示器用 薄膜電晶體陣列面板之新製法。 本發明之另一目的係保護液晶顯示器之閘極襯墊。 根據本發明，此等與其他目的，藉在兩電極被形成之前 ’形成比介於源極與汲極之其他部份較薄層之光阻（光阻） 層被實現。因此，使該薄層在某些層被蝕刻之時保護下層 ’且亦隨著其他層被蝕刻以暴露出其下層。 根據本發明，包含閘極線與連接至閘極線之閘極電極之 閘極導線，遮蔽閘極導線之閘極絕緣層，半導體圖案與歐 姆接觸層被依序形成於絕緣基材上。包含源極電極與攻極 電極之資料導線形成於同一層且彼此隔離且連接至源極電 極之資料線被形成於其上。遮蔽資料導線，但至少部份使 73308-951102.doc -6 · 木紙張尺纽财® S轉準(CNS) Α·Μ21()Χ 297公愛)~、·--；------ 1272419 A7 B7 五、發明説明（3 :及極笔極暴露出之鈍化層圖案被形成，且連接至沒極電核 之圖素電極被形成。源極/汲極之隔離係利用三部份光阻層 藉触刻與光触刻製程予以實現。第一部份係位於源極電極 與沒極電極之間且具有第一厚度，第二部份具有比第一厚 度厚之第二厚度層，而第三部份厚度為零。 在此步驟所使用之光罩具有三個部份且依如下予以對位 :邵份透光之第一部份面對光阻層之第一部份；實質上係 不透明之第二部份面對第二部份；而實質上係透明之第三 部份面對第三部份。 在此時，光罩之第一部份可能具有部份透明層或至少具 有尺寸比使用於曝光步驟光源之解析度較小之不透明部份 之圖案。 在其他方面，光阻層之第一部份可藉光阻層之逆流而被 形成。 較佳光阻層之第一部份具有相等於或小於第二部份之一 半之厚度。特別者，第二部份之厚度較佳係i微米〜2微米且 第一部份之厚度係小於4,〇〇〇埃。 根據本發明之具體實例，資料導線，歐姆接觸層圖案與 半導體圖案可藉一光罩予以形成。閘極絕緣層，半導體圖 案，歐姆接觸層圖案與資料導線經由以下之步驟被形成。 首先，閘極絕緣層，半導體層，接觸層與導電層被沉積， 且光阻層被塗覆在其上面，然後，光阻層經由一光罩予以 曝光，且被顯影以形成光阻圖案。上述光阻圖案之第二部 份被定位於資料導線之上。接著，導電層之資料導線，歐 73308:951102.doc 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 1272419 A7 p--- - B7__ 五、發明説明（4 ) 姆接觸層圖案與半導體圖案藉蝕刻在第三部份之下，第一 邵份之下，導電層與歐姆接觸層之下部份與第二部份之上 邵，之導電層部份，歐姆接觸層部份與半導體層部份被製 成，然後，光阻圖案被移除。在此時，資料導線，歐姆接 觸層圖案與半導體圖案可經由三步驟被形成。首先，在第 三邵份下方之導電層邵份被濕式或乾式蝕刻以暴露出歐姆 接觸層。然後，在第三部份下方之歐姆接觸層與半導體層 邵份隨同第一部份同時被置於乾式姓刻。因此，在第三部 份下之閘極絕緣層之邵份齊在第一部份下之導電層部份被 暴露出，且完整之半導體圖案被同時獲得。最後，藉姓刻 在第一部份與歐姆接觸層下方之導電層部份獲得完整的資 料導線與歐姆接觸層圖案。 閘極導線可具有連接至閘極線且收受外部電路信號之閘 極襯墊，資料導線可具有連接至資料線且收受外部電路信 號之資料襯墊，且鈍化層與閘極絕緣層可具有第一接觸孔 以暴露出閘極襯墊與第二接觸孔以暴露出資料襯塾。在此 時，形成經由第一接觸孔連接至閘極襯塾之冗長閘極襯塾 與經由第二接觸孔連接至資料襯墊之冗長資料襯墊之步驟 可被加入。冗長閘極襯墊與冗長資料襯墊係由與圖素電極 相同之層所形成。 根據本發明之另一具體實例，鈍化層圖案可由光阻圖案 ，製成。閘極導線可具有連接至閘極線且收受外部電路信號 之閘極襯塾，而資料導線可具有連接至資料線且收受外部 電路信號之資料襯塾。在此時，閘極絕緣層，半導體圖案 73308-951102.doc -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 1272419 五、發明説明（5 ，歐姆接觸層圖案，資料導線1化 由以下之步驟被形成。首先閘極:案人圖素電極係經 接觸層與導電層被沉積。然後，資料c層’欧姆 姆接觸橋與半導禮圖案藉_導·^纟導電橋下-歐 體層被形成。光阻層被塗覆於整=面=觸層與半導 源曝光且顯影以形成光阻圖案以：^經由光罩予以光 閘極襯塾，資料襯整與沒極電極，而份狀位於 電橋上。在藉移除覆蓋閘極 :伤被定位於導 施航沾s 、土<閘極絕緣層部份而使閘 資料椒1/露出之後’分別地遮蔽没極電極，閑極襯塾與 成圖素電極’冗長閑極襯急與冗長資料觀塾 成：先:阻圖案上。第一部份被触刻以暴露出導電橋，且第 <厚度被減少。導電橋與在其下方之歐姆接觸層 伤被移除以獲得完整之資料導線與歐姆接觸層圖案。 根據本發明之另-具體實例，一閘極導線可且 閘極線之閉極襯塾且可自外在電路接收信號，;：資料導ς 可具有連接至資料線之資料襯塾且可自外在電路接收信號 。此時’閉極絕緣層，半導體圖案，歐姆接觸層圖案，資 料導線，純化層及圖素電極經由以下之步驟被形成。首先 ，閘極絕緣層’半導體層’接觸層與導電層被沉積。然後 ，資料導綠，連接源極電極與汲極電極之導電橋，歐姆接 觸圖案，在導.電橋下之接觸橋與半導體圖案，藉蝕刻導電 層’歐姆接觸層與半導體層予以形成。在供作鈍化絕緣層 被》L·積之後’光阻層被塗覆在絕緣層上並經由光罩予以曝 9‘ 73308-951102.doc 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 1272419 A7 B7 五、發明説明（6 ) 光且顯影以形成光阻圖案使上述第三部份被定位於閘極襯 墊，資料襯墊及汲極襯墊上，而第二部份被定位於導電橋 上。接著，絕緣層之鈍化圖案藉蝕刻絕緣層與在閘極襯墊 上之閘極絕緣層部份予以形成。在此時，閘極襯墊與導電 橋被暴露出。然後，光阻圖案被移除。分別地遮蔽汲極電 極，資料襯墊與閘極襯墊之圖素電極，冗長閘極襯墊與冗 長閘極襯墊被形成於鈍化圖案之上。完整之資料導線與歐 姆接觸層圖案藉蝕刻導電橋與接觸橋被獲得。 圖示之簡易敛述 圖1係根據本發明之第一具體實例之供液晶顯示器用薄膜 電晶體陣列面板之配置圖示。 圖2與3係取圖1各自沿著線ΙΙ-ΙΓ及ΙΙΙ-ΙΙΓ之剖面圖。 圖4A係根據本發明之第一具體實例之供液晶顯示器用薄 膜電晶體陣列面板製法之第一製造步驟之配置圖示。 圖4B及4C係取圖4A沿著線IVb-IVb’及IVc-lVc’之剖面 圖。 圖5A與5B係圖4B與4C之下一製造步驟取圖4A沿著線 IVB-IVB’及 IVC-IVC’之剖面圖。 圖6A係圖5A與5B下一製造步驟薄膜電晶體陣列面板之配 置圖。 圖6B與6C分別係取圖6A沿著線VIB-VIB，及VIC-VIC，之剖 面圖。 圖7A，7B輿7C，圖8A，8B與8C，圖9A，9B與9C係具有 各種厚度之光阻層之具體實例。 73308-951102.doc - 10 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1272419 A7 B7 五、發明説明（7 ) 圖10A，11A，12A與圖10B，11B，12B分別地係圖6B下 一製造步騾取圖6B沿著線VIB-VIB’及VIC-VIC’之剖面 圖。 圖13 A係圖12A與12B下一製造步驟之薄膜電晶體陣列面 板之配置圖。 圖13B與13C分別係取圖13A沿著線XIIIB - XIIIB，及XIIIC —XIIIC’之剖面圖。 圖14係根據本發明之第二具體實例之供液晶顯示器用薄 膜電晶體陣列面板之配置圖示。 圖15與16分別係取圖14沿著線X V - X V，及X VI- X VI，之 剖面圖。 圖17A係根據本發明之第三具體實例之供液晶顯示器用薄 膜電晶體陣列面板製法之第一步驟之配置圖示。 圖17B與17C分別係取圖17A沿著線XVIIB_ X VIIB’及X VIIC- X VIIC’之剖面圖。 圖18A係圖17A，17B與17C之下一製造步騾之薄膜電晶體 陣列面板之配置圖。 圖18B與18C分別係取圖18A沿著線X VIIIB- X VIIB’及X vine- X me’。 圖19A係圖18A，18B與18C之下一製造步騾之薄膜電晶體 陣列面板之配置圖。 圖19B與19C係分別取圖19A沿著線X IXB- X IXB’及X IXC- X IXC’之剖面圖。 圖20係於圖19A，19B與19C之下一製造步驟中取19A圖沿 73308-951102.doc -11- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 1272419 A7 B7 五、發明説明（8 ) 著線X IXB- X IXB，之剖面圖。BACKGROUND OF THE INVENTION (a) Field of the Invention The present invention relates to a method of fabricating a thin film transistor array panel for a liquid crystal display. (b) Description of related art The liquid cryStai display is the most common FPDs (flat display). The liquid crystal display has two panels with electrodes for generating an electric field and a liquid crystal layer interposed therebetween. The transmittance of incident light is controlled by the % strength of the package applied to the liquid crystal layer. In the most widely used liquid crystal display, an electrode for generating an electric field is provided on two panels, and one of the two panels has a switching member such as a thin film transistor. In general, a thin film transistor array panel uses a plurality of photomasks. It is made by photolithography and applies five or six photolithography steps. Since the photoetching method causes high cost, the number of photolithography steps must be reduced. There are even proposals to use only four photolithography steps, and such methods are not easy to implement. A conventional method of manufacturing a thin film transistor array panel using a four-time photolithography step will be described below. First, an aluminum or aluminum alloy gate wire is formed on a substrate by using a first mask. Next, a gate insulating layer, an amorphous germanium layer, and an n+ amorphous germanium layer and a metal layer are sequentially deposited. The metal layer, the n+ amorphous germanium layer and the amorphous germanium layer are patterned by using a second mask. At this point, the gate pad of the gate wire is only covered by the gate insulating layer. An ITO (Indium Tin Oxide) layer was deposited and patterned using a third mask. At this time, the ITO layer on the gate pad 73308-951102.doc This paper scale applies to the Chinese National Standard (CNS) Α4 specification (21〇χ297 mm) 1272419 A7 B7 V. Invention description (2) Remove. After the metal layer and the amorphous germanium layer underneath are patterned by using the layer Å as an etch mask, a passivation layer is deposited. Borrowing a fourth mask to pattern the passivation layer and the gate insulating layer underneath, thereby obtaining a complete thin film transistor array panel, thereby removing the passivation layer and the gate insulation on the gate pad Part of the layer. As a result, the gate pad of aluminum or aluminum alloy was exposed under the conventional method using a four-time mask. The aluminum and aluminum alloys are extremely resistant to physical and chemical stimuli, so that they are easily damaged. Even if they have the advantage of low resistivity to compensate for the above facts, the gate lines produced have a multilayer structure or can withstand physical and chemical properties. Made from stimulating materials. However, the former complicates the process and the latter has problems such as the fact that the materials have a high electrical resistivity. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a novel method for fabricating a thin film transistor array panel for a liquid crystal display having a reduced number of masks. Another object of the present invention is to protect a gate pad of a liquid crystal display. In accordance with the present invention, these and other objects are achieved by forming a photoresist (resistance) layer that is thinner than the other portions of the source and drain before the electrodes are formed. Thus, the thin layer is protected from the underlying layer when certain layers are etched and also as other layers are etched to expose the underlying layer. According to the present invention, a gate line including a gate line and a gate electrode connected to the gate line is shielded from the gate insulating layer of the gate line, and a semiconductor pattern and an ohmic contact layer are sequentially formed on the insulating substrate. A data line including a source electrode and a taper electrode is formed on the same layer and isolated from each other and a data line connected to the source electrode is formed thereon. Cover the data lead, but at least partially make 73308-951102.doc -6 · Wood paper ruler New Zealand® S (CNS) Α·Μ21()Χ 297 public)~,·--;----- - 1272419 A7 B7 V. INSTRUCTION DESCRIPTION (3: A pattern of a passivation layer exposed by a pole pen is formed, and a pixel electrode connected to a immersed cell is formed. The source/drain isolation system utilizes three parts. The photoresist layer is realized by a etch and photo-etching process. The first portion is between the source electrode and the electrodeless electrode and has a first thickness, and the second portion has a second thickness layer thicker than the first thickness. And the third portion has a thickness of zero. The mask used in this step has three portions and is aligned as follows: the first portion of the light transmission faces the first portion of the photoresist layer; The second portion that is substantially opaque faces the second portion; and the third portion that is substantially transparent faces the third portion. At this point, the first portion of the reticle may have a partially transparent layer Or at least a pattern having an opaque portion that is smaller in size than the light source used in the exposure step. In other aspects, the first portion of the photoresist layer can be borrowed The photoresist layer is formed by countercurrent flow. The first portion of the preferred photoresist layer has a thickness equal to or less than one half of the second portion. In particular, the thickness of the second portion is preferably i micrometers to 2 micrometers. And the thickness of the first portion is less than 4, 〇〇〇. According to a specific example of the present invention, the data line, the ohmic contact layer pattern and the semiconductor pattern can be formed by a photomask. The gate insulating layer, the semiconductor pattern, the ohm The contact layer pattern and the data line are formed through the following steps. First, a gate insulating layer, a semiconductor layer, a contact layer and a conductive layer are deposited, and a photoresist layer is coated thereon, and then the photoresist layer is passed through a light The cover is exposed and developed to form a photoresist pattern. The second portion of the photoresist pattern is positioned over the data conductor. Next, the conductive layer of the data conductor, Europe 73308:951102.doc. Standard (CNS) A4 size (210X 297 mm) 1272419 A7 p--- - B7__ V. Invention description (4) The contact layer pattern and the semiconductor pattern are etched under the third part, under the first one. Conductive layer And the portion of the lower portion of the ohmic contact layer and the portion of the conductive layer above the second portion, the portion of the ohmic contact layer and the portion of the semiconductor layer are formed, and then the photoresist pattern is removed. At this time, The data line, the ohmic contact layer pattern and the semiconductor pattern can be formed through three steps. First, the conductive layer under the third portion is wet or dry etched to expose the ohmic contact layer. Then, in the third portion The lower ohmic contact layer and the semiconductor layer are simultaneously placed in the dry type along with the first part. Therefore, the portion of the gate insulating layer under the third portion is in the conductive layer portion under the first portion. The parts are exposed and the complete semiconductor pattern is obtained simultaneously. Finally, the complete data line and the ohmic contact layer pattern are obtained by the portion of the conductive layer whose first part is under the ohmic contact layer. The gate wire may have a gate pad connected to the gate line and receiving an external circuit signal, and the data wire may have a data pad connected to the data line and receiving an external circuit signal, and the passivation layer and the gate insulating layer may have a A contact hole exposes the gate pad and the second contact hole to expose the data lining. At this time, a step of forming a redundant gate pad connected to the gate pad via the first contact hole and a redundant data pad connected to the data pad via the second contact hole may be added. The lengthy gate pad and the lengthy data pad are formed by the same layer as the pixel electrode. According to another embodiment of the present invention, the passivation layer pattern may be made of a photoresist pattern. The gate conductor can have a gate pad that is connected to the gate line and receives an external circuit signal, and the data conductor can have a data pad that is connected to the data line and receives the signal from the external circuit. At this time, the gate insulating layer, semiconductor pattern 73308-951102.doc -8- This paper scale is applicable to China National Standard (CNS) A4 specification (210X 297 mm) 1272419 V. Invention description (5, ohmic contact layer pattern, The data wire is formed by the following steps. First, the gate electrode is deposited by the contact layer and the conductive layer. Then, the data c layer 'ohmic contact bridge and the semi-guided pattern borrowed _ guide · ^ A conductive bridge is formed under the conductive bridge layer. The photoresist layer is coated on the entire surface = the touch layer and the semiconducting source are exposed and developed to form a photoresist pattern to: ^ pass through the photomask to the optical gate lining, data lining and The electrode is not present, and the part is located on the bridge. After the cover is removed by the cover: the injury is located after the guide s s, soil < gate insulation layer and the gate material 1 / exposed Shielding the electrodeless electrode, the idler lining and the pixel-forming electrode's lengthy idler lining and lengthy data view: first: the resistance pattern. The first part is touched to expose the conductive bridge, and the first < The thickness is reduced. The conductive bridge and the ohmic contact layer underneath are removed to obtain The data wire and the ohmic contact layer pattern. According to another embodiment of the present invention, a gate wire can be closed with a gate line and can receive signals from an external circuit; the data guide can have a connection to The information of the data line is lining and can receive signals from the external circuit. At this time, the 'closed-pole insulating layer, the semiconductor pattern, the ohmic contact layer pattern, the data line, the purification layer and the pixel electrode are formed through the following steps. First, the gate The insulating layer 'semiconductor layer' contact layer and the conductive layer are deposited. Then, the data is green, the conductive bridge connecting the source electrode and the drain electrode, the ohmic contact pattern, the contact bridge under the conductive bridge and the semiconductor pattern, The etched conductive layer 'ohmic contact layer and the semiconductor layer are formed. After being used as the passivation insulating layer by the L·product, the photoresist layer is coated on the insulating layer and exposed through the photomask 9' 73308-951102.doc Paper scale applicable to China National Standard (CNS) A4 specification (210X297 mm) 1272419 A7 B7 V. Invention description (6) Light and develop to form a photoresist pattern so that the third part is positioned on the gate lining The data pad and the drain pad are disposed on the conductive bridge. Then, the passivation pattern of the insulating layer is formed by etching the insulating layer and the gate insulating layer portion on the gate pad. At this point, the gate pad and the conductive bridge are exposed. Then, the photoresist pattern is removed. The drain electrode, the data pad and the gate pad of the gate pad, the redundant gate pad and A redundant gate pad is formed over the passivation pattern. The complete data trace and the ohmic contact layer pattern are obtained by etching the conductive bridge and the contact bridge. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a first embodiment according to the present invention. A layout diagram of a thin film transistor array panel for a liquid crystal display. Fig. 2 and Fig. 3 are sectional views of the respective lines along the line ΙΙ-ΙΓ and ΙΙΙ-ΙΙΓ. Fig. 4A is a configuration diagram showing a first manufacturing step of a method for manufacturing a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention. 4B and 4C are cross-sectional views taken along line IVb-IVb' and IVc-1Vc' of Fig. 4A. 5A and 5B are cross-sectional views taken along line IVB-IVB' and IVC-IVC' of Fig. 4A, following a manufacturing step of Figs. 4B and 4C. Figure 6A is a configuration diagram of the thin film transistor array panel of the next fabrication step of Figures 5A and 5B. 6B and 6C are cross-sectional views taken along line VIB-VIB and VIC-VIC, respectively, of Fig. 6A. 7A, 7B, 7C, Figs. 8A, 8B and 8C, and Figs. 9A, 9B and 9C are specific examples of photoresist layers having various thicknesses. 73308-951102.doc - 10 - This paper scale applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1272419 A7 B7 V. Invention description (7) Figure 10A, 11A, 12A and Figure 10B, 11B, 12B FIG. 6B is a cross-sectional view taken along line VIB-VIB' and VIC-VIC', respectively, in the next manufacturing step of FIG. 6B. Figure 13A is a layout view of the thin film transistor array panel of the next fabrication step of Figures 12A and 12B. 13B and 13C are cross-sectional views taken along line XIIIB - XIIIB, and XIIIC - XIIIC', respectively, of Fig. 13A. Fig. 14 is a view showing the configuration of a thin film transistor array panel for a liquid crystal display according to a second embodiment of the present invention. 15 and 16 are cross-sectional views taken along line X V - X V, and X VI- X VI, respectively, of Fig. 14. Fig. 17A is a configuration diagram showing the first step of the method for producing a thin film transistor array panel for a liquid crystal display according to a third embodiment of the present invention. 17B and 17C are cross-sectional views taken along line XVIIB_XVIIB' and XVIIC-XVIIC', respectively, of Fig. 17A. Figure 18A is a layout view of a thin film transistor array panel of the fabrication step of Figures 17A, 17B and 17C. Figures 18B and 18C are taken along line X VIIIB-X VIIB' and X vine-X me', respectively, of Figure 18A. Figure 19A is a configuration diagram of a thin film transistor array panel of a fabrication step under Figs. 18A, 18B and 18C. 19B and 19C are cross-sectional views taken along line X IXB-X IXB' and X IXC-X IXC', respectively, of Fig. 19A. Figure 20 is taken in Figure 19A, 19B and 19C in a manufacturing step. Take the 19A picture along 73308-951102.doc -11- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 1272419 A7 B7 , invention description (8) line X IXB-X IXB, a sectional view.
圖21A與21B係圖20之下一製造步驟中取圖19A沿著線X IX B- X IXB，及X IXC- X IXC’之剖面圖。 圖22與23係根據本發明之第三具體實例且取圖14沿著線X V-X V’及X VI- X VI’之剖面圖。 圖24A，25A與圖24A，25B分別係根據本發明之第三具體 實例之圖18A至18B之下一製造步騾取圖19A沿著線X IXB- X IXB’及X IXC- X IXC’之剖面圖。 圖26A與26B分別係根據本發明之第三具體實例之圖25A 至25B之下一製造步驟取圖19A沿著線X IXB- X IXB’及X IXC- X IXC’之剖面圖 具體實例之詳細之敘述 本發明在本文件内將隨附之圖示更完整地予以描述，其 中本發明之較佳具體實例將予以說明。然而，本發明可依 多種不同形式舉例且將不被解釋成受限於在本文中所提出 具體實例； 更正確地說，此等具體實例被提供以使本發明更完全且 完整，且將完整地表達本發明之樣態予彼等熟練此方面技 藝者。於諸圖示中，為清楚之故層之厚度與區域被誇大。 相同數字參照為完全相同之構件。其將被了解當諸如層， 區域或基材之構件，被參照為係v'在另一構件之上〃時， 其可直接地在其他構件之上或亦可出現穿插其間之構件。 相反地，當一構件被參照為v直接地在另一構件上〃時， 此處並無穿插其間之構件。 73308-951102.doc -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 1272419 A7 B7 五、發明説明（9 ) 如先前所述者，製造步驟可藉於自汲極電極隔離源極電 極之步騾時將光阻圖案部份製成較保留部份為薄而予以減 少、〇 圖1係根據本發明之第一具體實例之供液晶顯示器用薄膜 電晶體陣列面板之配置圖示。而圖2與3係取圖1各自沿著線 ΙΙ-ΙΓ及ΙΙΙ-ΙΙΓ之剖面圖。 諸如銘（A1)或銘合金，麵（molybdenum)或ί目鴣（tungsten) ，鉻（Cr)與鈕（Ta)之金屬或導電材料之閘極導線被形成在絕 緣基材10之上。閘極導線包含一閘極線（掃描信號線）22在 水平方向延伸，一閘極襯墊24連接至一閘極線22之末端且 自外在電路傳送掃描信號至閘極線22，閘極電極26係薄膜 電晶體之一部份，與一儲存電極28係平行於閘極線22且將 諸如共同電壓之電壓施加至在液晶顯示器之上面板之共同 電極（未顯示出）。儲存電極28沿著連接至將在後文描述之 圖素電極82之導體圖案68形成一儲存器。液晶電容器包含 圖素電極82與共同電極。若介於圖素電極82與閘極線22間 之儲存電容夠充分則可不必提供儲存電極28。 閘極導線可具有多層結構和單層結構。當閘極導線被製 成多層結構時，較佳為其一層係由具有低電阻係數之材料 製得而另一層係由與其他材料具有良好接觸本質之材料所 製得。雙層之絡/銘（或銘合金）與銘/ 4目係此類實例。 氮化矽（SiNx)之閘極絕緣層30被形成於閘極導線之上且將 之覆蓋。 由諸如氫化非晶系矽之半導體所製得之半導體圖案42與 73308-951102.doc -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 1272419 A7 B7 五、發明説明（1C)) 4 8被形成於閘極絕緣層3 0之上。由諸如經掺雜，諸如磷不 純物加重摻雜之非晶系矽所製得之歐姆接觸層圖案（ohmic contact layer pattern)55，56與58被形成於半導體圖案42及 48之上。 由諸如翻或銦鵪合金，銘或銘合金與艇之導電材料所製 得之資料導線被形成在歐姆接觸層圖案55，56與58之上。 資料導線包含一資料線62在垂直方向延伸，一資料襯墊64 連接至資料線62末端且自外在電路傳送影像信號至資料線 62與薄膜電晶體（thin film transistor)之源極，其係資料線 62之分支。資料導線亦具有薄膜電晶體之汲極電極66與閘 極電極22或薄膜電晶體之通道部份C相對立且與資料線62相 隔離，而供作儲存電容器之導體圖案68被定位於儲存電極 28之上。當儲存電極28未被提供時，則為導體圖案68。 資料線可具有諸如閘極導線之多層結構。當然，當資料 導線具有多層結構時，較佳為其一層係由具有低電阻係數 之材料製得而另一層係由與其他材料具有良好接觸本質之 材料所製得。 歐姆接觸層圖案55，56與58扮演之角色係減少介於半導 體圖案42與48及資料線間之接觸阻抗且大體上延著該資料 線62延伸且與資料線62，資料襯墊64，源極電極65及汲極 電極66具有相同配置。換言之，在資料線62，資料襯墊64 及源極電極65下方之第一歐姆接觸層圖案55具有與資料線 62，資料襯餐64及源極電極65相同形狀，在汲極電極66下 方之第二歐姆接觸層圖案56與汲極電極66具有相同形狀， 而在導體圖案68下方之第三歐姆接觸層圖案58與導體圖案 73308-951102.doc - 14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1272419 A7 B7 五、發明説明（11 ) 68具有相同形狀。 半導體圖案42與48大體上沿著該資料線62延伸且除了薄 膜電晶體之通道部份C之外具有與資料線62，資料襯墊64， 源極電極65，汲極電極66，導體圖案68與歐姆接觸層圖案 55，56與58相同之配置。具體而言，一第一半導體圖案48 ，導體圖案68與第三歐姆接觸層圖案58具有相同之形狀， 但第二半導體圖案42與資料線62，資料襯墊64，源極電極 65，汲極電極66，導體圖案68及歐姆接觸層圖案55，56與 58具有不同形狀。換言之，資料線62，資料襯墊64與源極 電極65，特別是源極電極65與汲極電極66在薄膜電晶體之 通道部份C上係彼此相隔離，而在其下方之歐姆接觸層圖案 55與56亦彼此隔離，但第二半導體圖案42並未被分成兩段 ，因此其形成薄膜電晶體之通道。 鈍化層70被形成在資料線62，資料襯墊64，源極電極65 ，汲極電極66與導體圖案68之上。鈍化層70具有接觸孔71 ，73與74分別暴露出汲極電極66，資料襯墊64與導體圖案 68，而另一接觸孔72沿著閘極絕緣層30暴露出閘極襯墊24 。在此例中，形成在該閘極絕緣層30中之該接觸孔72與形 成在該鈍化層70中之該接觸孔72具有相同平面的形狀。鈍 化層70可被由諸如SiNx，丙烯酸有機材料，其他透明光可 解讀材料或其他有機材料之絕緣材料所製得。 接收影像信號及與上方面板之共同電極產生電場之圖素 電極82被形成於鈍化層70之上。圖素電極82被由諸如ITO (氧化錮錫）之透明導電材料所製得。圖素電極82經由接觸 孔71被物理性及電氣連接至汲極電極66且自汲極電極接收 73308-951102.doc - 15 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 1272419 A7 B7 五、發明説明（12 ) 影像信號。圖素電極82重疊於閘極線22與資料線62鄰接於 其上以增加開口率，但其可不必與彼等重疊。圖素電極82 經由接觸孔74被連接至導體圖案68且傳送影像信號至導體 圖案68 〇 經由接觸孔72與73被分別連接至閘極襯墊24與資料襯墊 64之冗長閘極襯墊84與冗長資料襯墊86被分別形成在閘極 襯墊24與資料襯墊64之上。因為此等冗長襯墊84與86保護 閘極襯塾24與資料襯塾64使免於由於外界空氣與介於外在 電路與閘極襯墊24與資料襯墊64間所選擇性補充之黏著劑 所造成之腐蚀。 於此具體實例中，透明之ITO被當作圖素電極82材料之實 例，但不透明之導電材料可被使用於反射型液晶顯示器 中 〇 現在，根據本發明具體實例之薄膜電晶體陣列面板之製 法在參照圖4A至13C與圖1至3下將予以描述。 首先，如圖4A至4C所示，諸如金屬之導體層藉諸如錢射 之方法被沉積在基材10上至具有厚度1，000至3,000埃，且包 含一閘極線22，一閘極襯墊24，一閘極電極26與一儲存電 極28之閘極導線使用第一光罩藉乾式或濕式蝕刻被形成。 接著，如圖5A與5B所示，閘極絕緣層30，半導體層40與 歐姆接觸層50藉諸如化學蒸氣沉積（CVD)依序被沉積而分 另1具有厚度1，500埃至5,000埃，500埃至2,000埃及300埃至 600埃。然後，諸如金屬之導體層60藉諸如濺射被沉積而具 有厚度1，500埃至3,000埃且具有1微米至2微米厚度之光阻層 73308-951102.doc - 16 - \ _ 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 127241921A and 21B are cross-sectional views taken along line X IX B-X IXB, and X IXC-X IXC' in Fig. 19A in a manufacturing step. 22 and 23 are cross-sectional views along line X V-X V' and X VI- X VI' in accordance with a third embodiment of the present invention. 24A, 25A and Figs. 24A, 25B are respectively a manufacturing step of Figs. 18A to 18B according to a third embodiment of the present invention. Fig. 19A is taken along line X IXB-X IXB' and X IXC-X IXC' Sectional view. 26A and 26B are respectively a detailed view of a cross-sectional view of FIG. 19A along line X IXB-X IXB' and X IXC-X IXC' according to a manufacturing step of FIGS. 25A to 25B according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION The present invention will be described more fully hereinafter with reference to the accompanying drawings in which reference herein The present invention may, however, be exemplified in many different forms and are not construed as being limited to the specific examples set forth herein; more specifically, such specific examples are provided to make the present invention more complete and complete, and The aspects of the invention are expressed to those skilled in the art. In the drawings, the thickness and area of the layer are exaggerated for clarity. The same numbers are referred to as identical components. It will be understood that when a member such as a layer, region or substrate is referred to as a v' on top of another member, it may be directly on the other member or a member interposed therebetween. Conversely, when a member is referred to as v directly on another member, there is no intervening member therebetween. 73308-951102.doc -12- This paper scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) 1272419 A7 B7 V. Invention description (9) As mentioned earlier, the manufacturing steps can be borrowed from the self-polar electrode When the step of isolating the source electrode, the portion of the photoresist pattern is made thinner than the remaining portion, and FIG. 1 is a configuration of a thin film transistor array panel for a liquid crystal display according to the first embodiment of the present invention. Illustration. 2 and 3 are cross-sectional views taken along lines ΙΙ-ΙΓ and ΙΙΙ-ΙΙΓ, respectively. A gate wire of a metal or a conductive material such as Ming (A1) or Ming alloy, molybdenum or tungsten, chromium (Cr) and button (Ta) is formed on the insulating substrate 10. The gate wire includes a gate line (scanning signal line) 22 extending in a horizontal direction, and a gate pad 24 is connected to the end of a gate line 22 and transmits a scan signal from the external circuit to the gate line 22, the gate Electrode 26 is a portion of a thin film transistor that is parallel to a storage electrode 28 in a gate line 22 and applies a voltage such as a common voltage to a common electrode (not shown) on the upper panel of the liquid crystal display. The storage electrode 28 forms a reservoir along the conductor pattern 68 connected to the pixel electrode 82 which will be described later. The liquid crystal capacitor includes a pixel electrode 82 and a common electrode. If the storage capacitance between the pixel electrode 82 and the gate line 22 is sufficient, it is not necessary to provide the storage electrode 28. The gate wire may have a multilayer structure and a single layer structure. When the gate wire is formed into a multilayer structure, it is preferred that one layer is made of a material having a low resistivity and the other layer is made of a material having a good contact property with other materials. Double-layered / Ming (or Ming alloy) and Ming / 4 mesh are examples of this. A gate insulating layer 30 of tantalum nitride (SiNx) is formed over the gate wiring and covered. Semiconductor pattern 42 made from a semiconductor such as hydrogenated amorphous germanium and 73308-951102.doc -13- This paper scale applies to China National Standard (CNS) A4 specification (210X297 mm) 1272419 A7 B7 V. Description of invention ( 1C)) 4 8 is formed over the gate insulating layer 30. An ohmic contact layer pattern 55, 56 and 58 made of, for example, an amorphous yttrium doped with phosphorus impurities such as phosphorus impurities is formed over the semiconductor patterns 42 and 48. A profile wire made of a conductive material such as a turn or indium-bismuth alloy, an inscription or alloy and a boat is formed over the ohmic contact layer patterns 55, 56 and 58. The data conductor includes a data line 62 extending in a vertical direction, and a data pad 64 is connected to the end of the data line 62 and transmits image signals from the external circuit to the source of the data line 62 and the thin film transistor. Branch of data line 62. The data conductor also has a thin film transistor whose drain electrode 66 is opposite to the gate electrode 22 or the channel portion C of the thin film transistor and is isolated from the data line 62, and the conductor pattern 68 serving as a storage capacitor is positioned at the storage electrode. Above 28. When the storage electrode 28 is not provided, it is the conductor pattern 68. The data line may have a multilayer structure such as a gate wire. Of course, when the data wire has a multilayer structure, it is preferred that one layer is made of a material having a low electrical resistivity and the other layer is made of a material having a good contact property with other materials. The ohmic contact layer patterns 55, 56 and 58 play a role in reducing the contact resistance between the semiconductor patterns 42 and 48 and the data lines and extending substantially along the data line 62 and with the data lines 62, the data pads 64, the source The electrode electrode 65 and the drain electrode 66 have the same configuration. In other words, in the data line 62, the first ohmic contact layer pattern 55 under the data pad 64 and the source electrode 65 has the same shape as the data line 62, the data lining 64 and the source electrode 65, under the gate electrode 66. The second ohmic contact layer pattern 56 has the same shape as the gate electrode 66, and the third ohmic contact layer pattern 58 and the conductor pattern 73308-951102.doc - 14- below the conductor pattern 68 apply to the Chinese national standard (CNS) A4 size (210 X 297 mm) 1272419 A7 B7 V. Invention description (11) 68 has the same shape. The semiconductor patterns 42 and 48 extend substantially along the data line 62 and have a data line 62, a data pad 64, a source electrode 65, a drain electrode 66, and a conductor pattern 68 in addition to the channel portion C of the thin film transistor. The same configuration as the ohmic contact layer patterns 55, 56 and 58. Specifically, a first semiconductor pattern 48, the conductor pattern 68 and the third ohmic contact layer pattern 58 have the same shape, but the second semiconductor pattern 42 and the data line 62, the data pad 64, the source electrode 65, and the drain The electrode 66, the conductor pattern 68 and the ohmic contact layer patterns 55, 56 and 58 have different shapes. In other words, the data line 62, the data pad 64 and the source electrode 65, in particular the source electrode 65 and the drain electrode 66 are isolated from each other on the channel portion C of the thin film transistor, and the ohmic contact layer underneath The patterns 55 and 56 are also isolated from each other, but the second semiconductor pattern 42 is not divided into two segments, so that it forms a channel for the thin film transistor. A passivation layer 70 is formed over the data line 62, the data pad 64, the source electrode 65, the drain electrode 66, and the conductor pattern 68. The passivation layer 70 has contact holes 71, 73 and 74 respectively exposing the drain electrode 66, the data pad 64 and the conductor pattern 68, and the other contact hole 72 exposing the gate pad 24 along the gate insulating layer 30. In this example, the contact hole 72 formed in the gate insulating layer 30 has the same planar shape as the contact hole 72 formed in the passivation layer 70. The passivation layer 70 can be made of an insulating material such as SiNx, an acrylic organic material, other transparent light interpretable materials or other organic materials. A pixel electrode 82 that receives an image signal and generates an electric field with a common electrode of the upper panel is formed over the passivation layer 70. The pixel electrode 82 is made of a transparent conductive material such as ITO (tantalum tin oxide). The pixel electrode 82 is physically and electrically connected to the drain electrode 66 via the contact hole 71 and is received from the drain electrode 73308-951102.doc - 15 - This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 PCT) 1272419 A7 B7 V. Description of invention (12) Image signal. The pixel electrode 82 is superposed on the gate line 22 and the data line 62 adjacent thereto to increase the aperture ratio, but it may not necessarily overlap with them. The pixel electrode 82 is connected to the conductor pattern 68 via the contact hole 74 and transmits image signals to the conductor pattern 68, and is connected to the gate pad 24 and the redundant gate pad 84 of the data pad 64 via the contact holes 72 and 73, respectively. A lengthy data pad 86 is formed over the gate pad 24 and the data pad 64, respectively. Because the lengthy pads 84 and 86 protect the gate pad 24 and the data pad 64 from being selectively replenished by the outside air and between the external circuit and the pad pad 24 and the pad 64. Corrosion caused by the agent. In this specific example, the transparent ITO is taken as an example of the material of the pixel electrode 82, but the opaque conductive material can be used in the reflective liquid crystal display. Now, the method of manufacturing the thin film transistor array panel according to the specific example of the present invention This will be described with reference to Figs. 4A to 13C and Figs. 1 to 3. First, as shown in FIGS. 4A to 4C, a conductor layer such as metal is deposited on the substrate 10 by a method such as a money shot to have a thickness of 1,000 to 3,000 angstroms, and includes a gate line 22, a gate lining. Pad 24, a gate electrode 26 and a gate electrode of a storage electrode 28 are formed by dry or wet etching using a first mask. Next, as shown in FIGS. 5A and 5B, the gate insulating layer 30, the semiconductor layer 40 and the ohmic contact layer 50 are sequentially deposited by, for example, chemical vapor deposition (CVD) to have a thickness of 1,500 angstroms to 5,000 angstroms, respectively. 500 angstroms to 2,000 Egyptians 300 angstroms to 600 angstroms. Then, a conductor layer 60 such as a metal is deposited by sputtering, such as sputtering, to have a thickness of 1,500 angstroms to 3,000 angstroms and a thickness of 1 micrometer to 2 micrometers. 73308-951102.doc - 16 - \ _ China National Standard (CNS) A4 specification (210X297 mm) 1272419
110被塗覆於導體層60之上。 此後，光阻層m經由第二光罩予以曝光且顯影形成如顯 示於圖6B與6C中之光阻圖案112與114。此時， …、 卑 >7^阻圖 案114位於源極電極65，汲極電極66與一薄膜電晶體通道部 分c之間。第二光阻圖案112位於資料線62，資料襯墊=，P 源極電極65，汲極電極66與導體圖案68將形成之資料導綠 部份A之上。殘留部份B係較第一與第二光阻圖案ιΐ2與^4 薄。殘留部份B可依蝕刻方法而具有一厚度。例如，當使用 濕式蝕刻時殘留部份B實質上具零厚度，但當使用乾式蝕刻 時殘留部份B可具有不為零之厚度。在此時，介於第一光阻 圖案114與第二光阻圖案1 p間之厚度比率視後文將描述之 蝕刻條件而定。然而，.較佳為第一光阻圖案i 14之厚度等於 或小於第二光阻圖案112厚度之一半，例如，小於6,〇〇〇埃 〇 有很多方法供以製造視條件所改變之光阻圖案之厚度， 而應用於正光阻之兩種方法將被描述。 第一種方法係如圖7A至7C所示。藉形成，諸如比光之解 析度較小之光柵或格予之圖案，或藉供應部份透明層於光 罩上以控制入射光量。 首先，如圖7A所示。光阻層200被塗覆在於基材上之薄膜 300。在此時，較佳係光阻層2〇〇係比常態為厚以控制光阻 層在顯影後之厚度。 接著如圖7B所示。光經由具有多個光柵（slits)41〇之光罩 400被照射在光阻層200。此時，光柵41〇與介於光柵間之不 73308-951102.doc -17- 1272419 A7 B7 五、發明説明（14 ) 透明部份420之尺寸係較照明系統光源之解析度為小。當使 用部份地透明層時，光罩400上留有具一厚度之鉻層（未顯 示出），曝光量因而被減少。另外，可使用包含具有不同透 光率（transmittance )膜之光罩。 當光阻層200被曝光時，光阻層200之聚合物被表面上的 光所分解（resolve)。增力u光量，則在底部之聚合物即被分 解。當底部部份之聚合物被直接曝光時曝光步驟即完成， 例如於圖7B之外部部份被完全分解。然而，接近光阻層200 之底部部份其經由slits圖案410被曝光之聚合物未被分解， 因為入射光量小於直接地曝光部份之光量。若曝光時間太 長，光阻層200之全體聚合物即被分解。所以，應被避免。 於圖7B中，參考數字210代表分解部份而數字220代表未分 解部份。在光阻層210與220顯影之後只有未分解部份220被 留下，而此處在中央處所留下之較薄部份被曝光之量少於 其它未被曝光部份。 第二種方法係利用逆流。其將在圖8A至8C與圖9A至9C中 所示之實例予以描述。 如圖8A所示。光阻層係經由分別具有實質上為透明部份 及實質上為不透明部份之兩部份210與220之光罩400曝光。 一個邵份210係全部聚合物被分解之邵份，而另一個部份 220係全部聚合物被如平般地留存之部份。然後，如圖9B所 示，光阻層被顯影以形成具有零厚度及非厚度部份之光阻 圖案。然而，如以上所述，零厚度部份可具有光阻之殘留 厚度。光阻圖案被置於逆流以使另一個部份220之光阻流入 73308-951102.doc -18- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 1272419110 is applied over conductor layer 60. Thereafter, the photoresist layer m is exposed through the second mask and developed to form the photoresist patterns 112 and 114 as shown in Figs. 6B and 6C. At this time, the ..., &> 7^ resistance pattern 114 is located between the source electrode 65, the drain electrode 66 and a thin film transistor channel portion c. The second photoresist pattern 112 is located on the data line 62, the data pad =, the P source electrode 65, the drain electrode 66 and the conductive green portion A which the conductor pattern 68 will form. The residual portion B is thinner than the first and second photoresist patterns ι2 and ^4. The residual portion B may have a thickness depending on the etching method. For example, the residual portion B has substantially zero thickness when wet etching is used, but the residual portion B may have a thickness other than zero when dry etching is used. At this time, the thickness ratio between the first photoresist pattern 114 and the second photoresist pattern 1 p depends on the etching conditions which will be described later. However, it is preferable that the thickness of the first photoresist pattern i 14 is equal to or smaller than one half of the thickness of the second photoresist pattern 112, for example, less than 6, and there are many methods for manufacturing the light changed by the viewing condition. The thickness of the resist pattern, and the two methods applied to the positive photoresist will be described. The first method is shown in Figures 7A to 7C. By forming, for example, a grating or lattice pattern having a smaller degree of resolution than light, or by supplying a portion of a transparent layer on the reticle to control the amount of incident light. First, as shown in Fig. 7A. The photoresist layer 200 is coated on a film 300 on a substrate. At this time, the preferred photoresist layer 2 is thicker than the normal to control the thickness of the photoresist layer after development. Next, as shown in Fig. 7B. Light is irradiated onto the photoresist layer 200 via a photomask 400 having a plurality of slits 41. At this time, the grating 41 〇 is not between the gratings 73308-951102.doc -17-1272419 A7 B7 5. The invention (14) The size of the transparent portion 420 is smaller than the resolution of the illumination system light source. When a partially transparent layer is used, a chrome layer (not shown) having a thickness is left on the mask 400, and the exposure amount is thus reduced. In addition, a photomask comprising films having different transmittances can be used. When the photoresist layer 200 is exposed, the polymer of the photoresist layer 200 is resolved by light on the surface. When the amount of light is increased, the polymer at the bottom is decomposed. The exposure step is completed when the bottom portion of the polymer is directly exposed, for example, the outer portion of Fig. 7B is completely decomposed. However, the polymer exposed through the slits pattern 410 near the bottom portion of the photoresist layer 200 is not decomposed because the amount of incident light is smaller than the amount of light directly exposed. If the exposure time is too long, the entire polymer of the photoresist layer 200 is decomposed. Therefore, it should be avoided. In Fig. 7B, reference numeral 210 represents a decomposed portion and numeral 220 represents an undecomposed portion. Only the undecomposed portion 220 is left after development of the photoresist layers 210 and 220, and the thinner portion left at the center here is exposed less than the other unexposed portions. The second method utilizes countercurrent. It will be described in the examples shown in Figs. 8A to 8C and Figs. 9A to 9C. As shown in Figure 8A. The photoresist layer is exposed through a mask 400 having two portions 210 and 220 of substantially transparent portions and substantially opaque portions, respectively. One of the Shao 210 series polymers is decomposed into a portion, while the other portion 220 is a portion of the polymer that is retained as a flat. Then, as shown in Fig. 9B, the photoresist layer is developed to form a photoresist pattern having a zero thickness and a non-thickness portion. However, as described above, the zero thickness portion may have a residual thickness of the photoresist. The photoresist pattern is placed in a countercurrent flow to cause the photoresist of the other portion 220 to flow in. 73308-951102.doc -18- This paper scale applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1272419
零厚度邵份以形成新光阻圖案250。 然而，介於另一個部份22〇之殘留光阻間之零厚度部份可 能無法完全藉逆流被光阻所覆蓋。為避免此類狀況，解析 度較光小之不透明圖案43〇被塗佈於如圖9A所示之光罩4〇〇 上。 然後，如圖9B所示，較薄部份23〇藉顯影被形成於另一個 邵份220之光阻之間。藉逆流此光阻圖案，即形成具有厚部 份與介於厚部份間薄部份之光阻圖案23〇。 利用此等方法，根據位置別即獲得具有不同厚度之光阻 圖案。 接著’光阻固案114與包含導體層60，歐姆接觸層50與半 導體層40之下層被置於餘刻製程。此時，此處可能殘留資 料導線與在其下方之資料導線A部份層，及僅在通道c部份 之半導體層。另外在殘留部份B之導體層60，歐姆接觸層50 與半導體層4〇被移除閘極絕緣層30。 如圖10A與10B所示，殘留部份B之歐姆接觸層50藉移除 在其上面之導體層60被暴露出。此時，可利用濕式蝕刻或 乾式蚀刻法，且較佳為蝕刻係在導體層60被蝕刻而光阻圖 案112與114未被蚀刻之條件下實施。然而，在乾式蚀刻狀 況下’因為不易找到此類條件，蚀刻可能會在光阻圖案112 與114亦被蝕刻之條下實施。於此場合，第一光阻圖案Π4 可能會較濕式蝕刻之場合厚以使導體層60不被曝光。 若導體層60由鉬或鉬鎢合金，鋁或鋁合金與妲之一所製 得，乾式或濕式蝕刻可被使用。然而，若導體層60由鉻所 73308-951102.doc -19-Zero thickness is applied to form a new photoresist pattern 250. However, the zero-thickness portion of the residual photoresist between the other portion 22〇 may not be completely covered by the photoresist by the countercurrent. In order to avoid such a situation, an opaque pattern 43A having a smaller resolution than that of light is applied to the photomask 4A as shown in Fig. 9A. Then, as shown in Fig. 9B, the thinner portion 23 is formed between the photoresist of the other trace 220 by development. By resisting the photoresist pattern, a photoresist pattern 23 having a thick portion and a thin portion between the thick portions is formed. With these methods, photoresist patterns having different thicknesses are obtained depending on the position. Next, the photoresist 114 and the conductor layer 60 are included, and the ohmic contact layer 50 and the lower layer of the semiconductor layer 40 are placed in a remnant process. At this point, there may be residual material wires and a portion of the data conductor A underneath it, and only the semiconductor layer of channel c. Further, in the conductor layer 60 of the residual portion B, the ohmic contact layer 50 and the semiconductor layer 4 are removed from the gate insulating layer 30. As shown in Figs. 10A and 10B, the ohmic contact layer 50 of the residual portion B is exposed by the conductor layer 60 removed thereon. At this time, wet etching or dry etching may be utilized, and preferably etching is performed under the condition that the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched. However, in the case of dry etching, since such conditions are not easily found, etching may be performed under the strips in which the photoresist patterns 112 and 114 are also etched. In this case, the first photoresist pattern Π4 may be thicker than in the case of wet etching so that the conductor layer 60 is not exposed. If the conductor layer 60 is made of one of molybdenum or molybdenum tungsten alloy, aluminum or aluminum alloy and tantalum, dry or wet etching can be used. However, if the conductor layer 60 is made of chrome 73308-951102.doc -19-
V 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 1272419V The paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 1272419
製得’濕式蝕刻會更佳；因為鉻不易藉乾式蝕刻移除。 CeNH03，在触刻導體層⑼之鉻時可被使用#為濕式敍刻劑 CF4與HC1或CF4與〇2之混合氣體系統系統可被使用以供 乾式蝕刻導體層60之鉬或鉬鎢，且於此場合，後者系統對 光阻層之蝕刻速率與對導體層6〇之蝕刻速率類似。 結果，如圖10A與10B所示，在通道部份c之接觸圖案67 與68與供作源極/汲極電極之資料導線部份a與儲存電容器 被殘留，而導體層60之殘留部份B被完全移除以暴露出在其 下方之歐姆接觸層50。此時，除源極電極65與汲極電極66 被彼此連接之外，導體圖案67與68具有與資料線62,資料 襯墊64 ’源極電極65，汲極電極66與導體圖案⑼相同之配 置。當使用乾式蝕刻時，光阻圖案112與114亦被蝕刻至某 一厚度。 接著’如圖11A與11B所示，在B部份之歐姆接觸層50之 暴露出部份與在其下方之半導體層4〇藉乾式蝕刻將第一光 阻圖案114予以移除。蝕刻條件可為使光阻圖案112與114， 歐姆接觸層50與半導體層40被蝕刻（半導體層與歐姆接觸層 具幾乎相同之蝕刻速率）而閘極絕緣層3〇不被蝕刻之條件。 較佳為光阻圖案112與114與半導體層40之蝕刻速率幾乎相 同。例如，可使用SF0與HC1或SF^〇2之混合氣體系統。當 光阻圖案112與114與半導體層40之蝕刻速率幾乎相同之時 ’第一光阻圖案114之厚度可相等於或小於半導體層40與歐 姆接觸層50之厚度相加總合。 然後，如圖11A與11B所示，導體圖案67藉移除通道部份 -20- 73308-951102.doc 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 1272419 A7 ---—-----5!___一 五、發明説明（17 ) " --— C之第-光阻圖案,114被暴露出’而開極絕緣層3〇藉移除B 邵f之歐姆接觸層50與半導體層40被暴露出。同時，覆蓋 於資料導線A部份之第二光阻圖案112之厚度藉蚀刻予以= 少。而且，完整之半導體圖案42與48在此步驟被獲得。參 考數字57與58分別代表在供作源極/汲極電極與儲存電容器 之導體圖案67與68下之歐姆接觸層圖案。 然後，在導體圖案67上殘留之光阻層藉灰化或電漿蝕刻 法被移除。 接著如圖12A與12B所示，在通道部份c供作源極/汲極電 極足導體圖案67與供作源極/汲極之歐姆接觸層圖案57電極 藉蝕刻法予以移除。此時，有可能因乾式蝕刻而將導體圖 案67和歐姆接觸層57均予以蝕刻，或藉濕式蝕刻以蝕刻導 體圖案67與藉乾式以蝕刻歐姆接觸層57。較佳為於前者之 場合所選定之蝕刻條件在介於導體圖案67與歐姆接觸層圖 案57之間具有最大之蝕刻選擇率。因為若蝕刻選擇率不夠 大’即難以檢測蝕刻終點與控制通道部份c週邊之半導體圖 案42之厚度。使用SI?6與〇2之混合氣體系統即為實例。於後 一％合依序實施濕式蝕刻與乾式蝕刻，被置於濕式蝕刻之 導體圖案67之側面被蚀刻而被置於乾式蝕刻之歐姆接觸層 圖案57之側面幾乎未被姓刻。因此，此等兩圖案67與”之 側面形成一階段形式^ (^4與11(：1或CF4與〇2之混合氣體系 統係供蚀刻法歐姆接觸層圖案57與半導體圖案42之蝕刻氣 體系統之實例。半導體圖案42可被製成具有均句厚度藉cf4 與〇2之混合之氣體系統予以蝕刻。此時，如圖l2b所示，半 73308-951102.doc . 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 1272419 A7 B7 導體圖案42之厚度可被減少而且第二光阻圖案112亦被蝕刻 至某一厚度。此時，蝕刻條件可被設定為不蝕刻閘極絕緣 層30，且較佳為使光阻圖案足夠厚而不致使資料線“，資 料襯塾64，源極電極65，汲極電極66與導體圖案68暴露出 結果，源極電極65與汲極電極66被隔離，且完整之資料 線62，資料襯墊64，源極電極65，汲極電極66與導體圖案 68與在下方之完整之接觸層圖案55，“與兄被獲得。 接著，在資料導線部份C上之第二光阻圖案112被移除。 然而，第二光阻圖案112之移除可在於通道部份0上之供作 源極/沒極電極之導體圖案67之移除步驟後與歐姆接觸層圖 案57之移除步驟前被實施。 總之，其可藉輪流利用濕式Μ刻和乾式蚀刻或藉僅利用 乾式蝕刻實施。 於前者之場合’於濕式蝕刻步驟之光阻圖案實質上且灾 厚度。首先，Β部份之導體層藉濕式_予以移除，而在: 下方之歐姆接觸層與半導體層藉乾式姓刻予以移除。此時 ，C部份之光轉制耗至某—厚度，^部料含有或不 必含錢2之光阻，其實質上係依㈣份之光阻層之最初厚 度而疋。當C邵份含有殘留光阻時， ^田％ _ 幻餘炙先阻藉灰化被移 除。取後，C邵份之導體層被濕蚀 4以^離源極與汲極電極 ，且C4伤<歐姆接觸層藉使用乾式蝕刻予以 於後者之場合，3部份之導體層， “ 藉乾式㈣予以移除。如前者之場合H觸層與半導體層 L #份可含有或不必 73308-951102.docIt is better to make 'wet etching'; because chromium is not easily removed by dry etching. CeNH03, which can be used when etching the chromium of the conductor layer (9), can be used as a wet smear agent CF4 and HCl or a mixed gas system system of CF4 and 〇2 for dry etching the molybdenum or molybdenum tungsten of the conductor layer 60, In this case, the etching rate of the photoresist layer of the latter system is similar to the etching rate of the conductor layer 6〇. As a result, as shown in Figs. 10A and 10B, the contact patterns 67 and 68 at the channel portion c and the data line portion a serving as the source/drain electrode and the storage capacitor are left, and the remaining portion of the conductor layer 60 remains. B is completely removed to expose the ohmic contact layer 50 underneath. At this time, in addition to the source electrode 65 and the drain electrode 66 being connected to each other, the conductor patterns 67 and 68 have the same data line 62, the data pad 64' source electrode 65, and the drain electrode 66 are the same as the conductor pattern (9). Configuration. When dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness. Next, as shown in Figs. 11A and 11B, the first photoresist pattern 114 is removed by dry etching in the exposed portion of the B portion of the ohmic contact layer 50 and the semiconductor layer 4 underneath. The etching conditions may be such that the photoresist patterns 112 and 114, the ohmic contact layer 50 and the semiconductor layer 40 are etched (the semiconductor layer and the ohmic contact layer have almost the same etching rate) and the gate insulating layer 3 is not etched. It is preferable that the etching rates of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, a mixed gas system of SF0 and HC1 or SF^2 can be used. When the etch rates of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same, the thickness of the first photoresist pattern 114 may be equal to or less than the sum of the thicknesses of the semiconductor layer 40 and the ohmic contact layer 50. Then, as shown in FIGS. 11A and 11B, the conductor pattern 67 is removed by the channel portion -20-73308-951102.doc. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 1272419 A7 --- —-----5!___ 1-5, invention description (17) " --- C - the photoresist pattern, 114 is exposed 'and open the insulation layer 3 〇 remove B Shao f The ohmic contact layer 50 and the semiconductor layer 40 are exposed. At the same time, the thickness of the second photoresist pattern 112 covering the portion A of the data line is reduced by etching. Moreover, the complete semiconductor patterns 42 and 48 are obtained at this step. Reference numerals 57 and 58 respectively represent ohmic contact layer patterns under conductor patterns 67 and 68 for source/drain electrodes and storage capacitors. Then, the photoresist layer remaining on the conductor pattern 67 is removed by ashing or plasma etching. Next, as shown in Figs. 12A and 12B, the source/drain electrode foot conductor pattern 67 and the source/drain ohmic contact layer pattern 57 electrode are removed by etching in the channel portion c. At this time, it is possible to etch both the conductor pattern 67 and the ohmic contact layer 57 by dry etching, or to wet the conductor pattern 67 and the dry type to etch the ohmic contact layer 57 by wet etching. Preferably, the etching conditions selected in the former case have a maximum etching selectivity between the conductor pattern 67 and the ohmic contact layer pattern 57. This is because if the etching selectivity is not large enough, it is difficult to detect the etching end point and the thickness of the semiconductor pattern 42 around the control channel portion c. An example is the use of a mixed gas system of SI?6 and 〇2. The wet etching and the dry etching are sequentially performed in the next %, and are etched on the side of the wet-etched conductor pattern 67 to be placed on the side of the dry-etched ohmic contact layer pattern 57 with almost no surname. Therefore, the two patterns 67 and the sides thereof form a one-stage form ^ (^4 and 11 (: 1 or a mixed gas system of CF4 and 〇2 for etching the ohmic contact layer pattern 57 and the semiconductor pattern 42 etching gas system) For example, the semiconductor pattern 42 can be etched with a gas system having a uniform thickness of cf4 and 〇2. At this time, as shown in Fig. 12b, the half is 73308-951102.doc. The paper scale is applicable to the Chinese national standard. (CNS) A4 size (210X297 mm) 1272419 A7 B7 The thickness of the conductor pattern 42 can be reduced and the second photoresist pattern 112 is also etched to a certain thickness. At this time, the etching condition can be set to not etch the gate insulation. Layer 30, and preferably such that the photoresist pattern is sufficiently thick to cause the data line ", the data lining 64, the source electrode 65, the drain electrode 66 and the conductor pattern 68 to be exposed, the source electrode 65 and the drain electrode 66 is isolated, and the complete data line 62, the data pad 64, the source electrode 65, the drain electrode 66 and the conductor pattern 68 and the complete contact layer pattern 55 below, are obtained with the brother. Next, in the data Second photoresist diagram on wire portion C 112 is removed. However, the removal of the second photoresist pattern 112 may be followed by removal of the ohmic contact layer pattern 57 after the removal step of the conductor pattern 67 for the source/dot electrode on the channel portion 0. In other words, it can be implemented by using wet etching and dry etching in turn or by dry etching only. In the former case, the photoresist pattern in the wet etching step is substantially and catastrophic. First, Β Part of the conductor layer is removed by the wet type, and the ohmic contact layer and the semiconductor layer below are removed by the dry type. At this time, the light conversion of the C part is consumed to a certain thickness. The photoresist with or without the money 2 is substantially in accordance with the initial thickness of the (four) part of the photoresist layer. When the C trace contains residual photoresist, ^田% _ 幻余炙 first resists ashing After removal, the conductor layer of C-segment is wet-etched 4 to the source and drain electrodes, and the C4 is damaged. The ohmic contact layer is applied to the latter by dry etching. , “Remove by dry (4). For the former case, the H-touch layer and the semiconductor layer L may contain With or without 73308-951102.doc
本紙張尺度適财® ®家^^71_^1〇 X -22 - 1272419 A7 B7 五、發明説明（ ） 含有殘留之光阻，且當C部份含有殘留光阻時，剩餘之光阻 藉灰化被移除。最後，C部份之導體層被乾蝕刻以隔離源極 與汲極電極，且C部份之歐姆接觸層藉使用乾式蝕刻予以移 除。 因為後者僅使用一種類型，該步驟簡單但不易找出適當 之蚀刻條件。反之，前者具有易於找出之適當蝕刻條件， 但步驟則複雜。 在藉以上之步驟製成資料線62，資料襯墊64，源極電極 65，汲極電極66與導體圖案68之後，如圖13A至圖13C所示 。具有厚度超過2,000埃之鈍化層70藉SiNx之CVD或有機絕 緣體之旋轉塗覆被製成。然後，分別暴露出汲極電極66， 閘極襯墊24，資料襯墊64與供作儲存電容器之導體圖案68 之接觸孔71，72，73與74在利用第三光罩之下藉蝕刻鈍化 層70及閘極絕緣層30被製成。 接著，如圖1至3所示。ITO層被沉積成具有厚度400埃至 500埃，且藉使用第四光罩蝕刻以形成圖素電極82，冗長閘 極襯塾84與冗長資料襯墊86。 如以上所述，於第一具體實例中，資料線62，資料襯墊 64，源極電極65，汲極電極66與導體圖案68，歐姆接觸圖 案55，56與58及半導體圖案42與48藉使用一光罩被製成， 且源極電極與汲極電極之隔離亦在此一步驟中完成。然而 ，於第二與第三具體實例中，源極電極與汲極電極係在鈍 化層形成之步驟予以隔離。 然後，根據本發明之第二具體實例之液晶顯示器與其製 73308-951102.doc -23- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 1272419 A7 B7 五、發明説明（ ) 法將參考圖14及圖21B予描述。 圖14係根據本發明之第二具體實例之供液晶顯示器用薄 膜電晶體陣列面板之配置圖示。且圖15與16分別係取圖14 沿著線XV- XV’及XVI· XVI’之剖面圖。 如圖14至16所示，根據此具體實例之薄膜電晶體面板之 結構係類似於根據第一具體實例之薄膜電晶體面板。然而 ，彼等不同處為鈍化層70具有一開口 75暴露出介於源極電 極65與汲極電極66間之半導體圖案42，且鈍化層70除了被 圖素電極82，冗長閘極襯墊84與冗長資料襯墊86覆蓋之部 份外被予以輕微蝕刻。此時，開口 75完全將源極電極與資 料電極隔離，且經由開口 75暴露出之半導體圖案42將藉在 後續將形成之排列層予以遮蓋與保護。 以下根據本發明之第二具體實例之薄膜電晶體陣列面板 之製法將參考上述之圖17A至21b與圖14至16予以描述。 首先，如圖17A至17C所示，閘極線22，閘極襯墊24，閘 極電極26與儲存電極28藉使用第一光罩在基材10上被製 成。 接著，如圖18A至18C所示，閘極絕緣層30，半導體層40 與歐姆接觸層50藉諸如化學蒸氣沉積（CVD)，依序被沉積 ，而諸如金屬之導體層60藉諸如濺射被沉積。然後，供作 源極/汲極之導體圖案67，供源極/汲極用在導體圖案67下之 歐姆揍觸層圖.案57，供薄膜電晶體用之半導體圖案42，供 儲存電容器用之導體圖案68,供儲存電容器在導體圖案68 下之歐姆接觸層圖案58與供儲存電容器用之半導體圖案48 73308-951102.doc -24- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 1272419This paper scale is suitable for ® ® ^ ^ 71_ ^ 1 〇 X -22 - 1272419 A7 B7 5, invention description ( ) contains residual photoresist, and when part C contains residual photoresist, the remaining photoresist is ash The removal was removed. Finally, the conductor layer of the C portion is dry etched to isolate the source and drain electrodes, and the ohmic contact layer of the C portion is removed by dry etching. Since the latter uses only one type, this step is simple but it is not easy to find the proper etching conditions. Conversely, the former has suitable etching conditions that are easy to find, but the steps are complicated. After the data line 62, the data pad 64, the source electrode 65, the drain electrode 66 and the conductor pattern 68 are formed by the above steps, as shown in Figs. 13A to 13C. A passivation layer 70 having a thickness of more than 2,000 angstroms is formed by spin coating of CVD or organic insulator of SiNx. Then, the drain electrode 66, the gate pad 24 are exposed, and the contact pads 71, 72, 73 and 74 of the data pad 64 and the conductor pattern 68 serving as the storage capacitor are etched by etching under the third mask. Layer 70 and gate insulating layer 30 are formed. Next, as shown in Figures 1 to 3. The ITO layer is deposited to have a thickness of 400 angstroms to 500 angstroms and is etched using a fourth mask to form a pixel electrode 82, a redundant gate liner 84 and a lengthy data pad 86. As described above, in the first embodiment, the data line 62, the data pad 64, the source electrode 65, the drain electrode 66 and the conductor pattern 68, the ohmic contact patterns 55, 56 and 58 and the semiconductor patterns 42 and 48 are borrowed. A photomask is used, and the isolation of the source electrode from the drain electrode is also completed in this step. However, in the second and third embodiments, the source electrode and the drain electrode are isolated in the step of forming the passivation layer. Then, the liquid crystal display according to the second embodiment of the present invention and its manufacture 73308-951102.doc -23- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1272419 A7 B7 V. Invention Description ( ) Method This will be described with reference to FIGS. 14 and 21B. Fig. 14 is a view showing the configuration of a thin film transistor array panel for a liquid crystal display according to a second embodiment of the present invention. 15 and 16 are cross-sectional views taken along line XV-XV' and XVI·XVI', respectively, of Fig. 14. As shown in Figs. 14 to 16, the structure of the thin film transistor panel according to this specific example is similar to the thin film transistor panel according to the first specific example. However, the difference is that the passivation layer 70 has an opening 75 exposing the semiconductor pattern 42 between the source electrode 65 and the drain electrode 66, and the passivation layer 70 is in addition to the pixel electrode 82, the redundant gate pad 84 The portion covered with the lengthy data pad 86 is slightly etched. At this point, the opening 75 completely isolates the source electrode from the data electrode, and the semiconductor pattern 42 exposed through the opening 75 will be covered and protected by the alignment layer to be subsequently formed. Hereinafter, a method of fabricating a thin film transistor array panel according to a second embodiment of the present invention will be described with reference to Figs. 17A to 21b and Figs. 14 to 16 described above. First, as shown in Figs. 17A to 17C, the gate line 22, the gate pad 24, the gate electrode 26 and the storage electrode 28 are formed on the substrate 10 by using the first mask. Next, as shown in FIGS. 18A to 18C, the gate insulating layer 30, the semiconductor layer 40 and the ohmic contact layer 50 are sequentially deposited by, for example, chemical vapor deposition (CVD), and the conductor layer 60 such as metal is sprinkled by, for example, sputtering. Deposition. Then, a conductor pattern 67 for source/drain, an ohmic contact layer for source/drain for conductor pattern 67, and a semiconductor pattern 42 for thin film transistor for storage capacitor. Conductor pattern 68, ohmic contact layer pattern 58 for storage capacitor under conductor pattern 68 and semiconductor pattern for storage capacitor 48 73308-951102.doc -24- This paper scale applies to Chinese National Standard (CNS) A4 specification (210X) 297 mm) 1272419
藉使用第二光罩依序被製成圖案。此時，供源極/汲極用之 導體圖案67除了源極電極與沒極電極被連接之外，具有如 完整薄膜電晶體之源極/汲極之相同結構。 接著，如圖19A至19C所示，具有接觸孔71，72，73與74 與開口75之鈍化層7G藉使用第三光罩被製成圖案。此時， 鈍化層70<厚度隨著所在位置改變。在薄膜電晶體通道部 份C上 < 鈍化層70部份，介於源極電極65與汲極電極66間之 鈍化邵份係較A部份薄。於圖19B與19c之B部份為接觸孔7ι ，72，73與74及開口 75部份。具有多重厚度之鈍化層7〇之 形成方法如同於第一具體實例中形成具有多重厚度之光阻 圖案112與114之方法。然而，於第一具體實例中，光阻圖 案112與114在最後才被移除，但於本具體實例中鈍化層7〇 係薄膜電晶體面板之一部份。 然後’如圖2Q所示，閘極襯墊24藉移除在接觸孔72下之 閘極絕緣層30被暴露出 '此時，較佳為蝕刻條件係設定為 蝕刻閘極絕緣層30但不蝕刻鈍化層7〇與導體圖案67與68。 所以，較佳為使鈍化層70與閘極絕緣層3〇分別為不同材料 。然而，若蝕刻條件亦足以使鈍化層7〇被蝕刻，較佳為使 鈍化層70較平常厚。 接著，如圖14，圖21A與21B所示，圖素電極82，冗長 閘極襯墊84與冗長資料襯墊86藉沉積導體層且藉使用第四 光罩形成導體層圖案被製成。 然後。如圖15與16所示，鈍化層70被乾蝕刻以形成開口 75。餘刻藉使用圖素電極82，冗長閘極襯塾84與冗長資料 73308-951102.doc -25- 本紙張尺度適用中國國家標準(CNS) A4规格(210 X 297公釐) 1272419 A7 B7 五、發明説明（22 ) 襯墊86作為蚀刻阻絕層（stopper)實施之。此時，蚀刻條件 可被設定為僅蝕刻鈍化層70。蝕刻終點係當鈍化層70之薄 部份，換言之即鈍化層70在通道之部份，被完全移除且供 源極/汲極用之導體圖案67被暴露出之時。有可能者為使用 被形成以製成圖素電極，冗長閘極襯蟄8 4與冗長資料襯蟄 86之光阻圖案作為触刻阻絕層而非彼等自身。此時，光阻 圖案可在任何後續步騾中予以移除。 源極電極65與藉蝕刻導體圖案67得之汲極電極與在其下 方之歐姆接觸層圖案57之分離方法係相同於第一具體實例 中者。 然而，更正確地說不同於第一具體實例者為，冗長閘極 襯墊84與長資料襯墊86於本具體實例中係本質性。因為若 閘極襯蟄24與資料襯墊64被暴露出而無冗長襯墊84與86時 ，襯墊24與64於隔離源極電極65與汲極電極66之步驟時將 被蚀刻掉。 接著，根據本發明之第三具體實例之液晶顯示器與其製 法將參考圖22至圖26B予以描述。於第二具體實例中，光阻 層至圖案鈍化層並無隔離，但在此具體實例中此予隔離。 因為根據本具體實例之薄膜電晶體面板之配置圖示係相 同於圖14，根據第三具體實例之薄膜電晶體之結構面板將 參考根據本發明之第三具體實例之圖14與圖22與23且取圖 14沿著線X V-X V’及X VI- X VI’之剖面圖予以描述。 如圖14，22與23所示，本具體實例之薄膜電晶體面板結 構係極類似於第二具體實例之結構。然而，不同於第二具 73308-951102.doc -26 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 1272419 A7 B7 五、發明説明（23 ) 體實例者為其未被圖素電極82，冗長閘極襯墊84與冗長資 料襯墊86所覆蓋之鈍化層70部份並未被蝕刻。 以下，根據本發明之第三具體實例之薄膜電晶體陣列面 板之製法將參考上述之圖24A至26B與圖14，22與24而被描 述。 首先，閘極導線22，24，26與28，閘極絕緣層30，供源 極/汲極用之導體圖案67，在導體圖案67下之歐姆接觸層圖 案57，供薄膜電晶體用之半導體圖案42，供儲存電容器用 之歐姆接觸層圖案58與供儲存電容器用之半導體圖案48藉 與第二具體實例相同方法予以製成。 然後，如圖24A與24B所示。鈍化層70被沉積或塗覆，且 光阻層被塗覆在鈍化層70上。然後，光阻層經由第三光罩 被曝光且顯影以形成光阻圖案122與124。此時，光阻圖案 122與124之厚度隨所在位置改變。光阻圖案122與124被置 於接觸孔71 ’ 72’ 73與74部份具有零厚度’且光阻圖案 124被置於開口 75部份係較122部份薄。如以上所述，具有 多重厚度之鈍化層70之形成方法如同於第一具體實例之方 法。 然後，如圖25A與25B所示，光阻層在通道上之薄部份 124與在其下方之鈍化層70沿著被暴露出之鈍化層70與在被 暴露出之鈍化層70下之閘極絕緣層30被蝕刻。因為蝕刻條 件應被設定為同時蚀刻鈍化70與閘極絕緣層30，較佳為使 鈍化層70與閘極絕緣層30為相同之材料。 因此，完整之接觸孔71，72，73與74與開口 75被獲得， 73308-951102.doc -27- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 1272419 A7 B7 五、發明説明（24 ) 與供源極/汲極用之導體圖案67經由開口 75被暴露出。 接著，如圖16，26A與26B所示，光阻圖案122被移除， 且諸如ITO之導體層被沉積。然後，導體層使用第四光罩予 以蝕刻以形成圖素電極82，冗長閘極襯墊84與資料襯墊86 。與第二具體實例相同之理由下，冗長閘極襯墊84與冗長 資料襯墊86係本質具有。 接著，如圖14，22與23所示，源極電極65與沒極電極之 隔離係藉蝕刻供源極/汲極用之導體圖案67並經由開口 75暴 露出，與蝕刻在導體圖案67下之歐姆接觸層57。此製法與 第二具體實例之製法相同。 雖然，第一至第三具體實例結構係僅具有圖素電極面板 ，本發明，可被應用於同時具有圖素電極與共同電極結構 之面板。 此類薄膜電晶體面板可由很多其他改更方法及多種其他 變易結構所製成。 經由本發明，供液晶顯示器用之薄膜電晶體面板之製法 被有效率地簡化，且同時，閘極襯墊與資料襯墊被保護。 於諸圖示與說明書，此處已揭示本發明之典型較佳具體 實例，且雖然使用了特定之條件，彼等僅係供範例及記述 之應用而非供限制之目的，本發明之樣態在以下之申請專 利範圍中提出。 圖式元件符號說明 10 絕緣基材 24 閘極襯墊 22 閘極線 26 閘極電極 73308-951102.doc -28 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 1272419 A7 B7 五、發明説明（25 28 儲存電極 84 閘極襯塾 30 閘極絕緣層 86 資料襯墊 40 半導體層 110 光阻層 42 半導體圖案 112 光阻圖案 48 半導體圖案 114 光阻圖案 50 歐姆接觸層 122 光阻圖案 55 歐姆接觸層圖案 124 光阻圖案 56 歐姆接觸層圖案 200 光阻層 57 歐姆接觸層圖案 210 分解部份 58 歐姆接觸層圖案 220 未分解部份 60 導體層 230 光阻圖案 62 資料線 250 光阻圖案 64 資料襯墊 300 薄膜 65 源極電極 400 光罩 66 汲極電極 410 光柵 67 導體圖案 420 不透明部份 68 導體圖案 430 不透明圖案 70 純化層 71 接觸孔 72 接觸孔 73 接觸孔 74 接觸孔 75 開口 82 像素電極 73308-951102.doc -29- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)The pattern is sequentially formed by using the second mask. At this time, the conductor pattern 67 for the source/drain has the same structure as the source/drain of the intact thin film transistor except that the source electrode and the electrode are connected. Next, as shown in FIGS. 19A to 19C, the passivation layer 7G having the contact holes 71, 72, 73 and 74 and the opening 75 is patterned by using the third photomask. At this time, the passivation layer 70< thickness changes with the position. On the thin film transistor channel portion C < the passivation layer 70 portion, the passivation trace between the source electrode 65 and the drain electrode 66 is thinner than the A portion. Parts B of Figs. 19B and 19c are contact holes 7i, 72, 73 and 74 and openings 75. The formation method of the passivation layer 7 having a plurality of thicknesses is the same as the method of forming the photoresist patterns 112 and 114 having a plurality of thicknesses in the first specific example. However, in the first embodiment, the photoresist patterns 112 and 114 are removed at the end, but in this embodiment the passivation layer 7 is part of the thin film transistor panel. Then, as shown in FIG. 2Q, the gate pad 24 is exposed by removing the gate insulating layer 30 under the contact hole 72. At this time, it is preferable that the etching condition is set to etch the gate insulating layer 30 but not The passivation layer 7 is etched and the conductor patterns 67 and 68 are etched. Therefore, it is preferable that the passivation layer 70 and the gate insulating layer 3 are made of different materials. However, if the etching conditions are also sufficient for the passivation layer 7 to be etched, it is preferable to make the passivation layer 70 thicker than usual. Next, as shown in Fig. 14, Fig. 21A and Fig. 21B, the pixel electrode 82, the redundant gate pad 84 and the redundant data pad 86 are formed by depositing a conductor layer and forming a conductor layer pattern by using a fourth mask. then. As shown in Figures 15 and 16, passivation layer 70 is dry etched to form opening 75. The engraving uses the pixel electrode 82, the lengthy gate lining 84 and the lengthy data 73308-951102.doc -25- This paper scale applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1272419 A7 B7 V. DESCRIPTION OF THE INVENTION (22) The spacer 86 is implemented as an etch stop. At this time, the etching conditions can be set to etch only the passivation layer 70. The end point of the etch is when the thin portion of the passivation layer 70, in other words, the passivation layer 70, is completely removed at the portion of the via and the source/drain conductor pattern 67 is exposed. It is possible to use a photoresist pattern formed to form a pixel electrode, a lengthy gate liner 8 4 and a lengthy data substrate 86 as a etch stop layer rather than themselves. At this point, the photoresist pattern can be removed in any subsequent steps. The method of separating the source electrode 65 from the drain electrode obtained by etching the conductor pattern 67 and the ohmic contact layer pattern 57 underneath is the same as in the first embodiment. More specifically, however, unlike the first embodiment, the lengthy gate pad 84 and the long data pad 86 are essential in this particular example. Because the gate pads 24 and the data pads 64 are exposed without the lengthy pads 84 and 86, the pads 24 and 64 will be etched away during the step of isolating the source electrode 65 from the drain electrode 66. Next, a liquid crystal display according to a third specific example of the present invention and a method thereof will be described with reference to Figs. 22 to 26B. In the second embodiment, the photoresist layer to pattern passivation layer is not isolated, but is isolated in this embodiment. Since the configuration diagram of the thin film transistor panel according to the present specific embodiment is the same as that of FIG. 14, the structural panel of the thin film transistor according to the third specific example will be referred to FIG. 14 and FIGS. 22 and 23 according to the third specific example of the present invention. 14 is taken along the cross-sectional views of lines X VX V' and X VI- X VI'. As shown in Figs. 14, 22 and 23, the thin film transistor panel structure of this specific example is very similar to the structure of the second specific example. However, unlike the second one, 73308-951102.doc -26 - This paper scale applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1272419 A7 B7 V. Description of invention (23) The portion of passivation layer 70 covered by prime electrode 82, redundant gate pad 84 and redundant data pad 86 is not etched. Hereinafter, a method of fabricating a thin film transistor array panel according to a third embodiment of the present invention will be described with reference to Figs. 24A to 26B and Figs. 14, 22 and 24 described above. First, the gate wires 22, 24, 26 and 28, the gate insulating layer 30, the conductor pattern 67 for the source/drain, the ohmic contact layer pattern 57 under the conductor pattern 67, and the semiconductor for the thin film transistor The pattern 42, the ohmic contact layer pattern 58 for the storage capacitor, and the semiconductor pattern 48 for the storage capacitor are fabricated in the same manner as the second embodiment. Then, as shown in Figs. 24A and 24B. The passivation layer 70 is deposited or coated, and a photoresist layer is coated on the passivation layer 70. Then, the photoresist layer is exposed and developed via the third mask to form the photoresist patterns 122 and 124. At this time, the thicknesses of the photoresist patterns 122 and 124 vary depending on the position. The photoresist patterns 122 and 124 are placed in the contact holes 71' 72', and the portions 74 and 74 have a thickness of zero and the photoresist pattern 124 is placed in the portion of the opening 75 which is thinner than the portion 122. As described above, the formation of the passivation layer 70 having multiple thicknesses is as in the method of the first specific example. Then, as shown in FIGS. 25A and 25B, the thin portion 124 of the photoresist layer on the via and the passivation layer 70 underneath along the exposed passivation layer 70 and the exposed passivation layer 70 The pole insulating layer 30 is etched. Since the etching conditions should be set to simultaneously etch passivation 70 and gate insulating layer 30, it is preferred that passivation layer 70 and gate insulating layer 30 be of the same material. Therefore, the complete contact holes 71, 72, 73 and 74 and the opening 75 are obtained, 73308-951102.doc -27- This paper scale applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 1272419 A7 B7 V. DESCRIPTION OF THE INVENTION (24) The conductor pattern 67 for the source/drain is exposed through the opening 75. Next, as shown in FIGS. 16, 26A and 26B, the photoresist pattern 122 is removed, and a conductor layer such as ITO is deposited. The conductor layer is then etched using a fourth mask to form the pixel electrode 82, the lengthy gate pad 84 and the data pad 86. For the same reason as the second embodiment, the redundant gate pad 84 and the redundant data pad 86 are essential. Next, as shown in FIGS. 14, 22 and 23, the isolation between the source electrode 65 and the electrodeless electrode is exposed by the conductor pattern 67 for the source/drain and is exposed through the opening 75, and is etched under the conductor pattern 67. Ohmic contact layer 57. This method is the same as the second embodiment. Although the first to third specific example structures have only the pixel electrode panel, the present invention can be applied to a panel having both a pixel electrode and a common electrode structure. Such thin film transistor panels can be made from many other modifications and a variety of other variations. According to the present invention, the method of manufacturing a thin film transistor panel for a liquid crystal display is efficiently simplified, and at the same time, the gate pad and the data pad are protected. The present invention has been described in terms of the preferred embodiments of the present invention, and, although the specific conditions are used, they are merely used for the purposes of illustration and description and not for the purpose of limitation. It is proposed in the scope of the following patent application. Schematic symbol description 10 Insulation substrate 24 Gate pad 22 Gate line 26 Gate electrode 73308-951102.doc -28 - This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 1272419 A7 B7 V. Description of the invention (25 28 storage electrode 84 gate pad 30 gate insulating layer 86 data pad 40 semiconductor layer 110 photoresist layer 42 semiconductor pattern 112 photoresist pattern 48 semiconductor pattern 114 photoresist pattern 50 ohmic contact layer 122 photoresist pattern 55 ohmic contact layer pattern 124 photoresist pattern 56 ohmic contact layer pattern 200 photoresist layer 57 ohmic contact layer pattern 210 decomposition portion 58 ohmic contact layer pattern 220 undecomposed portion 60 conductor layer 230 photoresist pattern 62 data Line 250 photoresist pattern 64 data pad 300 film 65 source electrode 400 mask 66 drain electrode 410 grating 67 conductor pattern 420 opaque portion 68 conductor pattern 430 opaque pattern 70 purification layer 71 contact hole 72 contact hole 73 contact hole 74 Contact hole 75 Opening 82 Pixel electrode 73308-951102.doc -29- This paper size applies to Chinese National Standard (CNS) A 4 specifications (210 X 297 mm)