KR100436009B1 - Method of manufacturing tft substrate with self-aligned pixel electrode - Google Patents

Abstract

PURPOSE: A method of manufacturing a TFT(Thin Film Transistor) substrate is provided to minimize coupling capacitance and crosstalk, to simplify manufacturing processes and to prevent the corrosion of a metal line by forming a self-aligned pixel electrode without wet-etching. CONSTITUTION: A photoresist layer(120) is formed on a substrate(1) via a protection layer(10). A photoresist pattern is selectively formed by performing simultaneously a front-side exposure and a rear-side exposure on the resultant structure. A transparent conductive layer(40) such as an ITO layer is formed on the entire surface of the resultant structure. A self-aligned pixel electrode is formed by removing the photoresist pattern and the ITO layer formed on the photoresist pattern.

Description

Method of manufacturing thin film transistor substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor substrate, and more particularly, to a method of manufacturing a thin film transistor substrate in which pixel electrodes formed in a pixel region are formed by self alignment.

Referring to the accompanying drawings, a structure of a general liquid crystal display device will be described.

1 is a plan view illustrating a structure of a general thin film transistor substrate, FIG. 2 is a plan view illustrating a structure of a P portion which is a unit pixel in FIG. 1, FIG. 3 is an equivalent circuit diagram of FIG. 2, and FIG. 4 is FIG. 2. Is a cross-sectional view of the portion A.

As shown in FIG. 1, a plurality of gate lines 3 are formed in a horizontal direction on the transparent insulating substrate 1, and a plurality of data lines 5 intersecting the gate lines 3 are formed in a vertical direction. have. Here, in the active area X displayed on the screen at the center of the substrate 1, there are a plurality of pixel areas P defined by data lines 5 and gate lines 3 that cross each other. In the edge pad region Y of the substrate 1, a plurality of gate pads 7 connected to the gate lines 3 and data pads 9 connected to the data lines 5 are formed.

FIG. 2 is a cross-sectional view illustrating the unit pixel region P in FIG. 1 in more detail. The gate line 3 is formed in a horizontal direction, and crosses the gate line 3 to define the pixel region P. Referring to FIG. The data line 5 is formed. The gate electrode 31, which is part of the gate line 3, the source electrode 51, the drain electrode 52, and the semiconductor layer, which are part of the data line 5, intersect the gate line 3 and the data line 5. A thin film transistor (TFT) composed of (2) is formed. In the pixel region P, a pixel electrode 4 having an edge portion partially overlapped with the gate line 3 and the data line 5 is formed, and the first electrode 53 for the storage capacitor is disposed between the data lines 5. ) Is formed parallel to the gate line 3, and the storage capacitor first electrode 53 overlaps the pixel electrode 4 and a part of the neighboring gate line 3. Here, the source electrode 51 and the storage capacitor first electrode 53 are connected to the pixel electrode 4 through the contact hole 6, and the first storage capacitor electrode 1 is disposed on the neighboring gate line 3. 53) The overlapping portion is used as the second electrode 32 for the storage capacitor.

3 is an equivalent circuit diagram of FIG. 2, wherein a first terminal is connected to a gate line 3, a second terminal is connected to a data line 5, and a third terminal is connected to a pixel electrode 4. There is a thin film transistor TFT. One unit pixel is connected to the first capacitor C _gd and the pixel electrode 4, which are formed through an insulator between the gate line 3 and the pixel electrode 4, which are connected to the thin film transistor TFT. A second capacitor C _st and a thin film transistor TFT formed between the first storage capacitor 53 and the second storage electrode 32 which is a part of the neighboring gate line 3. The third and fourth capacitors C _1dp and C _2dp are formed between the data line 5 and the neighboring data line 5 and the pixel electrode 4.

FIG. 4 is a cross-sectional view illustrating a portion A in FIG. 2, wherein a gate electrode 31 and a second electrode 32 for a storage capacitor are formed on the transparent insulating substrate 1, and a gate insulating film 8 covering them is formed. Formed. The semiconductor layer 2 is formed on a portion of the gate insulating layer 8, and is separated from the upper portion of the semiconductor layer 2, and the source and drain electrodes 51 formed on the semiconductor layer 2 and the portion of the gate insulating layer 8 are formed. 52 is formed, and a first electrode 53 for a storage capacitor is formed on the gate insulating film 8 corresponding to the second electrode 32 for a maintenance capacitor. In addition, a passivation layer 10 is formed on the substrate 1 and a contact hole 6 is formed on the source electrode 51 and the first electrode 53 for the storage capacitor. ), A pixel electrode 4 connected to the source electrode 51 and the storage capacitor first electrode 53 is formed through the contact hole 6.

Then, referring to the accompanying drawings, a more detailed description of a conventional method for manufacturing a thin film transistor substrate is as follows.

5A to 5D are sectional views showing the manufacturing method of part 2 to B according to the related art, in the order of their processes.

The gate line 3, the gate electrode 31, and the storage electrode second electrode 32 are formed on the transparent insulating substrate 1, and the gate insulating film 8 covering them is formed. Next, a semiconductor layer 2 is formed on a portion of the gate insulating film 8 that corresponds to the upper gate electrode 31, and the data line 5 and the source electrode are formed on the semiconductor layer 2 and a part of the gate insulating film 8. 51, the drain electrode 52 and the first electrode 53 for the storage capacitor are formed. Subsequently, a contact hole 6 is formed on a portion of the substrate 1 corresponding to the source electrode 51 and the storage capacitor first electrode 53 by using a transparent organic insulating film such as a polymer having a photosensitive property or an acrylic resin. , The planarized protective film 10 is formed (see FIG. 4).

Next, as shown in FIGS. 5A to 5B, a transparent conductive film 4 such as an ITO film is deposited on the protective film 10 of the substrate 1 on which the data line 5 is formed, and a positive photoresist ( 12) coating. Exposure is performed using a photomask, and the photoresist 12 in the portion developed using the developer is removed to form an opening in a portion corresponding to the data line 5.

5C to 5D, the pixel electrode 4 is etched by etching a part of the conductive film 4 using an etchant mixed with HCL, HNO ₃ and pure water, using the remaining photoresist 12 as a mask. After formation, the photoresist 12 is removed.

The pixel electrode 4 is formed to overlap the data line 5.

As described above with reference to FIG. 3, the conventional thin film transistor has a first capacitor C _gd and data between the gate line 3 and the pixel electrode 4 via the gate insulating film 8 and the protective film 10. Third and fourth capacitors C _1dp and C ₂ are formed between the line 5 and the pixel electrode 4.

However, in the conventional thin film transistor manufacturing method, since one substrate is formed by dividing into several regions, misalignment must be taken into consideration, so that the pixel electrode 4, the data line 5, and the gate line 3 overlap each other. Since the width of is increased, the capacitors C _gd , C _1dp , and C _2dp formed are large. When misalignment occurs in some regions in the process of dividing into several regions, a difference in the capacitors formed in the pixels may occur, resulting in a difference in brightness between the regions. In addition, when the width overlapped between the pixel electrode and the neighboring data line is large, a coupling capacitor acts largely to generate crosstalk in a direction in which the data line is formed in units of the signal line, thereby partially removing the pixel electrode. An etchant used for etching has a problem of rapidly corroding a data line or a gate line.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and to form a pixel electrode by uniformly forming a capacitor and eliminating wet etching even when a divided process is performed by forming a pixel electrode by self matching.

1 is a plan view showing the structure of a typical thin film transistor substrate,

2 is a plan view showing the structure of the P portion in FIG.

3 is an equivalent circuit diagram of FIG. 2.

4 is a cross-sectional view showing a portion A in FIG.

5A to 5D are sectional views showing the manufacturing method of part 2 to B according to the prior art according to the process sequence thereof,

6A to 6D and 7A to 7D are partial cross-sectional views of B and C of FIG. 2 illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, in the order of their processes.

In the method of manufacturing a thin film transistor substrate according to the present invention, a metal film is deposited and patterned on a transparent insulating substrate to form a gate electrode and a gate line, a gate insulating film is formed on the substrate, and a semiconductor layer is formed on the gate insulating film. A metal film is deposited on the substrate and etched to form a source electrode, a drain electrode, and a data line, a passivation layer is formed on the substrate, and the pixel electrode where the gate line, the data line, and the edge overlap each other is self-aligned through front and back exposure. To form.

The first storage capacitor electrode is formed at the same time as the gate line, and the second storage capacitor electrode is formed to partially overlap the first storage capacitor electrode while forming the data line.

In addition, a photoresist is deposited on the flattened passivation film, and the front and rear exposures are performed, leaving photoresist only on the portions corresponding to the data lines and the first storage capacitor electrode, and depositing a transparent conductive film on the substrate. The remaining photoresist is removed to form a pixel electrode.

Here, the mask for the back exposure is the first storage capacitor electrode, the gate line and the data line.

In the method of manufacturing a thin film transistor substrate according to the present invention, since the pixel electrode is formed through a backside exposure using a gate line and a data line as a mask, mismatching does not occur, and a portion overlapping the pixel electrode, the gate line, and the data line is minimized. do.

In addition, since the wet etching process is not used in the process of forming the pixel electrode, the gate line and the data line, which are metal lines, are not affected by the etchant.

Then, an embodiment according to the method of manufacturing the thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings so that a person having ordinary skill in the art to which the present invention pertains can easily carry out.

6A to 6D and 7A to 7D are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, in accordance with a process sequence thereof.

In the method of manufacturing a thin film transistor substrate according to an embodiment of the present invention, aluminum (Al) or an aluminum alloy (Al-alloy, Nd, W, Ta, etc.) is deposited on the transparent insulating substrate 1 to a thickness of about 200 nm. Then, the photolithography process is performed to form the gate line 3, the gate electrode 31, and the first storage capacitor electrode 32 that is part of the gate line 3.

In the case of the independent wiring system, the independent wiring can be added to form the first storage capacitor electrode 32.

Next, on the substrate 1, a gate insulating film 8 made of a nitride film or an oxide film having a thickness of about 200 to 400 nm, an undoped amorphous silicon layer of 200 nm or less, and an amorphous silicon layer doped at a high concentration of about 50 nm. To be deposited. Here, it is preferable to deposit the two amorphous silicon layers at 230 to 300 degrees and the gate insulating film at 200 degrees or more. Subsequently, a photolithography process is performed using an active mask to etch two layers of amorphous silicon, leaving only a portion corresponding to the gate electrode 31.

Next, a metal film such as chromium (Cr), Al, Al-alloy, etc. is deposited on the substrate 1 to a thickness of about 100 to 400 nm, and a photolithography process is performed to perform data line 5, source electrode 51, and drain electrode. 52 and the second storage capacitor electrode 53 are formed. Subsequently, the semiconductor layer 2 is formed by etching a portion of the amorphous silicon layer that is heavily doped in the portion where the channel is formed using the source and drain electrodes 51 and 52 as a mask.

Next, a protective film 10 is formed on the substrate 1 by coating a transparent organic insulating film such as a polymer having a photosensitive property or an acrylic resin with a thickness of 2 μm. It is preferable to planarize the protective film 10 here. Subsequently, portions corresponding to the source electrode 51 and the second storage capacitor electrode 53 are partially etched through a photographic process to form a protective film 10 included in the contact hole 6 (see FIG. 4).

Next, as shown in FIGS. 6A and 7A to 6B and 7B, the photoresist 120 is coated to a sufficient thickness on the substrate 1. UV exposure is performed using a photomask and backside exposure is performed using the data line 5 and the first and second storage capacitor electrodes 53 and 32 as masks. In this case, a portion where light is not irradiated to the photoresist 120 through the photomask is a portion where the data line 5 and the second storage capacitor electrode 53 and the first storage capacitor electrode 32 overlap each other. The portion corresponding to the first storage capacitor electrode 32 is omitted. Therefore, when the photoresist 120 of the exposed portion is removed using a developing solution, only the portion corresponding to the first storage capacitor electrode 32 that does not overlap the data line 5 and the second storage capacitor electrode 53 is removed. The photoresist 120 remains. Here, the photoresist 120 is removed on the source electrode 51 and the second storage capacitor electrode 53.

6C and 7C to 6D and 7D, the protective film 10 of the substrate 1 having the contact hole 6 on the source electrode 51 and the second storage capacitor electrode 53. ), A transparent conductive film 40 such as an ITO film is deposited on the upper portion, and the photoresist 120 and the transparent conductive film 40 formed thereon are simultaneously removed to form the pixel electrode 40.

In the method of manufacturing a thin film transistor substrate according to the exemplary embodiment of the present invention, the pixel electrode 40 is formed through backside exposure using the gate line 3 and the data line 5 as a mask, and thus the process of dividing the pixel electrode 40 into a plurality of times. Does not occur. In addition, since the pixel electrode 40 is formed to be self-aligned, a portion overlapping with the pixel electrode 40, the gate line 3, and the data line 5 is minimized, so that the pixel electrode 40 is interposed between the pixel electrode 40 and the data line 5. The capacitors C _1dp and C _2dp formed and the capacitor C _gd formed between the pixel electrode 40 and the gate line 3 are formed to a minimum. Since they are formed by self matching, the capacitors formed in all the pixel regions are the same.

In addition, since the wet etching process is not used in the process of forming the pixel electrode 40, the gate line 3 and the data line 5, which are metal wires, are not affected by the etchant.

Therefore, in the method of manufacturing a thin film transistor according to the present invention, the pixel electrodes are formed by self matching to uniformize and minimize the capacitors generated in the pixel region, thereby minimizing the coupling capacitor and the crosstalk, and eliminating the wet etching process. Simplification, thereby preventing the corrosion of the metal wiring.

Claims (5)

Depositing a conductive material on a transparent insulating substrate and performing a photo process to form a gate line, a gate electrode, and a first storage capacitor electrode connected to the gate line; Continuously depositing a gate insulating film made of a nitride film or an oxide film, an undoped amorphous silicon layer, and a heavily doped amorphous silicon layer on the substrate, Patterning the two layers of the amorphous silicon layer by a photolithography process with an active mask to form a semiconductor layer, Terminating a conductive material on the substrate and performing a photo process to form a data line, a source electrode and a drain electrode, and simultaneously forming a second storage capacitor electrode on the first storage capacitor electrode; Etching the heavily doped amorphous silicon layer using the source and drain electrodes as masks; Forming a protective film by coating a transparent organic insulating film such as a polymer or an acrylic resin having photosensitivity on the substrate, Patterning the passivation layer to form contact holes exposing the source electrode and the second storage capacitor electrode, respectively; Forming a pixel electrode connected to the source electrode and the second storage capacitor electrode through the contact hole on the passivation layer, the pixel electrode overlapping the data line at least at both edge portions thereof; . The method of claim 1, wherein the forming of the pixel electrode comprises: A photoresist was formed on the substrate, the photomask was used for exposure, and the backside exposure was performed using the data line, the gate line, and the first and second storage capacitor electrodes as a mask, thereby performing the first storage capacitor. Leaving the photoresist only on an upper portion of the passivation layer in a portion corresponding to a portion of the electrode, a data line and a gate line Removing a photoresist on the source electrode and the second storage capacitor electrode; And depositing a transparent conductive film such as an ITO film on the protective film and removing a portion of the photoresist and the transparent conductive film. The method of claim 2, wherein a part of the first storage capacitor electrode is a portion except for a portion where the first storage capacitor electrode and the second storage capacitor electrode overlap each other. The method of claim 1, wherein the first storage capacitor electrode protrudes from the gate line. The method of claim 1, wherein the gate line or the data line is formed by stacking chromium (Cr), aluminum, or an aluminum alloy.