TWI268602B - Semiconductor device featured with using micro bumps to connect the first semiconductor chip and the second semiconductor chip when stacking the first semiconductor chip and the second semiconductor chip together - Google Patents

Semiconductor device featured with using micro bumps to connect the first semiconductor chip and the second semiconductor chip when stacking the first semiconductor chip and the second semiconductor chip together

Info

Publication number
TWI268602B
TWI268602B TW094103849A TW94103849A TWI268602B TW I268602 B TWI268602 B TW I268602B TW 094103849 A TW094103849 A TW 094103849A TW 94103849 A TW94103849 A TW 94103849A TW I268602 B TWI268602 B TW I268602B
Authority
TW
Taiwan
Prior art keywords
semiconductor chip
semiconductor
micro bumps
connect
stacking
Prior art date
Application number
TW094103849A
Other languages
English (en)
Other versions
TW200539430A (en
Inventor
Kazuhiro Kondo
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of TW200539430A publication Critical patent/TW200539430A/zh
Application granted granted Critical
Publication of TWI268602B publication Critical patent/TWI268602B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Wire Bonding (AREA)
TW094103849A 2004-02-16 2005-02-05 Semiconductor device featured with using micro bumps to connect the first semiconductor chip and the second semiconductor chip when stacking the first semiconductor chip and the second semiconductor chip together TWI268602B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004038403A JP3918818B2 (ja) 2004-02-16 2004-02-16 半導体装置

Publications (2)

Publication Number Publication Date
TW200539430A TW200539430A (en) 2005-12-01
TWI268602B true TWI268602B (en) 2006-12-11

Family

ID=34857804

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094103849A TWI268602B (en) 2004-02-16 2005-02-05 Semiconductor device featured with using micro bumps to connect the first semiconductor chip and the second semiconductor chip when stacking the first semiconductor chip and the second semiconductor chip together

Country Status (7)

Country Link
US (2) US7294936B2 (zh)
EP (1) EP1610383A4 (zh)
JP (1) JP3918818B2 (zh)
KR (1) KR101116325B1 (zh)
CN (1) CN100423260C (zh)
TW (1) TWI268602B (zh)
WO (1) WO2005078797A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007265019A (ja) 2006-03-28 2007-10-11 Sony Computer Entertainment Inc 演算処理装置
KR100837554B1 (ko) * 2006-09-28 2008-06-12 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
KR100843214B1 (ko) * 2006-12-05 2008-07-02 삼성전자주식회사 메모리 칩과 프로세서 칩이 관통전극을 통해 연결된 플래너멀티 반도체 칩 패키지 및 그 제조방법
CN104699639B (zh) * 2013-12-10 2018-06-01 联想(北京)有限公司 电路板及电子设备

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117252A (ja) * 1982-12-24 1984-07-06 Hitachi Micro Comput Eng Ltd 半導体装置
JPH05109977A (ja) * 1991-10-18 1993-04-30 Mitsubishi Electric Corp 半導体装置
US5838603A (en) * 1994-10-11 1998-11-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chip
JPH08167703A (ja) * 1994-10-11 1996-06-25 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法、ならびにメモリコアチップ及びメモリ周辺回路チップ
TW520816U (en) * 1995-04-24 2003-02-11 Matsushita Electric Ind Co Ltd Semiconductor device
JPH09152979A (ja) * 1995-09-28 1997-06-10 Matsushita Electric Ind Co Ltd 半導体装置
JPH10200062A (ja) 1997-01-04 1998-07-31 T I F:Kk 半導体装置
JPH11168185A (ja) * 1997-12-03 1999-06-22 Rohm Co Ltd 積層基板体および半導体装置
TW456005B (en) 1999-10-12 2001-09-21 Agilent Technologies Inc Integrated circuit package with stacked dies
DE10142119B4 (de) * 2001-08-30 2007-07-26 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zu seiner Herstellung

Also Published As

Publication number Publication date
EP1610383A1 (en) 2005-12-28
CN100423260C (zh) 2008-10-01
JP2005229050A (ja) 2005-08-25
TW200539430A (en) 2005-12-01
US7294936B2 (en) 2007-11-13
US20070246835A1 (en) 2007-10-25
KR20060132436A (ko) 2006-12-21
CN1765021A (zh) 2006-04-26
KR101116325B1 (ko) 2012-03-09
US20060290004A1 (en) 2006-12-28
EP1610383A4 (en) 2010-08-25
JP3918818B2 (ja) 2007-05-23
WO2005078797A1 (ja) 2005-08-25

Similar Documents

Publication Publication Date Title
TW200608557A (en) Stacked semiconductor device
WO2006137819A3 (en) High density vertically stacked semiconductor device
TW200737482A (en) Stack package utilizing through vias and re-distribution lines
SG143240A1 (en) Multi-chip package structure and method of forming the same
SG121705A1 (en) Semiconductor package
WO2006138425A3 (en) Chip spanning connection
SG170678A1 (en) Integrated circuit packaging system with package-on-package stacking and method of manufacture thereof
WO2009079772A8 (en) Method for stacking serially-connected integrated circuits and multi-chip device made from same
TW200705624A (en) Laminated semiconductor package
WO2011044385A3 (en) Vertically stackable dies having chip identifier structures
SG148851A1 (en) Stacked semiconductor packages
WO2005122249A3 (en) Semiconductor device module with flip chip devices on a common lead frame
TW200721399A (en) Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
FR2893764B1 (fr) Boitier semi-conducteur empilable et procede pour sa fabrication
EP1681717A4 (en) ELECTRONIC DEVICE AND PROCESS FOR THEIR MANUFACTURE
TW200627563A (en) Bump-less chip package
WO2004034432A3 (en) Power mosfet
WO2006035321A3 (en) Structurally-enhanced integrated circuit package and method of manufacture
WO2006036358A3 (en) Power led package
TW200627555A (en) Method for wafer level package
WO2006051527A3 (en) Integrated circuit die with logically equivalent bonding pads
TWI268602B (en) Semiconductor device featured with using micro bumps to connect the first semiconductor chip and the second semiconductor chip when stacking the first semiconductor chip and the second semiconductor chip together
WO2006010903A3 (en) Multiple chip semiconductor device
TWI264127B (en) Chip package and substrate thereof
WO2007047808A3 (en) Stacked integrated circuit chip assembly

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees