TWI266404B - Dummy structures extending from seal ring into active circuit area of integrated circuit chip - Google Patents

Dummy structures extending from seal ring into active circuit area of integrated circuit chip Download PDF

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Publication number
TWI266404B
TWI266404B TW094142544A TW94142544A TWI266404B TW I266404 B TWI266404 B TW I266404B TW 094142544 A TW094142544 A TW 094142544A TW 94142544 A TW94142544 A TW 94142544A TW I266404 B TWI266404 B TW I266404B
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Taiwan
Prior art keywords
redundant
integrated circuit
active circuit
active
circuit chip
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Application number
TW094142544A
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English (en)
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TW200705636A (en
Inventor
Hsien-Wei Chen
Original Assignee
Taiwan Semiconductor Mfg
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Publication of TWI266404B publication Critical patent/TWI266404B/zh
Publication of TW200705636A publication Critical patent/TW200705636A/zh

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    • H—ELECTRICITY
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    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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Description

1266404 九、發明說明： 【發明所屬之技術領域】 . 树败致》可以強化積體電路(integrateddmiit，IC)軸 強 度之几餘結構，尤指從封環(sed ring)結構延伸進入1(：晶片之一 ▲ '的：ή：健構。 动電路區 【先前技術】 1C晶片彼此之間一般是透過導線(像是金線或是鋁線)連接到一#壯分 • 構的一導線架(leadframe)或是一底持上，以便傳遞或是接收外界的传號衣= 樣的導線，-般是透過熱壓合或是超音波震盪的方式，直接谭接在=曰曰°思 的接合焊墊(bondingpad)上。導線烊接的過程，往往對接合焊塾二下= 屬間介電(inte酬al dielectric，IMD)層、以及接合焊墊底下所有的結構，、= 加了熱應力或是機械應力。.因此，接合焊墊的結構跟^層，就需 承受這樣的應力，而且，也要確保良好的焊接效果，並要避免對^ 3 造成傷害。 、日日门 較早期的焊墊結構是從最下層一直做到最上層，完全不容許電路中的 籲傳導線或是半導體元件，從焊墊結構底下穿過去或者是待在焊塾結構底 下。為了充分運用晶片的面積以及縮小晶片的大小，所以需要把半導體元 件或是傳導線放在焊墊結構底下。這樣的技術一般稱作主動電路上的焊接 (bond over active drcuits，B0AC)或是谭墊下電路(drcuits 皿加—， 同時的，半導體製程也開始於運用具有低介電常數(1〇wk)或是超低 介電常數(uitm low k)的材料，以便降低電阻電容延遲(RC如㈣與寄生電 容。，目前_設計的趨勢是，讓晶片的最上層到底下的基底㈣祕e)，介 電常數依序遞減。然而，正因為介電常數變小了，一般來說，介電材料的 機構強度也是變差。而且，許多的低介電常數枯料都很容易龜裂，或是沒 有足狗的機構強度來承受後續的-些具有較大應力的製程(譬如說焊接導線 0503-A31125TWF/Edward 1266404 或是化學機械研磨(chemical mechanic polish，CMP))。低介電常數材料不僅 僅是難以承受擠壓的應力，而且面對切應力(shear strength)時，黏著力也是 一大問通。這樣的結不’彺往導致了剝離脫落^peeling or lamination)的情 形發生。 在一般的焊接導線過程中，接合焊墊必須承受壓應力以及侧向的切應 力，尤其是在焊接導線時對金屬球擠壓時。這樣的應力可能導致底下脆弱 的介電層龜裂。當金屬導線被焊接機台從晶片上的焊墊拉扯時，接合焊墊
結構也要承受拉應力跟扭應力。這樣的應力可能導致接合焊墊剝離脫落或 是移位的情形發生。 目前-般的冗餘結構，妓放在主動電路結構之間，用來強化晶片上 的放層之減強度。樣的職結構—般是使麟主動電路巾的傳導線以 及接合焊墊-樣的㈣，並且是在—樣的製程下同時產生。這些冗餘結構 對於補強晶片之機構強度，以及降低_剝離的效能上，有相當的幫助。 當晶片從-個晶圓上切割下來時，晶片會再一次遭受大機械應力，f 如壓應力跟切應力。如此的應力可能導致_、剝離、脫落，甚至是晶片 上-大塊部份都可能整個被剝掉。為了克服這樣的應力’晶圓上晶片跟晶 片之間的切割道，就必須被適當的下來n 最 上所能得到㈣諸量，„要縮小切割道喊度。但是啊地早如^ 上所，大量齡__制，已_細層彳隱弱了，所 較寬的切割道。為了克服這樣的兩難問題，封環㈣㈣結 ==產生。封環就像是一堵牆般的結構，圍繞在晶 封壤疋在形脇_導電結構時，_以及/或多㈣轉便形成。 所以，就需要有i結構’能夠讓接合焊 切割過程中，得財_的應力,是必她== 細層的錄，^最聽«料是树隨戦錢合==數的 0503-A31125TWF/Edward 6 1266404 【發明内容】 本發明之一實施例提供一積體電路晶片。一 路區中。,. 、電路形成在一主動雷 封娘㈣rmg)結構至少部份的圍繞該主動電路F 一… 。 (d_y)結構延伸自該封環結構並伸入該主動電路區。一弟一冗餘 路區=二'’:例&二:積體電路晶片。-積體電路形成在一主動電 _(seal rm§)結構至少部份的圍繞該主動雷路區。— (d_y)結構延伸自該封環結構並伸人該絲電路卜了一几餘 =3靖爾你軸 冗餘構了^餘結構下。一冗餘接孔連接該第-與該第二 。本^之—實施例提供—積體電路“。—積體電路形成在—主動電 路區中。數個冗餘支柱㈣ar)結構，形成於該主動電路區中。_封環㈣ :二均份的圍繞該主動電路區。—第—冗餘咖㈣,)結構延伸自該_ 結構並伸入該主動電路區。 衣 【實施方式】 第1圖顯示了一1C晶片的一部份之剖面圖。第1圖的晶片20有一部 分的主動電路22是位於接合焊墊24之下。第丨圖也顯示了 _部份的封環 30，大致是在晶片2〇周圍，環繞著主動區32。第丨圖也顯示了一些作為範 例的冗餘結構34，散佈在晶片20中的主動電路區32中。冗餘結構34與封 環30都有在晶片2〇中使用，但是都是完全的分開，也就是沒有連接或是 黏在一起。 第2圖與第3圖是依據本發明的一實施例之一 ic晶片20。第2圖顯示 的是在一晶圓上之IC晶片2〇的部分區域的剖面圖。更明白的說，第2圖 是1C晶片20的外圍接近晶片附近之放大圖，作為舉例說明用。第3圖為 1C晶片20的上視圖，用來顯示某，層的佈局，也僅僅是作為舉例說明用。 0503-A31125TWF/Edward 7 1266404 大致上來說，本發明的實施例提供的 ^ 冗餘結構40連接在封产川』 /、啕封環30與冗餘結構4〇, 以下開於第-每^ 是說冗餘結構4〇從封環3〇延伸出來。 Μ於弟例的說明將與第2圖以 30 20 ^ 0 3 可月趨地放置在晶片2〇的周圍，曰而5封匕〇 可能在整個結構上，有―兩個斷點 :不=績的，以就是說， 續的。一所 材料，或是隨著在封環結構3G 道躺用-振的 結構30跟冗餘社槎如p 方不^封七所不同。最好是封環 〜構4。、丄;:=是 傳導線(Wire)44在那—層所使_ 二/^、純㈣以及/或 部的宜一層中之^^ 凡’圖形。在弁他貫施例中，部份或是全 餘碎構40、34所用的材料，跟主動電路/傳_ 14 ,乂及/ :==_線物或節=== 構30、34與4Q，這就’比^ t些額外偷綱是瓣形成结
Jr贿物_而形成，職爾最好要比細 材料、金屬二，這種材料可能是，但不限定是··導電 或是上述的組合。二金屬雜物、上述的合金或化合物、 任何適當的材料而或是全部的某—層中之封環結㈣可以用 較高的_度，2材;^轉也是_tb細層綱_具有 鶴、铭、多晶石夕、金屬但不限定是：導電材料、金屬、銅、 雖然說，在圖上的封科相合金或化合物、或是上述的組合。 線44等使用了不不同部份的冗餘結撬Μ 勺圖案表不，這僅僅是為了區別晶片20上不同地方， 〇503-A31125TWF/Edward 8 1266404 而這些地方可能用-模-樣或是類似的材料。 構：：==::，那~ 伸到晶片20的主動電路區32去，如同第2圖與第 ” 反 40設置在主動電路部份44 θ 、 "不。几餘結構34、 44之U近，也設置麵 冗餘結構34、40的形狀跟大小可能有所變化。最好，可以在不 =之間。 設計規範(designs的條件下，把冗餘結構μι加以最大化。日日如 在曰圖所顯示的第一實施例卜有-部份的積體電路22是 ι爾&中，同時也在接合焊塾24底下。_說這禮的 ，、關«不主Μ -部分的積體電路η放在接合焊塾 一上力的I怨下，也就是說，可以不是CUP設計。 > t同弟2圖所不，冗餘接孔(ciummy via)46連接了冗餘結構Μ、恥 垂直方向上相重疊的部分。這樣，可以提供冗餘結構％、㈣直方向上 迷接’可以更加祕固晶片的機構強度。在別的實施例當中，這樣的冗餘 接孔46鱗可以不必使用。連串的冗餘接孔46可以用來連接許多層，進 而开/成垂直方向上的几餘支挺，來更進—步的增航餘結構％、術斤提供 的機構強度。這樣給的冗餘結構34、4〇所用的冗餘接孔46可以在跟晶片、 20中的其他結構(像是主動電路44中的接孔)一起同時形成，以避免發 要額外步驟來製作這些結構的情形發生。 此外封％結構30最好是一連貫的從上到下，如同第2圖所示。封壤 、、構中+有許夕不樣的層，相鄰兩層之間用接孔48連接在一起。但是， 在別h㈣i(未_示)中，封環結構巾3㈣上部分跟下部分不—定要在绮 環結構30中連接在_去已，上^ _ 文你吳也有可能不連，或是間接的透過冗餘結構4〇跟 几餘接孔46相連。此外，封環結構％可能只有在晶片如中的某幾層中形 0503-A31125TWF/Edward 9 1266404 成。譬如說，在某些實施例中，可能只有上部分、只有中部分、只有下部 分、或是只有上部分跟下部分。 本發明的一實施例可以提供以下數個優點·· 增強晶片的整個機構強度； 增加附著性，以防止剝離； 容許比較小的切割道； 防止或降低在切割晶片時，所產生的剝離或是損害之情形； 防止或是降低在壓應力時所產生的龜裂； 增加晶片可以承受的應力耐受度； 厂々止或疋·降低晶片在焊接導線時所產生的損宝； 除了佈局輯或是設計雜外，不需要㈣製程上的步驟。 心雖然並非必要，但是最好有越多的冗餘結構4〇可以跟封環結構3〇相 :接被’這樣可以最大化冗餘結構40與封環結構3〇的整合度。這樣的 :大化可以透過使祕局工具巾的算法或是_個軟體卫具 —層的佈局過程中達成。第4關第7 _示了本 ==:不__局圖…_第7圖將可 …可可以自動地將几餘結構佈局在用預定設計規範的声上。 =的設纟嫩咐'賴纽—些__彳，舉娜說1層所^的 近層所使用主動料線之材料；當層之接孔所使用的材料；鄰 ^線的大小，層與層之間歧驗的線與結構 1 構之_隔距離；微影技術所制成 二
上僅僅是糊，可钟与相細去A turn组合。U 第4 Μ第7 素不必然都要考慮所有的因素。 階4之=T: IC晶片其中… 二=πΤ有數個主動傳導線㈣ 主動傳g 44。叫’封環3〇在那—層的部分也顯示在 0503-A31125TWF/Edward 066404 導線靖5G所環繞。保護帶50所代表的就是主動傳 作過辦，求的最小間距。當真正的佈局工具的實際操 第5円=的保可能會、也可能不會顯示出來。 布：中，依據設計規範， 同的實施例，可_同 、㈣延伸出來。不 剩下的办門+ , 札乏1甲的方式也可能不一樣。接著， 閱第6 ^ 增入沒有跟封環結構3〇相連接的冗餘結構34，請參 下面的層中之冗餘結構40連接到封環¥3〇^間^透過其他上面或是 圖中無況是第4圖到第7 成了，如同第7圖所示。 τ卓之後那一層所需要的怖局圖就完 跟封的冗餘結構34是在冗餘結構如直接 的先後频序，^放^上靖見第5圖與第6圖）。但是’這樣 顯示，在样明貫賴而言，並非絕對必要的。譬如說，雖然沒有 餘結構34級置或是她結卿錢連接的冗 := 置或是_;也可以進行。心，在其他實施J几 =:構。〇直接連冗餘結構34可以在其他的階段才放置或是 ^=4有跟封環結構30直接連接的冗餘結構34可以依照大 先_技_結構34 ’剩下的空間才放置較㈣ 4。此外，—賴是Μ的佈局可驗其㈣—層或衫層有關， ^取大化冗餘接孔46以及/或是冗餘編咖。因此，就可以 化一個佈駐具，使其在佈過程當巾，來自_完成社所述的工作， =且符合駿的設計規範的需求。這樣預設的設計規範，可以寫在軟體演 异法中，來決定佈局放置的準則， .’、 以下在這-段f所提_步驟。這些步驟_序可能不_樣，可能是依序 0503-A31125TWF/Edward 11 1266404 進盯，也可能是部分重疊，也可能是平行處理 主動區中。-封環結構至少部份的圍繞該主動 先形成在-晶片的一 -層時，形成―第—冗餘結構，並使其延伸=鄉。當形成封環結構的 路區。當形成封環賴義糾，以钱構並伸人該主動電 . 田成該弟一冗餘結構時，可以形 成Μ C的傳導線之一部份。該第一冗餘結 夕門。分-， 」乂延伸於該1C中的傳導線 之間該封環結構在該層中的部分、該第_ 的邱八_ 几餘枯構、以及該1C的傳導線 的口F刀，可以用一樣的材料形成。 就某另一方面而言，本發明提供了製造ic曰η沾丄 ^ _ 衣日日片的乃法。這個方法包含 有以下在這一段中所提到的步驟。這些步驟的順序可能不一樣，可能是依 序進行，也可能是部分重疊，也可能是平行處理。晶片中，位於主動 的1C，先形成一層的傳導線。开>成一封環結構的一部份，至少部份的圍銬 該主動電路區位於該層的部分。形成冗餘結構，並使其在該層的部分，延 伸自該封環結構並伸入該主勳電路區。選擇性的放置該等冗餘結構，以最 小化地放置於在該層中該封環結構與該傳導線之間的介電材料區域。該耸 冗餘結構的選擇跟放置是用/軟體演算法自動完成。而用該演算軟體的選 擇跟放置是根據一套預設的設計規範。而且，用該演算軟體的選擇跟玫置 可以在佈局的過程當中，用，個佈局工具來進行。 0503-A31125TWF/Edward 1266404 【圖式簡單說明】 第1圖顯示了一 1C晶片的一部份之剖面圖。 第2圖顯示的是在一晶圓上之1C晶片20的部分區域的剖面圖。 第3圖為1C晶片20的上視圖，用來顯示某一層的佈局。 第4圖到第7圖顯示了本發明的一第二實施例中的一個佈局流程中不 同階段時的佈局圖。 【主要元件符號說明】 晶片20 ; 主動電路22; 接合焊墊24 ; 封環30 ; 主動電路區32 ; 冗餘結構34、40 ; 主動傳導線44; 冗餘接孔46 ; 接孔48 ; 保護帶50。 0503-A31125TWF/Edward 13

Claims (1)

1266404 十、申請專利範圍： 1·一積體電路晶片，包含有·· 一主動電路區； 一積體電路，形成在該主動電路區中； 一封環(sealring)結構’至少部份的圍繞該主動電路區；以及 一第-冗餘(dummy)結構’延伸自該封職構並伸人該絲電路區。 2. 如申請專利範圍第！項所述之積體電路晶片，另包含有一接合焊 墊，形成於該主動電路區，其中，部分之該積體電路係置於該接合悍塾下。 3. 如申請專利範圍第2項所述之積體雷 電路係置於部分之該第-冗餘結構下_路曰曰片’其中’部分之該積體 播/如申請專利範15第1項所述之積體電路晶片，其中，該第-冗餘社 構係延伸於主動電路區的傳導線之間。 、… 5. 如巾請專利顧第丨顿述之龍，另包含有 (dummy)結構，延伸自該封環結構並伸人該主動電路區。 —几餘 6. 如申請專利範圍第5項所述之魏電路晶片，其中，部分之該第_ 置於部分之該第—冗餘結構下，該積體電路晶片另包含有一 i 餘接孔(dummy via)，連接該第一與該第二 几 二請專利範除 構係與該第一冗餘結構位於同一層。 餘、、、。 8·如申請專纖Μ 5綱述之雜電u，另包含有： -第三冗縣構，設_主_路， =r-層’且該第三_構係與該第一 _構二= ’其中’該第三餘結 H5C餘結 9·如申請專利範圍第8項所述之積職路晶片 構係位於傳導線的兩部份之間。 10·如申請專利範圍第1項所述之龍電路晶片 0503-A31125TWF/Edward 14 1266404 構具有與該封環結構之部分相同的一材τ 比起鄰近的介電層錄的材料、上述的合^、金射化物、 12· —積體電路晶片，包含有·· 疋述妁、、且口 一主動電路區； 一積體電路，形成在該主動電路區申，· -，環(sealring)結構’至少部份的圍繞該主動電路區丨 二·結構’延伸自_環結構並伸人該絲電路區； -^職dun卿)結構，延伸自該封環結構並伸入該主動電路區，其 中’刀之5亥第一冗餘結構係置於部分之該第一腿結構下；以及 -冗餘接孔(dummy via)，連接該第一與該第二冗餘結構。 13. 如申請專利細第12項所述之積體電路晶片，另包含有一接人焊 塾，形成_絲電路區’財，部分之該積體電路係置於該接合焊墊下。 14. 如申晴專利範圍第12項所述之積體電路晶片，其中，部分之該 體電路係置於部分之該第二冗餘結構下…^ ^ ^ 貝 15. 如申睛專利範圍帛12項所述之積體電路晶片，其中，該第一冗餘 結構係延伸於主動電路區的傳導線之間。 ’、 16. 如申請專利範圍第12項所述之積體電路晶片，其中，該第—冗餘 結構係延伸於主動電路區的傳導線之間。 、 17·如申請專利範圍第12項所述之積體電路晶片，另包含有： 一第二冗餘結構，設於該主動電路區中，該第三冗餘結構與該第—冗 餘結構位於同一層，且該第三冗餘結構係與該第一冗餘結構以及該封環= 構相隔離。 18·如申請專利範圍第π項所述之積體意路晶片，其中，該第三冗餘 結構係位於傳導線的兩部份之間。 0503-A31125TWF/Edwaxd 15 1266404 19. 如申請專利範圍第12項所述之積體 一與該第二冗餘結構都具有與該封環結構之部分相1 片」、中*母 20. -積體電路晶片’包含有： 77目同的材質。 主動電路區； 一積體電路，形成在該主動電路區中； 數個冗餘支柱(pillar)結構，形成於該主動電路區中； -封環㈣ring)結構，至少部份的圍繞該主動電路區；以及 -第-冗餘(dummy)結構’延伸自該封環結構並伸人齡動電路區。
16 0503-A31125TWF/Edward
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